Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9828727 |
1 |
|
|
T33 |
97 |
|
T1 |
59 |
|
T11 |
1733 |
| auto[1] |
7579188 |
1 |
|
|
T33 |
75 |
|
T1 |
20 |
|
T14 |
40098 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14347171 |
1 |
|
|
T33 |
147 |
|
T1 |
69 |
|
T11 |
1733 |
| auto[1] |
3060744 |
1 |
|
|
T33 |
25 |
|
T1 |
10 |
|
T14 |
23191 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9880355 |
1 |
|
|
T33 |
107 |
|
T1 |
64 |
|
T11 |
1733 |
| auto[1] |
7527560 |
1 |
|
|
T33 |
65 |
|
T1 |
15 |
|
T14 |
39926 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2246302 |
1 |
|
|
T33 |
16 |
|
T1 |
5 |
|
T14 |
8086 |
| auto[1] |
auto[0] |
auto[1] |
1538337 |
1 |
|
|
T33 |
16 |
|
T1 |
6 |
|
T14 |
11405 |
| auto[1] |
auto[1] |
auto[0] |
2220514 |
1 |
|
|
T33 |
24 |
|
T14 |
8649 |
|
T15 |
226 |
| auto[1] |
auto[1] |
auto[1] |
1522407 |
1 |
|
|
T33 |
9 |
|
T1 |
4 |
|
T14 |
11786 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |