Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9808654 |
1 |
|
|
T33 |
83 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7599261 |
1 |
|
|
T33 |
89 |
|
T1 |
25 |
|
T14 |
38900 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14325789 |
1 |
|
|
T33 |
116 |
|
T1 |
73 |
|
T11 |
1733 |
| auto[1] |
3082126 |
1 |
|
|
T33 |
56 |
|
T1 |
6 |
|
T14 |
22172 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9849947 |
1 |
|
|
T33 |
59 |
|
T1 |
72 |
|
T11 |
1733 |
| auto[1] |
7557968 |
1 |
|
|
T33 |
113 |
|
T1 |
7 |
|
T14 |
38097 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2238707 |
1 |
|
|
T33 |
31 |
|
T14 |
7930 |
|
T15 |
357 |
| auto[1] |
auto[0] |
auto[1] |
1538423 |
1 |
|
|
T33 |
30 |
|
T1 |
4 |
|
T14 |
11045 |
| auto[1] |
auto[1] |
auto[0] |
2237135 |
1 |
|
|
T33 |
26 |
|
T1 |
1 |
|
T14 |
7995 |
| auto[1] |
auto[1] |
auto[1] |
1543703 |
1 |
|
|
T33 |
26 |
|
T1 |
2 |
|
T14 |
11127 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |