Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9814122 |
1 |
|
|
T33 |
93 |
|
T1 |
55 |
|
T11 |
1733 |
| auto[1] |
7593793 |
1 |
|
|
T33 |
79 |
|
T1 |
24 |
|
T14 |
39423 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14315512 |
1 |
|
|
T33 |
161 |
|
T1 |
68 |
|
T11 |
1733 |
| auto[1] |
3092403 |
1 |
|
|
T33 |
11 |
|
T1 |
11 |
|
T14 |
22165 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9824596 |
1 |
|
|
T33 |
119 |
|
T1 |
61 |
|
T11 |
1733 |
| auto[1] |
7583319 |
1 |
|
|
T33 |
53 |
|
T1 |
18 |
|
T14 |
38962 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2244723 |
1 |
|
|
T33 |
17 |
|
T1 |
7 |
|
T14 |
8675 |
| auto[1] |
auto[0] |
auto[1] |
1546055 |
1 |
|
|
T33 |
3 |
|
T1 |
10 |
|
T14 |
11005 |
| auto[1] |
auto[1] |
auto[0] |
2246193 |
1 |
|
|
T33 |
25 |
|
T14 |
8122 |
|
T15 |
341 |
| auto[1] |
auto[1] |
auto[1] |
1546348 |
1 |
|
|
T33 |
8 |
|
T1 |
1 |
|
T14 |
11160 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |