Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9775940 |
1 |
|
|
T33 |
104 |
|
T1 |
57 |
|
T11 |
1733 |
| auto[1] |
7631975 |
1 |
|
|
T33 |
68 |
|
T1 |
22 |
|
T14 |
40140 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14326779 |
1 |
|
|
T33 |
133 |
|
T1 |
62 |
|
T11 |
1733 |
| auto[1] |
3081136 |
1 |
|
|
T33 |
39 |
|
T1 |
17 |
|
T14 |
23542 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9827557 |
1 |
|
|
T33 |
119 |
|
T1 |
51 |
|
T11 |
1733 |
| auto[1] |
7580358 |
1 |
|
|
T33 |
53 |
|
T1 |
28 |
|
T14 |
40316 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2249305 |
1 |
|
|
T33 |
9 |
|
T1 |
6 |
|
T14 |
8202 |
| auto[1] |
auto[0] |
auto[1] |
1542175 |
1 |
|
|
T33 |
21 |
|
T1 |
12 |
|
T14 |
11134 |
| auto[1] |
auto[1] |
auto[0] |
2249917 |
1 |
|
|
T33 |
5 |
|
T1 |
5 |
|
T14 |
8572 |
| auto[1] |
auto[1] |
auto[1] |
1538961 |
1 |
|
|
T33 |
18 |
|
T1 |
5 |
|
T14 |
12408 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |