Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9820504 |
1 |
|
|
T33 |
73 |
|
T1 |
65 |
|
T11 |
1733 |
| auto[1] |
7587411 |
1 |
|
|
T33 |
99 |
|
T1 |
14 |
|
T14 |
39457 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14323834 |
1 |
|
|
T33 |
144 |
|
T1 |
73 |
|
T11 |
1733 |
| auto[1] |
3084081 |
1 |
|
|
T33 |
28 |
|
T1 |
6 |
|
T14 |
23352 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9837367 |
1 |
|
|
T33 |
69 |
|
T1 |
58 |
|
T11 |
1733 |
| auto[1] |
7570548 |
1 |
|
|
T33 |
103 |
|
T1 |
21 |
|
T14 |
39769 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2235999 |
1 |
|
|
T33 |
24 |
|
T1 |
12 |
|
T14 |
8199 |
| auto[1] |
auto[0] |
auto[1] |
1542243 |
1 |
|
|
T33 |
17 |
|
T1 |
4 |
|
T14 |
11136 |
| auto[1] |
auto[1] |
auto[0] |
2250468 |
1 |
|
|
T33 |
51 |
|
T1 |
3 |
|
T14 |
8218 |
| auto[1] |
auto[1] |
auto[1] |
1541838 |
1 |
|
|
T33 |
11 |
|
T1 |
2 |
|
T14 |
12216 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |