Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9824929 |
1 |
|
|
T33 |
87 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7582986 |
1 |
|
|
T33 |
85 |
|
T1 |
25 |
|
T14 |
38248 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14314348 |
1 |
|
|
T33 |
124 |
|
T1 |
67 |
|
T11 |
1733 |
| auto[1] |
3093567 |
1 |
|
|
T33 |
48 |
|
T1 |
12 |
|
T14 |
22467 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9827217 |
1 |
|
|
T33 |
87 |
|
T1 |
63 |
|
T11 |
1733 |
| auto[1] |
7580698 |
1 |
|
|
T33 |
85 |
|
T1 |
16 |
|
T14 |
38735 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2232114 |
1 |
|
|
T33 |
17 |
|
T14 |
8131 |
|
T15 |
344 |
| auto[1] |
auto[0] |
auto[1] |
1546285 |
1 |
|
|
T33 |
25 |
|
T1 |
7 |
|
T14 |
11156 |
| auto[1] |
auto[1] |
auto[0] |
2255017 |
1 |
|
|
T33 |
20 |
|
T1 |
4 |
|
T14 |
8137 |
| auto[1] |
auto[1] |
auto[1] |
1547282 |
1 |
|
|
T33 |
23 |
|
T1 |
5 |
|
T14 |
11311 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |