Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9813733 |
1 |
|
|
T33 |
126 |
|
T1 |
48 |
|
T11 |
1733 |
| auto[1] |
7594182 |
1 |
|
|
T33 |
46 |
|
T1 |
31 |
|
T14 |
42639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14309379 |
1 |
|
|
T33 |
143 |
|
T1 |
74 |
|
T11 |
1733 |
| auto[1] |
3098536 |
1 |
|
|
T33 |
29 |
|
T1 |
5 |
|
T14 |
22315 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9784431 |
1 |
|
|
T33 |
94 |
|
T1 |
52 |
|
T11 |
1733 |
| auto[1] |
7623484 |
1 |
|
|
T33 |
78 |
|
T1 |
27 |
|
T14 |
38875 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2264270 |
1 |
|
|
T33 |
42 |
|
T1 |
9 |
|
T14 |
7788 |
| auto[1] |
auto[0] |
auto[1] |
1552708 |
1 |
|
|
T33 |
27 |
|
T1 |
1 |
|
T14 |
10507 |
| auto[1] |
auto[1] |
auto[0] |
2260678 |
1 |
|
|
T33 |
7 |
|
T1 |
13 |
|
T14 |
8772 |
| auto[1] |
auto[1] |
auto[1] |
1545828 |
1 |
|
|
T33 |
2 |
|
T1 |
4 |
|
T14 |
11808 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |