Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9793205 |
1 |
|
|
T33 |
70 |
|
T1 |
42 |
|
T11 |
1733 |
| auto[1] |
7614710 |
1 |
|
|
T33 |
102 |
|
T1 |
37 |
|
T14 |
39271 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14326987 |
1 |
|
|
T33 |
154 |
|
T1 |
72 |
|
T11 |
1733 |
| auto[1] |
3080928 |
1 |
|
|
T33 |
18 |
|
T1 |
7 |
|
T14 |
22474 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9847654 |
1 |
|
|
T33 |
120 |
|
T1 |
65 |
|
T11 |
1733 |
| auto[1] |
7560261 |
1 |
|
|
T33 |
52 |
|
T1 |
14 |
|
T14 |
38004 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2234770 |
1 |
|
|
T33 |
15 |
|
T1 |
1 |
|
T14 |
7743 |
| auto[1] |
auto[0] |
auto[1] |
1538970 |
1 |
|
|
T33 |
9 |
|
T1 |
5 |
|
T14 |
10511 |
| auto[1] |
auto[1] |
auto[0] |
2244563 |
1 |
|
|
T33 |
19 |
|
T1 |
6 |
|
T14 |
7787 |
| auto[1] |
auto[1] |
auto[1] |
1541958 |
1 |
|
|
T33 |
9 |
|
T1 |
2 |
|
T14 |
11963 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |