Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9800538 |
1 |
|
|
T33 |
89 |
|
T1 |
53 |
|
T11 |
1733 |
| auto[1] |
7607377 |
1 |
|
|
T33 |
83 |
|
T1 |
26 |
|
T14 |
39971 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14313547 |
1 |
|
|
T33 |
115 |
|
T1 |
76 |
|
T11 |
1733 |
| auto[1] |
3094368 |
1 |
|
|
T33 |
57 |
|
T1 |
3 |
|
T14 |
22479 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9818591 |
1 |
|
|
T33 |
62 |
|
T1 |
59 |
|
T11 |
1733 |
| auto[1] |
7589324 |
1 |
|
|
T33 |
110 |
|
T1 |
20 |
|
T14 |
37809 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2252472 |
1 |
|
|
T33 |
24 |
|
T1 |
10 |
|
T14 |
7527 |
| auto[1] |
auto[0] |
auto[1] |
1551522 |
1 |
|
|
T33 |
27 |
|
T1 |
2 |
|
T14 |
11283 |
| auto[1] |
auto[1] |
auto[0] |
2242484 |
1 |
|
|
T33 |
29 |
|
T1 |
7 |
|
T14 |
7803 |
| auto[1] |
auto[1] |
auto[1] |
1542846 |
1 |
|
|
T33 |
30 |
|
T1 |
1 |
|
T14 |
11196 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |