Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9824498 |
1 |
|
|
T33 |
106 |
|
T1 |
40 |
|
T11 |
1733 |
| auto[1] |
7583417 |
1 |
|
|
T33 |
66 |
|
T1 |
39 |
|
T14 |
40024 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14318372 |
1 |
|
|
T33 |
115 |
|
T1 |
71 |
|
T11 |
1733 |
| auto[1] |
3089543 |
1 |
|
|
T33 |
57 |
|
T1 |
8 |
|
T14 |
22091 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9828389 |
1 |
|
|
T33 |
89 |
|
T1 |
47 |
|
T11 |
1733 |
| auto[1] |
7579526 |
1 |
|
|
T33 |
83 |
|
T1 |
32 |
|
T14 |
38214 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2251858 |
1 |
|
|
T33 |
21 |
|
T1 |
6 |
|
T14 |
7763 |
| auto[1] |
auto[0] |
auto[1] |
1550200 |
1 |
|
|
T33 |
19 |
|
T1 |
2 |
|
T14 |
10110 |
| auto[1] |
auto[1] |
auto[0] |
2238125 |
1 |
|
|
T33 |
5 |
|
T1 |
18 |
|
T14 |
8360 |
| auto[1] |
auto[1] |
auto[1] |
1539343 |
1 |
|
|
T33 |
38 |
|
T1 |
6 |
|
T14 |
11981 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |