Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9823901 |
1 |
|
|
T33 |
67 |
|
T1 |
44 |
|
T11 |
1733 |
| auto[1] |
7584014 |
1 |
|
|
T33 |
105 |
|
T1 |
35 |
|
T14 |
37630 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14324579 |
1 |
|
|
T33 |
136 |
|
T1 |
70 |
|
T11 |
1733 |
| auto[1] |
3083336 |
1 |
|
|
T33 |
36 |
|
T1 |
9 |
|
T14 |
23070 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9850752 |
1 |
|
|
T33 |
114 |
|
T1 |
57 |
|
T11 |
1733 |
| auto[1] |
7557163 |
1 |
|
|
T33 |
58 |
|
T1 |
22 |
|
T14 |
39624 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2243912 |
1 |
|
|
T33 |
10 |
|
T1 |
4 |
|
T14 |
8395 |
| auto[1] |
auto[0] |
auto[1] |
1544955 |
1 |
|
|
T33 |
4 |
|
T1 |
5 |
|
T14 |
11853 |
| auto[1] |
auto[1] |
auto[0] |
2229915 |
1 |
|
|
T33 |
12 |
|
T1 |
9 |
|
T14 |
8159 |
| auto[1] |
auto[1] |
auto[1] |
1538381 |
1 |
|
|
T33 |
32 |
|
T1 |
4 |
|
T14 |
11217 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |