Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9846044 |
1 |
|
|
T33 |
96 |
|
T1 |
59 |
|
T11 |
1733 |
| auto[1] |
7561871 |
1 |
|
|
T33 |
76 |
|
T1 |
20 |
|
T14 |
36614 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14344091 |
1 |
|
|
T33 |
160 |
|
T1 |
68 |
|
T11 |
1733 |
| auto[1] |
3063824 |
1 |
|
|
T33 |
12 |
|
T1 |
11 |
|
T14 |
22321 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9881392 |
1 |
|
|
T33 |
109 |
|
T1 |
51 |
|
T11 |
1733 |
| auto[1] |
7526523 |
1 |
|
|
T33 |
63 |
|
T1 |
28 |
|
T14 |
38990 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2239829 |
1 |
|
|
T33 |
27 |
|
T1 |
7 |
|
T14 |
8929 |
| auto[1] |
auto[0] |
auto[1] |
1535300 |
1 |
|
|
T33 |
7 |
|
T1 |
6 |
|
T14 |
12390 |
| auto[1] |
auto[1] |
auto[0] |
2222870 |
1 |
|
|
T33 |
24 |
|
T1 |
10 |
|
T14 |
7740 |
| auto[1] |
auto[1] |
auto[1] |
1528524 |
1 |
|
|
T33 |
5 |
|
T1 |
5 |
|
T14 |
9931 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |