Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9845022 |
1 |
|
|
T33 |
129 |
|
T1 |
67 |
|
T11 |
1733 |
| auto[1] |
7562893 |
1 |
|
|
T33 |
43 |
|
T1 |
12 |
|
T14 |
38022 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16428998 |
1 |
|
|
T33 |
165 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
978917 |
1 |
|
|
T33 |
7 |
|
T14 |
5085 |
|
T15 |
295 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9808609 |
1 |
|
|
T33 |
94 |
|
T1 |
55 |
|
T11 |
1733 |
| auto[1] |
7599306 |
1 |
|
|
T33 |
78 |
|
T1 |
24 |
|
T14 |
37806 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3339171 |
1 |
|
|
T33 |
45 |
|
T1 |
20 |
|
T14 |
16238 |
| auto[1] |
auto[0] |
auto[1] |
493651 |
1 |
|
|
T33 |
5 |
|
T14 |
2551 |
|
T15 |
160 |
| auto[1] |
auto[1] |
auto[0] |
3281218 |
1 |
|
|
T33 |
26 |
|
T1 |
4 |
|
T14 |
16483 |
| auto[1] |
auto[1] |
auto[1] |
485266 |
1 |
|
|
T33 |
2 |
|
T14 |
2534 |
|
T15 |
135 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |