Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9797387 |
1 |
|
|
T33 |
115 |
|
T1 |
67 |
|
T11 |
1733 |
| auto[1] |
7610528 |
1 |
|
|
T33 |
57 |
|
T1 |
12 |
|
T14 |
39149 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14308289 |
1 |
|
|
T33 |
150 |
|
T1 |
67 |
|
T11 |
1733 |
| auto[1] |
3099626 |
1 |
|
|
T33 |
22 |
|
T1 |
12 |
|
T14 |
22237 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9801985 |
1 |
|
|
T33 |
106 |
|
T1 |
63 |
|
T11 |
1733 |
| auto[1] |
7605930 |
1 |
|
|
T33 |
66 |
|
T1 |
16 |
|
T14 |
38237 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2254906 |
1 |
|
|
T33 |
20 |
|
T1 |
4 |
|
T14 |
8262 |
| auto[1] |
auto[0] |
auto[1] |
1551633 |
1 |
|
|
T33 |
21 |
|
T1 |
7 |
|
T14 |
11362 |
| auto[1] |
auto[1] |
auto[0] |
2251398 |
1 |
|
|
T33 |
24 |
|
T14 |
7738 |
|
T15 |
451 |
| auto[1] |
auto[1] |
auto[1] |
1547993 |
1 |
|
|
T33 |
1 |
|
T1 |
5 |
|
T14 |
10875 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |