Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9835726 |
1 |
|
|
T33 |
120 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7572189 |
1 |
|
|
T33 |
52 |
|
T1 |
25 |
|
T14 |
39346 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14323918 |
1 |
|
|
T33 |
77 |
|
T1 |
66 |
|
T11 |
1733 |
| auto[1] |
3083997 |
1 |
|
|
T33 |
95 |
|
T1 |
13 |
|
T14 |
21998 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9834923 |
1 |
|
|
T33 |
41 |
|
T1 |
56 |
|
T11 |
1733 |
| auto[1] |
7572992 |
1 |
|
|
T33 |
131 |
|
T1 |
23 |
|
T14 |
37642 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2253837 |
1 |
|
|
T33 |
24 |
|
T1 |
1 |
|
T14 |
7352 |
| auto[1] |
auto[0] |
auto[1] |
1548123 |
1 |
|
|
T33 |
67 |
|
T1 |
8 |
|
T14 |
10564 |
| auto[1] |
auto[1] |
auto[0] |
2235158 |
1 |
|
|
T33 |
12 |
|
T1 |
9 |
|
T14 |
8292 |
| auto[1] |
auto[1] |
auto[1] |
1535874 |
1 |
|
|
T33 |
28 |
|
T1 |
5 |
|
T14 |
11434 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |