Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9819242 |
1 |
|
|
T33 |
54 |
|
T1 |
58 |
|
T11 |
1733 |
| auto[1] |
7588673 |
1 |
|
|
T33 |
118 |
|
T1 |
21 |
|
T14 |
37785 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14330464 |
1 |
|
|
T33 |
150 |
|
T1 |
49 |
|
T11 |
1733 |
| auto[1] |
3077451 |
1 |
|
|
T33 |
22 |
|
T1 |
30 |
|
T14 |
22549 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9849051 |
1 |
|
|
T33 |
119 |
|
T1 |
46 |
|
T11 |
1733 |
| auto[1] |
7558864 |
1 |
|
|
T33 |
53 |
|
T1 |
33 |
|
T14 |
38116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2238553 |
1 |
|
|
T1 |
2 |
|
T14 |
8001 |
|
T15 |
330 |
| auto[1] |
auto[0] |
auto[1] |
1537519 |
1 |
|
|
T33 |
3 |
|
T1 |
18 |
|
T14 |
12194 |
| auto[1] |
auto[1] |
auto[0] |
2242860 |
1 |
|
|
T33 |
31 |
|
T1 |
1 |
|
T14 |
7566 |
| auto[1] |
auto[1] |
auto[1] |
1539932 |
1 |
|
|
T33 |
19 |
|
T1 |
12 |
|
T14 |
10355 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |