Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9854635 |
1 |
|
|
T33 |
70 |
|
T1 |
46 |
|
T11 |
1733 |
| auto[1] |
7553280 |
1 |
|
|
T33 |
102 |
|
T1 |
33 |
|
T14 |
37265 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16430042 |
1 |
|
|
T33 |
164 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
977873 |
1 |
|
|
T33 |
8 |
|
T1 |
1 |
|
T14 |
5246 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9816928 |
1 |
|
|
T33 |
49 |
|
T1 |
60 |
|
T11 |
1733 |
| auto[1] |
7590987 |
1 |
|
|
T33 |
123 |
|
T1 |
19 |
|
T14 |
37665 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3326463 |
1 |
|
|
T33 |
53 |
|
T1 |
5 |
|
T14 |
17048 |
| auto[1] |
auto[0] |
auto[1] |
492088 |
1 |
|
|
T33 |
6 |
|
T1 |
1 |
|
T14 |
2818 |
| auto[1] |
auto[1] |
auto[0] |
3286651 |
1 |
|
|
T33 |
62 |
|
T1 |
13 |
|
T14 |
15371 |
| auto[1] |
auto[1] |
auto[1] |
485785 |
1 |
|
|
T33 |
2 |
|
T14 |
2428 |
|
T15 |
119 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |