Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9809800 |
1 |
|
|
T33 |
100 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7598115 |
1 |
|
|
T33 |
72 |
|
T1 |
25 |
|
T14 |
36906 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16424217 |
1 |
|
|
T33 |
163 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
983698 |
1 |
|
|
T33 |
9 |
|
T14 |
5237 |
|
T15 |
291 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9783298 |
1 |
|
|
T33 |
65 |
|
T1 |
62 |
|
T11 |
1733 |
| auto[1] |
7624617 |
1 |
|
|
T33 |
107 |
|
T1 |
17 |
|
T14 |
39078 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3330431 |
1 |
|
|
T33 |
58 |
|
T1 |
9 |
|
T14 |
18599 |
| auto[1] |
auto[0] |
auto[1] |
492124 |
1 |
|
|
T33 |
7 |
|
T14 |
2969 |
|
T15 |
145 |
| auto[1] |
auto[1] |
auto[0] |
3310488 |
1 |
|
|
T33 |
40 |
|
T1 |
8 |
|
T14 |
15242 |
| auto[1] |
auto[1] |
auto[1] |
491574 |
1 |
|
|
T33 |
2 |
|
T14 |
2268 |
|
T15 |
146 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |