Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9831865 |
1 |
|
|
T33 |
103 |
|
T1 |
49 |
|
T11 |
1733 |
| auto[1] |
7576050 |
1 |
|
|
T33 |
69 |
|
T1 |
30 |
|
T14 |
38704 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16430115 |
1 |
|
|
T33 |
164 |
|
T1 |
77 |
|
T11 |
1733 |
| auto[1] |
977800 |
1 |
|
|
T33 |
8 |
|
T1 |
2 |
|
T14 |
5437 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9823280 |
1 |
|
|
T33 |
49 |
|
T1 |
51 |
|
T11 |
1733 |
| auto[1] |
7584635 |
1 |
|
|
T33 |
123 |
|
T1 |
28 |
|
T14 |
38744 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3305488 |
1 |
|
|
T33 |
81 |
|
T1 |
14 |
|
T14 |
17495 |
| auto[1] |
auto[0] |
auto[1] |
488042 |
1 |
|
|
T33 |
3 |
|
T1 |
1 |
|
T14 |
2881 |
| auto[1] |
auto[1] |
auto[0] |
3301347 |
1 |
|
|
T33 |
34 |
|
T1 |
12 |
|
T14 |
15812 |
| auto[1] |
auto[1] |
auto[1] |
489758 |
1 |
|
|
T33 |
5 |
|
T1 |
1 |
|
T14 |
2556 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |