Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9824213 |
1 |
|
|
T33 |
93 |
|
T1 |
58 |
|
T11 |
1733 |
| auto[1] |
7583702 |
1 |
|
|
T33 |
79 |
|
T1 |
21 |
|
T14 |
39736 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16427921 |
1 |
|
|
T33 |
165 |
|
T1 |
77 |
|
T11 |
1733 |
| auto[1] |
979994 |
1 |
|
|
T33 |
7 |
|
T1 |
2 |
|
T14 |
5245 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9813908 |
1 |
|
|
T33 |
71 |
|
T1 |
59 |
|
T11 |
1733 |
| auto[1] |
7594007 |
1 |
|
|
T33 |
101 |
|
T1 |
20 |
|
T14 |
38928 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3314967 |
1 |
|
|
T33 |
49 |
|
T1 |
11 |
|
T14 |
16392 |
| auto[1] |
auto[0] |
auto[1] |
491566 |
1 |
|
|
T33 |
1 |
|
T1 |
1 |
|
T14 |
2476 |
| auto[1] |
auto[1] |
auto[0] |
3299046 |
1 |
|
|
T33 |
45 |
|
T1 |
7 |
|
T14 |
17291 |
| auto[1] |
auto[1] |
auto[1] |
488428 |
1 |
|
|
T33 |
6 |
|
T1 |
1 |
|
T14 |
2769 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |