Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9796574 |
1 |
|
|
T33 |
141 |
|
T1 |
63 |
|
T11 |
1733 |
| auto[1] |
7611341 |
1 |
|
|
T33 |
31 |
|
T1 |
16 |
|
T14 |
38701 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16435861 |
1 |
|
|
T33 |
165 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
972054 |
1 |
|
|
T33 |
7 |
|
T14 |
5145 |
|
T15 |
349 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9849023 |
1 |
|
|
T33 |
60 |
|
T1 |
63 |
|
T11 |
1733 |
| auto[1] |
7558892 |
1 |
|
|
T33 |
112 |
|
T1 |
16 |
|
T14 |
38491 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3289471 |
1 |
|
|
T33 |
91 |
|
T1 |
10 |
|
T14 |
16567 |
| auto[1] |
auto[0] |
auto[1] |
484826 |
1 |
|
|
T33 |
6 |
|
T14 |
2539 |
|
T15 |
183 |
| auto[1] |
auto[1] |
auto[0] |
3297367 |
1 |
|
|
T33 |
14 |
|
T1 |
6 |
|
T14 |
16779 |
| auto[1] |
auto[1] |
auto[1] |
487228 |
1 |
|
|
T33 |
1 |
|
T14 |
2606 |
|
T15 |
166 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |