Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9799796 |
1 |
|
|
T33 |
52 |
|
T1 |
57 |
|
T11 |
1733 |
| auto[1] |
7608119 |
1 |
|
|
T33 |
120 |
|
T1 |
22 |
|
T14 |
38022 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16433447 |
1 |
|
|
T33 |
161 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
974468 |
1 |
|
|
T33 |
11 |
|
T14 |
5519 |
|
T15 |
215 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9830729 |
1 |
|
|
T33 |
68 |
|
T1 |
63 |
|
T11 |
1733 |
| auto[1] |
7577186 |
1 |
|
|
T33 |
104 |
|
T1 |
16 |
|
T14 |
40478 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3298221 |
1 |
|
|
T33 |
28 |
|
T1 |
9 |
|
T14 |
17903 |
| auto[1] |
auto[0] |
auto[1] |
486571 |
1 |
|
|
T33 |
3 |
|
T14 |
2815 |
|
T15 |
112 |
| auto[1] |
auto[1] |
auto[0] |
3304497 |
1 |
|
|
T33 |
65 |
|
T1 |
7 |
|
T14 |
17056 |
| auto[1] |
auto[1] |
auto[1] |
487897 |
1 |
|
|
T33 |
8 |
|
T14 |
2704 |
|
T15 |
103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |