Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 948
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T763 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.99036241 Jul 03 04:24:54 PM PDT 24 Jul 03 04:24:56 PM PDT 24 77515018 ps
T764 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1779816418 Jul 03 04:25:24 PM PDT 24 Jul 03 04:25:25 PM PDT 24 27143400 ps
T765 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.342911337 Jul 03 04:26:12 PM PDT 24 Jul 03 04:26:15 PM PDT 24 27213013 ps
T106 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3457980549 Jul 03 04:25:18 PM PDT 24 Jul 03 04:25:19 PM PDT 24 58598384 ps
T766 /workspace/coverage/cover_reg_top/22.gpio_intr_test.548703841 Jul 03 04:25:41 PM PDT 24 Jul 03 04:25:42 PM PDT 24 42310910 ps
T107 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2101522354 Jul 03 04:25:00 PM PDT 24 Jul 03 04:25:01 PM PDT 24 32071088 ps
T767 /workspace/coverage/cover_reg_top/36.gpio_intr_test.1850664747 Jul 03 04:25:31 PM PDT 24 Jul 03 04:25:32 PM PDT 24 26370881 ps
T52 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1754528103 Jul 03 04:25:16 PM PDT 24 Jul 03 04:25:17 PM PDT 24 698018368 ps
T130 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.445382888 Jul 03 04:25:13 PM PDT 24 Jul 03 04:25:15 PM PDT 24 92175698 ps
T768 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3889225935 Jul 03 04:25:06 PM PDT 24 Jul 03 04:25:09 PM PDT 24 323305777 ps
T53 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3024379086 Jul 03 04:25:11 PM PDT 24 Jul 03 04:25:12 PM PDT 24 136514458 ps
T50 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3816228228 Jul 03 04:25:03 PM PDT 24 Jul 03 04:25:04 PM PDT 24 450955969 ps
T51 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2426137048 Jul 03 04:26:23 PM PDT 24 Jul 03 04:26:25 PM PDT 24 667489001 ps
T769 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2575651816 Jul 03 04:25:02 PM PDT 24 Jul 03 04:25:03 PM PDT 24 43784168 ps
T770 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3713452788 Jul 03 04:25:18 PM PDT 24 Jul 03 04:25:19 PM PDT 24 12873405 ps
T108 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3879940839 Jul 03 04:25:11 PM PDT 24 Jul 03 04:25:12 PM PDT 24 14786794 ps
T771 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1937963029 Jul 03 04:26:29 PM PDT 24 Jul 03 04:26:32 PM PDT 24 119751080 ps
T772 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4210952998 Jul 03 04:25:15 PM PDT 24 Jul 03 04:25:16 PM PDT 24 18295009 ps
T773 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4192584263 Jul 03 04:25:12 PM PDT 24 Jul 03 04:25:12 PM PDT 24 62709146 ps
T774 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2593568649 Jul 03 04:24:52 PM PDT 24 Jul 03 04:24:54 PM PDT 24 331072084 ps
T775 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2815842110 Jul 03 04:25:11 PM PDT 24 Jul 03 04:25:13 PM PDT 24 93893953 ps
T776 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1985782881 Jul 03 04:25:15 PM PDT 24 Jul 03 04:25:16 PM PDT 24 21411177 ps
T777 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3382189542 Jul 03 04:25:21 PM PDT 24 Jul 03 04:25:23 PM PDT 24 47082761 ps
T778 /workspace/coverage/cover_reg_top/3.gpio_intr_test.582136605 Jul 03 04:26:12 PM PDT 24 Jul 03 04:26:14 PM PDT 24 15591249 ps
T779 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2904523385 Jul 03 04:25:19 PM PDT 24 Jul 03 04:25:20 PM PDT 24 16065605 ps
T780 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1932983152 Jul 03 04:24:53 PM PDT 24 Jul 03 04:24:54 PM PDT 24 43021068 ps
T781 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3879190503 Jul 03 04:26:05 PM PDT 24 Jul 03 04:26:06 PM PDT 24 41480315 ps
T782 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1573753846 Jul 03 04:24:51 PM PDT 24 Jul 03 04:24:52 PM PDT 24 47297721 ps
T783 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1385049075 Jul 03 04:25:03 PM PDT 24 Jul 03 04:25:04 PM PDT 24 11429982 ps
T784 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1924507355 Jul 03 04:25:20 PM PDT 24 Jul 03 04:25:22 PM PDT 24 119131795 ps
T785 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1562281564 Jul 03 04:25:17 PM PDT 24 Jul 03 04:25:18 PM PDT 24 11900179 ps
T786 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2196704218 Jul 03 04:25:05 PM PDT 24 Jul 03 04:25:07 PM PDT 24 33095675 ps
T787 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2344164018 Jul 03 04:24:48 PM PDT 24 Jul 03 04:24:51 PM PDT 24 258747650 ps
T109 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1514860126 Jul 03 04:25:07 PM PDT 24 Jul 03 04:25:08 PM PDT 24 23512943 ps
T788 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3122645683 Jul 03 04:25:10 PM PDT 24 Jul 03 04:25:12 PM PDT 24 37191053 ps
T789 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3226890390 Jul 03 04:25:07 PM PDT 24 Jul 03 04:25:09 PM PDT 24 32759057 ps
T790 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.894730520 Jul 03 04:25:03 PM PDT 24 Jul 03 04:25:04 PM PDT 24 45332642 ps
T791 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.289722814 Jul 03 04:25:22 PM PDT 24 Jul 03 04:25:23 PM PDT 24 162412091 ps
T792 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1476096286 Jul 03 04:25:08 PM PDT 24 Jul 03 04:25:09 PM PDT 24 103948970 ps
T793 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2146529278 Jul 03 04:25:02 PM PDT 24 Jul 03 04:25:03 PM PDT 24 16312157 ps
T794 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2870426016 Jul 03 04:26:24 PM PDT 24 Jul 03 04:26:26 PM PDT 24 32062620 ps
T795 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2921643659 Jul 03 04:25:30 PM PDT 24 Jul 03 04:25:32 PM PDT 24 13195533 ps
T796 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1673358655 Jul 03 04:24:51 PM PDT 24 Jul 03 04:24:52 PM PDT 24 15624664 ps
T797 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2860819368 Jul 03 04:25:15 PM PDT 24 Jul 03 04:25:17 PM PDT 24 262262893 ps
T112 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1499928077 Jul 03 04:24:53 PM PDT 24 Jul 03 04:24:54 PM PDT 24 12223173 ps
T798 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3602866499 Jul 03 04:24:52 PM PDT 24 Jul 03 04:24:53 PM PDT 24 15767546 ps
T799 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4201586788 Jul 03 04:25:01 PM PDT 24 Jul 03 04:25:03 PM PDT 24 101643247 ps
T800 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4258428800 Jul 03 04:25:20 PM PDT 24 Jul 03 04:25:22 PM PDT 24 81820192 ps
T801 /workspace/coverage/cover_reg_top/41.gpio_intr_test.97589323 Jul 03 04:25:24 PM PDT 24 Jul 03 04:25:26 PM PDT 24 13375367 ps
T802 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3211831721 Jul 03 04:25:01 PM PDT 24 Jul 03 04:25:02 PM PDT 24 127176793 ps
T803 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1426710775 Jul 03 04:25:13 PM PDT 24 Jul 03 04:25:14 PM PDT 24 177160502 ps
T804 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2425135733 Jul 03 04:24:52 PM PDT 24 Jul 03 04:24:53 PM PDT 24 53844941 ps
T805 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1853819775 Jul 03 04:25:13 PM PDT 24 Jul 03 04:25:16 PM PDT 24 202065885 ps
T806 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1475710454 Jul 03 04:26:26 PM PDT 24 Jul 03 04:26:29 PM PDT 24 291553969 ps
T807 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1715867541 Jul 03 04:24:35 PM PDT 24 Jul 03 04:24:36 PM PDT 24 21221576 ps
T808 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3462604496 Jul 03 04:25:21 PM PDT 24 Jul 03 04:25:23 PM PDT 24 17560364 ps
T809 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1766246471 Jul 03 04:25:00 PM PDT 24 Jul 03 04:25:01 PM PDT 24 11692515 ps
T810 /workspace/coverage/cover_reg_top/29.gpio_intr_test.578703954 Jul 03 04:25:26 PM PDT 24 Jul 03 04:25:28 PM PDT 24 104458843 ps
T811 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2286939876 Jul 03 04:25:03 PM PDT 24 Jul 03 04:25:05 PM PDT 24 70284008 ps
T812 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3104313816 Jul 03 04:25:15 PM PDT 24 Jul 03 04:25:16 PM PDT 24 24124363 ps
T813 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1187190601 Jul 03 04:25:18 PM PDT 24 Jul 03 04:25:19 PM PDT 24 13608482 ps
T814 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3220269321 Jul 03 04:25:17 PM PDT 24 Jul 03 04:25:18 PM PDT 24 17235077 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1381504139 Jul 03 04:25:25 PM PDT 24 Jul 03 04:25:28 PM PDT 24 276958164 ps
T816 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2335815702 Jul 03 04:25:29 PM PDT 24 Jul 03 04:25:31 PM PDT 24 157349229 ps
T817 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3981851669 Jul 03 04:24:59 PM PDT 24 Jul 03 04:25:00 PM PDT 24 53344840 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1046088768 Jul 03 04:24:55 PM PDT 24 Jul 03 04:24:56 PM PDT 24 112523341 ps
T819 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1651785118 Jul 03 04:25:12 PM PDT 24 Jul 03 04:25:13 PM PDT 24 21954684 ps
T820 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1496005743 Jul 03 04:24:59 PM PDT 24 Jul 03 04:25:00 PM PDT 24 176780706 ps
T821 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1198820971 Jul 03 04:25:24 PM PDT 24 Jul 03 04:25:31 PM PDT 24 29686622 ps
T110 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1075247284 Jul 03 04:26:34 PM PDT 24 Jul 03 04:26:35 PM PDT 24 64060690 ps
T822 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1489157196 Jul 03 04:26:29 PM PDT 24 Jul 03 04:26:31 PM PDT 24 25904016 ps
T823 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3623269127 Jul 03 04:25:03 PM PDT 24 Jul 03 04:25:06 PM PDT 24 265663638 ps
T824 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2272745143 Jul 03 04:26:31 PM PDT 24 Jul 03 04:26:32 PM PDT 24 29625046 ps
T825 /workspace/coverage/cover_reg_top/5.gpio_intr_test.530962549 Jul 03 04:24:59 PM PDT 24 Jul 03 04:24:59 PM PDT 24 33572925 ps
T826 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1430695208 Jul 03 04:24:50 PM PDT 24 Jul 03 04:24:51 PM PDT 24 23597263 ps
T827 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.481673013 Jul 03 04:25:19 PM PDT 24 Jul 03 04:25:20 PM PDT 24 68716796 ps
T828 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1513182041 Jul 03 04:25:09 PM PDT 24 Jul 03 04:25:10 PM PDT 24 63680648 ps
T829 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.565885145 Jul 03 04:25:16 PM PDT 24 Jul 03 04:25:17 PM PDT 24 118639993 ps
T830 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1431363411 Jul 03 04:26:27 PM PDT 24 Jul 03 04:26:28 PM PDT 24 18374178 ps
T831 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1920985322 Jul 03 04:25:12 PM PDT 24 Jul 03 04:25:13 PM PDT 24 59656090 ps
T832 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1021167663 Jul 03 04:24:53 PM PDT 24 Jul 03 04:24:54 PM PDT 24 31087566 ps
T833 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2561464275 Jul 03 04:25:10 PM PDT 24 Jul 03 04:25:11 PM PDT 24 78530835 ps
T834 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3319985079 Jul 03 04:25:16 PM PDT 24 Jul 03 04:25:18 PM PDT 24 258527670 ps
T835 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1443144172 Jul 03 04:25:21 PM PDT 24 Jul 03 04:25:23 PM PDT 24 15720066 ps
T836 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.703500656 Jul 03 04:25:20 PM PDT 24 Jul 03 04:25:22 PM PDT 24 1485081348 ps
T837 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1261836225 Jul 03 04:25:13 PM PDT 24 Jul 03 04:25:14 PM PDT 24 57602998 ps
T838 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2632270025 Jul 03 04:25:11 PM PDT 24 Jul 03 04:25:12 PM PDT 24 11385292 ps
T839 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3782584593 Jul 03 04:24:50 PM PDT 24 Jul 03 04:24:52 PM PDT 24 19786035 ps
T111 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.242602677 Jul 03 04:25:05 PM PDT 24 Jul 03 04:25:06 PM PDT 24 47336005 ps
T840 /workspace/coverage/cover_reg_top/20.gpio_intr_test.4036296397 Jul 03 04:25:08 PM PDT 24 Jul 03 04:25:14 PM PDT 24 13323141 ps
T841 /workspace/coverage/cover_reg_top/39.gpio_intr_test.313091423 Jul 03 04:25:24 PM PDT 24 Jul 03 04:25:26 PM PDT 24 43406698 ps
T842 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1965698678 Jul 03 04:25:07 PM PDT 24 Jul 03 04:25:08 PM PDT 24 138272983 ps
T843 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.743649930 Jul 03 04:25:12 PM PDT 24 Jul 03 04:25:13 PM PDT 24 47158455 ps
T844 /workspace/coverage/cover_reg_top/46.gpio_intr_test.498958585 Jul 03 04:25:27 PM PDT 24 Jul 03 04:25:29 PM PDT 24 18766383 ps
T845 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2099618065 Jul 03 04:25:15 PM PDT 24 Jul 03 04:25:16 PM PDT 24 19043980 ps
T846 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2196988368 Jul 03 04:25:17 PM PDT 24 Jul 03 04:25:18 PM PDT 24 45901782 ps
T847 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3013617700 Jul 03 04:25:17 PM PDT 24 Jul 03 04:25:18 PM PDT 24 51842421 ps
T848 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1352521361 Jul 03 04:25:02 PM PDT 24 Jul 03 04:25:03 PM PDT 24 48523520 ps
T849 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1473751263 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 255915047 ps
T850 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2978454246 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:42 PM PDT 24 42373527 ps
T851 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2083128958 Jul 03 04:47:51 PM PDT 24 Jul 03 04:47:52 PM PDT 24 272938346 ps
T852 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3917474262 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 82710353 ps
T853 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.293156418 Jul 03 04:47:39 PM PDT 24 Jul 03 04:47:41 PM PDT 24 158212167 ps
T854 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1592875393 Jul 03 04:47:47 PM PDT 24 Jul 03 04:47:48 PM PDT 24 35074949 ps
T855 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1975891391 Jul 03 04:47:36 PM PDT 24 Jul 03 04:47:37 PM PDT 24 139992205 ps
T856 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2618113675 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:38 PM PDT 24 39151914 ps
T857 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3869996261 Jul 03 04:47:47 PM PDT 24 Jul 03 04:47:49 PM PDT 24 270711581 ps
T858 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.65998736 Jul 03 04:47:45 PM PDT 24 Jul 03 04:47:47 PM PDT 24 55824371 ps
T859 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4072313498 Jul 03 04:47:46 PM PDT 24 Jul 03 04:47:48 PM PDT 24 250054368 ps
T860 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.208600225 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 81006617 ps
T861 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1493989188 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 79540081 ps
T862 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1350816781 Jul 03 04:47:45 PM PDT 24 Jul 03 04:47:46 PM PDT 24 165112141 ps
T863 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2507621118 Jul 03 04:47:39 PM PDT 24 Jul 03 04:47:41 PM PDT 24 70562028 ps
T864 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1105964147 Jul 03 04:47:48 PM PDT 24 Jul 03 04:47:49 PM PDT 24 222080339 ps
T865 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.849019305 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:36 PM PDT 24 21478453 ps
T866 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2344611867 Jul 03 04:47:42 PM PDT 24 Jul 03 04:47:43 PM PDT 24 40142325 ps
T867 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1408644289 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:36 PM PDT 24 54232079 ps
T868 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1250876077 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:36 PM PDT 24 57897109 ps
T869 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.653735941 Jul 03 04:47:36 PM PDT 24 Jul 03 04:47:38 PM PDT 24 76488910 ps
T870 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3798522038 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:37 PM PDT 24 108579209 ps
T871 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3675346783 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 163320638 ps
T872 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.344049779 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 156234916 ps
T873 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4099663962 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 30229773 ps
T874 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3045355745 Jul 03 04:47:38 PM PDT 24 Jul 03 04:47:40 PM PDT 24 361268854 ps
T875 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2799306178 Jul 03 04:47:43 PM PDT 24 Jul 03 04:47:45 PM PDT 24 265597889 ps
T876 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.905495087 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 89994761 ps
T877 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4235434885 Jul 03 04:47:43 PM PDT 24 Jul 03 04:47:45 PM PDT 24 151139953 ps
T878 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.715928086 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:42 PM PDT 24 349933030 ps
T879 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2942684147 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:36 PM PDT 24 77928998 ps
T880 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.793772358 Jul 03 04:47:48 PM PDT 24 Jul 03 04:47:50 PM PDT 24 55644350 ps
T881 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2104165014 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 156473775 ps
T882 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1081539653 Jul 03 04:47:39 PM PDT 24 Jul 03 04:47:41 PM PDT 24 56220375 ps
T883 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4230984205 Jul 03 04:47:46 PM PDT 24 Jul 03 04:47:47 PM PDT 24 56480308 ps
T884 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3576416810 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:42 PM PDT 24 76986044 ps
T885 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1021708590 Jul 03 04:47:42 PM PDT 24 Jul 03 04:47:44 PM PDT 24 241178005 ps
T886 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3952057599 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:41 PM PDT 24 105019230 ps
T887 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2667075941 Jul 03 04:47:48 PM PDT 24 Jul 03 04:47:50 PM PDT 24 255973215 ps
T888 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.819871227 Jul 03 04:47:41 PM PDT 24 Jul 03 04:47:43 PM PDT 24 298849737 ps
T889 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3856244381 Jul 03 04:47:41 PM PDT 24 Jul 03 04:47:42 PM PDT 24 888106708 ps
T890 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1142689958 Jul 03 04:47:45 PM PDT 24 Jul 03 04:47:46 PM PDT 24 102720264 ps
T891 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1435095726 Jul 03 04:47:30 PM PDT 24 Jul 03 04:47:32 PM PDT 24 30580120 ps
T892 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1236530601 Jul 03 04:47:48 PM PDT 24 Jul 03 04:47:49 PM PDT 24 76629044 ps
T893 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1244465806 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 179539716 ps
T894 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.463738395 Jul 03 04:47:47 PM PDT 24 Jul 03 04:47:48 PM PDT 24 209101951 ps
T895 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2946645129 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:40 PM PDT 24 199488396 ps
T896 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.458751399 Jul 03 04:47:41 PM PDT 24 Jul 03 04:47:42 PM PDT 24 179944246 ps
T897 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3363050639 Jul 03 04:47:33 PM PDT 24 Jul 03 04:47:34 PM PDT 24 31952764 ps
T898 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2186970808 Jul 03 04:47:45 PM PDT 24 Jul 03 04:47:46 PM PDT 24 54458830 ps
T899 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1589694296 Jul 03 04:47:49 PM PDT 24 Jul 03 04:47:50 PM PDT 24 119782755 ps
T900 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3800809270 Jul 03 04:47:33 PM PDT 24 Jul 03 04:47:35 PM PDT 24 239871925 ps
T901 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2267092974 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 98221368 ps
T902 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2979658100 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:42 PM PDT 24 27690216 ps
T903 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1179329231 Jul 03 04:47:39 PM PDT 24 Jul 03 04:47:41 PM PDT 24 109200197 ps
T904 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1028777448 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 133703844 ps
T905 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4107957735 Jul 03 04:47:38 PM PDT 24 Jul 03 04:47:39 PM PDT 24 93632829 ps
T906 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1461401325 Jul 03 04:47:43 PM PDT 24 Jul 03 04:47:44 PM PDT 24 82424911 ps
T907 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2268904992 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 73720173 ps
T908 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.67263139 Jul 03 04:47:30 PM PDT 24 Jul 03 04:47:31 PM PDT 24 27917735 ps
T909 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.153147740 Jul 03 04:47:46 PM PDT 24 Jul 03 04:47:47 PM PDT 24 34876635 ps
T910 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4240764249 Jul 03 04:47:42 PM PDT 24 Jul 03 04:47:43 PM PDT 24 32273766 ps
T911 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1102327845 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:35 PM PDT 24 30071772 ps
T912 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1527131239 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 91189160 ps
T913 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3320130470 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 180769596 ps
T914 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1663657965 Jul 03 04:47:44 PM PDT 24 Jul 03 04:47:46 PM PDT 24 59985657 ps
T915 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3427626369 Jul 03 04:47:31 PM PDT 24 Jul 03 04:47:33 PM PDT 24 127863201 ps
T916 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3361906110 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:36 PM PDT 24 45087945 ps
T917 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1392364163 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:42 PM PDT 24 41393703 ps
T918 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2722764839 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:42 PM PDT 24 142475814 ps
T919 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3469623764 Jul 03 04:47:41 PM PDT 24 Jul 03 04:47:43 PM PDT 24 86401653 ps
T920 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1737356886 Jul 03 04:47:47 PM PDT 24 Jul 03 04:47:48 PM PDT 24 65669009 ps
T921 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2906425421 Jul 03 04:47:43 PM PDT 24 Jul 03 04:47:44 PM PDT 24 66721276 ps
T922 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1038943121 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 277610394 ps
T923 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2896798913 Jul 03 04:47:44 PM PDT 24 Jul 03 04:47:46 PM PDT 24 31856908 ps
T924 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224542176 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:42 PM PDT 24 70575633 ps
T925 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2288706127 Jul 03 04:47:42 PM PDT 24 Jul 03 04:47:44 PM PDT 24 38080864 ps
T926 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3460183895 Jul 03 04:47:43 PM PDT 24 Jul 03 04:47:45 PM PDT 24 37624117 ps
T927 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1487807618 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:36 PM PDT 24 127362157 ps
T928 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1495010129 Jul 03 04:47:38 PM PDT 24 Jul 03 04:47:40 PM PDT 24 492189782 ps
T929 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3421765662 Jul 03 04:47:44 PM PDT 24 Jul 03 04:47:45 PM PDT 24 58864008 ps
T930 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1405367664 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 112261861 ps
T931 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1985732698 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:41 PM PDT 24 70590907 ps
T932 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1700535789 Jul 03 04:47:41 PM PDT 24 Jul 03 04:47:43 PM PDT 24 62671124 ps
T933 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.998817846 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:42 PM PDT 24 212816520 ps
T934 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4252704791 Jul 03 04:47:42 PM PDT 24 Jul 03 04:47:43 PM PDT 24 65091313 ps
T935 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3934683991 Jul 03 04:47:39 PM PDT 24 Jul 03 04:47:41 PM PDT 24 37517841 ps
T936 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2209298356 Jul 03 04:47:43 PM PDT 24 Jul 03 04:47:45 PM PDT 24 150120293 ps
T937 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3242720022 Jul 03 04:47:39 PM PDT 24 Jul 03 04:47:40 PM PDT 24 36756862 ps
T938 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3053987807 Jul 03 04:47:45 PM PDT 24 Jul 03 04:47:47 PM PDT 24 320253906 ps
T939 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3438976450 Jul 03 04:47:39 PM PDT 24 Jul 03 04:47:41 PM PDT 24 164113656 ps
T940 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3826387915 Jul 03 04:47:43 PM PDT 24 Jul 03 04:47:44 PM PDT 24 37952911 ps
T941 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3758880548 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 159099000 ps
T942 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3146098679 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 164102411 ps
T943 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3070311140 Jul 03 04:47:43 PM PDT 24 Jul 03 04:47:45 PM PDT 24 114190844 ps
T944 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2837865692 Jul 03 04:47:35 PM PDT 24 Jul 03 04:47:37 PM PDT 24 239663977 ps
T945 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.956978461 Jul 03 04:47:44 PM PDT 24 Jul 03 04:47:46 PM PDT 24 33319688 ps
T946 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2091249700 Jul 03 04:47:36 PM PDT 24 Jul 03 04:47:38 PM PDT 24 143174715 ps
T947 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037842125 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:36 PM PDT 24 53086555 ps
T948 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1216344987 Jul 03 04:47:40 PM PDT 24 Jul 03 04:47:42 PM PDT 24 51685799 ps

Test location /workspace/coverage/default/36.gpio_full_random.1775000918
Short name T1
Test name
Test status
Simulation time 205148798 ps
CPU time 0.82 seconds
Started Jul 03 04:26:33 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 196628 kb
Host smart-09060815-fca5-4603-a9f8-6ec2e5f2494e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775000918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1775000918
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3677021759
Short name T34
Test name
Test status
Simulation time 149942188176 ps
CPU time 1829.77 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:56:12 PM PDT 24
Peak memory 198772 kb
Host smart-a94811eb-2d23-4894-ab66-f2e6b72358c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3677021759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3677021759
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4154314803
Short name T11
Test name
Test status
Simulation time 473211875 ps
CPU time 3.52 seconds
Started Jul 03 04:25:19 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 198704 kb
Host smart-1a13d708-2faf-447d-929e-b55f55ae1954
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154314803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4154314803
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3996953550
Short name T42
Test name
Test status
Simulation time 64979417 ps
CPU time 0.84 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 214160 kb
Host smart-04e55ae8-4728-4582-88a9-b17f5b3ec44c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996953550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3996953550
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.476460123
Short name T93
Test name
Test status
Simulation time 56598635 ps
CPU time 0.67 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 195768 kb
Host smart-f1581228-adbd-4263-9506-b09efc6204d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476460123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.476460123
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2949838593
Short name T48
Test name
Test status
Simulation time 113445089 ps
CPU time 1.37 seconds
Started Jul 03 04:25:16 PM PDT 24
Finished Jul 03 04:25:18 PM PDT 24
Peak memory 198448 kb
Host smart-3276c14a-e258-4774-9177-3da42f0a0b93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949838593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2949838593
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1927767453
Short name T2
Test name
Test status
Simulation time 6535665697 ps
CPU time 52.04 seconds
Started Jul 03 04:25:47 PM PDT 24
Finished Jul 03 04:26:40 PM PDT 24
Peak memory 198652 kb
Host smart-18cceb6f-7b42-43b7-98bf-e90c105c2b1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927767453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1927767453
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2481744598
Short name T171
Test name
Test status
Simulation time 12131606 ps
CPU time 0.6 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 194536 kb
Host smart-cadcf071-50db-4769-bec5-42b853da4b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481744598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2481744598
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3657107039
Short name T120
Test name
Test status
Simulation time 97502617 ps
CPU time 0.81 seconds
Started Jul 03 04:25:12 PM PDT 24
Finished Jul 03 04:25:13 PM PDT 24
Peak memory 198352 kb
Host smart-41d5ddca-2a43-4691-bded-375a6346dde9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657107039 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3657107039
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1754528103
Short name T52
Test name
Test status
Simulation time 698018368 ps
CPU time 1.34 seconds
Started Jul 03 04:25:16 PM PDT 24
Finished Jul 03 04:25:17 PM PDT 24
Peak memory 198672 kb
Host smart-027d1681-872a-49c3-9b18-16b63e6bbf59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754528103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1754528103
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3098328095
Short name T747
Test name
Test status
Simulation time 83746521 ps
CPU time 1.17 seconds
Started Jul 03 04:25:10 PM PDT 24
Finished Jul 03 04:25:12 PM PDT 24
Peak memory 198632 kb
Host smart-f5ea5ed1-58e3-4080-812b-17be73d6c04f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098328095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3098328095
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.242602677
Short name T111
Test name
Test status
Simulation time 47336005 ps
CPU time 0.65 seconds
Started Jul 03 04:25:05 PM PDT 24
Finished Jul 03 04:25:06 PM PDT 24
Peak memory 196084 kb
Host smart-bdad5e6b-2ecd-4e96-87c3-f2e50f53a961
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242602677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.242602677
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3623269127
Short name T823
Test name
Test status
Simulation time 265663638 ps
CPU time 3.14 seconds
Started Jul 03 04:25:03 PM PDT 24
Finished Jul 03 04:25:06 PM PDT 24
Peak memory 198736 kb
Host smart-0918a1ca-3536-41f9-98c0-897fbe730b18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623269127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3623269127
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2003036833
Short name T95
Test name
Test status
Simulation time 75214232 ps
CPU time 0.59 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 195044 kb
Host smart-4e470eca-46e5-4768-bb72-d6eb819e4d93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003036833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2003036833
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2803396393
Short name T743
Test name
Test status
Simulation time 41942722 ps
CPU time 0.92 seconds
Started Jul 03 04:24:51 PM PDT 24
Finished Jul 03 04:24:52 PM PDT 24
Peak memory 198492 kb
Host smart-1d106c10-0e8e-4dda-a19c-76c2151bc0cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803396393 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2803396393
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1715867541
Short name T807
Test name
Test status
Simulation time 21221576 ps
CPU time 0.59 seconds
Started Jul 03 04:24:35 PM PDT 24
Finished Jul 03 04:24:36 PM PDT 24
Peak memory 195488 kb
Host smart-2df05033-e6b4-4174-967d-135ce3a36cd5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715867541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1715867541
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3602866499
Short name T798
Test name
Test status
Simulation time 15767546 ps
CPU time 0.58 seconds
Started Jul 03 04:24:52 PM PDT 24
Finished Jul 03 04:24:53 PM PDT 24
Peak memory 194212 kb
Host smart-fa88e7d4-9724-4d22-8fb5-e024b3c0e082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602866499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3602866499
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1685852210
Short name T718
Test name
Test status
Simulation time 50896009 ps
CPU time 1.14 seconds
Started Jul 03 04:24:49 PM PDT 24
Finished Jul 03 04:24:50 PM PDT 24
Peak memory 198668 kb
Host smart-75f4548e-947d-4af3-ab23-785969859913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685852210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1685852210
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2426137048
Short name T51
Test name
Test status
Simulation time 667489001 ps
CPU time 1.35 seconds
Started Jul 03 04:26:23 PM PDT 24
Finished Jul 03 04:26:25 PM PDT 24
Peak memory 198524 kb
Host smart-4d53feb4-9ed5-4098-adbc-03416dcce11c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426137048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2426137048
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1075247284
Short name T110
Test name
Test status
Simulation time 64060690 ps
CPU time 0.61 seconds
Started Jul 03 04:26:34 PM PDT 24
Finished Jul 03 04:26:35 PM PDT 24
Peak memory 194704 kb
Host smart-8b3f2b72-e8ad-4818-a888-00c318c1a790
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075247284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1075247284
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1068135879
Short name T90
Test name
Test status
Simulation time 534477918 ps
CPU time 1.47 seconds
Started Jul 03 04:24:51 PM PDT 24
Finished Jul 03 04:24:53 PM PDT 24
Peak memory 197300 kb
Host smart-00329d99-ff65-445b-aace-0f5a90313194
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068135879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1068135879
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4258271838
Short name T745
Test name
Test status
Simulation time 16265152 ps
CPU time 0.59 seconds
Started Jul 03 04:26:32 PM PDT 24
Finished Jul 03 04:26:33 PM PDT 24
Peak memory 194884 kb
Host smart-fd737fde-5ce1-4dbc-847f-5c8d2cff7c6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258271838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.4258271838
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1407528510
Short name T724
Test name
Test status
Simulation time 64470902 ps
CPU time 0.79 seconds
Started Jul 03 04:25:03 PM PDT 24
Finished Jul 03 04:25:05 PM PDT 24
Peak memory 198464 kb
Host smart-c4d9bdde-4c5a-49bf-8e44-0445b74220bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407528510 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1407528510
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1514860126
Short name T109
Test name
Test status
Simulation time 23512943 ps
CPU time 0.59 seconds
Started Jul 03 04:25:07 PM PDT 24
Finished Jul 03 04:25:08 PM PDT 24
Peak memory 195580 kb
Host smart-b4061e30-2190-426a-ab42-d98d74a5d9b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514860126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1514860126
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3094366966
Short name T741
Test name
Test status
Simulation time 19859874 ps
CPU time 0.62 seconds
Started Jul 03 04:24:46 PM PDT 24
Finished Jul 03 04:24:52 PM PDT 24
Peak memory 194904 kb
Host smart-9962b11d-2927-47bd-af86-07fb6bb6890b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094366966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3094366966
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1965698678
Short name T842
Test name
Test status
Simulation time 138272983 ps
CPU time 0.6 seconds
Started Jul 03 04:25:07 PM PDT 24
Finished Jul 03 04:25:08 PM PDT 24
Peak memory 194920 kb
Host smart-434fb877-e339-4ba8-8bc9-ff89b8ec2738
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965698678 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1965698678
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.342911337
Short name T765
Test name
Test status
Simulation time 27213013 ps
CPU time 1.48 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 198188 kb
Host smart-b7a18957-661c-4a34-a0ff-b8177fc4eab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342911337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.342911337
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3981851669
Short name T817
Test name
Test status
Simulation time 53344840 ps
CPU time 0.82 seconds
Started Jul 03 04:24:59 PM PDT 24
Finished Jul 03 04:25:00 PM PDT 24
Peak memory 198124 kb
Host smart-c028ca52-57c5-4a0f-a5be-35b53702b70d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981851669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3981851669
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2099618065
Short name T845
Test name
Test status
Simulation time 19043980 ps
CPU time 0.91 seconds
Started Jul 03 04:25:15 PM PDT 24
Finished Jul 03 04:25:16 PM PDT 24
Peak memory 198596 kb
Host smart-56949b5c-0776-4f2b-965d-71edd05636f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099618065 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2099618065
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1385049075
Short name T783
Test name
Test status
Simulation time 11429982 ps
CPU time 0.62 seconds
Started Jul 03 04:25:03 PM PDT 24
Finished Jul 03 04:25:04 PM PDT 24
Peak memory 195516 kb
Host smart-b42499b2-c5df-4e0a-8262-e97750859be7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385049075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1385049075
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3104313816
Short name T812
Test name
Test status
Simulation time 24124363 ps
CPU time 0.58 seconds
Started Jul 03 04:25:15 PM PDT 24
Finished Jul 03 04:25:16 PM PDT 24
Peak memory 194160 kb
Host smart-46bccbfe-33af-42a2-86a5-bc7bd08b3954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104313816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3104313816
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1884713710
Short name T116
Test name
Test status
Simulation time 34020836 ps
CPU time 0.87 seconds
Started Jul 03 04:25:04 PM PDT 24
Finished Jul 03 04:25:06 PM PDT 24
Peak memory 197484 kb
Host smart-03398b19-5078-4055-b349-2847d1dfb68e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884713710 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1884713710
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.743649930
Short name T843
Test name
Test status
Simulation time 47158455 ps
CPU time 1.41 seconds
Started Jul 03 04:25:12 PM PDT 24
Finished Jul 03 04:25:13 PM PDT 24
Peak memory 198548 kb
Host smart-cb39af0b-6503-4119-b029-aaf2524f4316
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743649930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.743649930
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2593568649
Short name T774
Test name
Test status
Simulation time 331072084 ps
CPU time 1.21 seconds
Started Jul 03 04:24:52 PM PDT 24
Finished Jul 03 04:24:54 PM PDT 24
Peak memory 198660 kb
Host smart-4a6ed326-8681-4204-82f9-ac3161b94cc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593568649 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2593568649
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3879940839
Short name T108
Test name
Test status
Simulation time 14786794 ps
CPU time 0.61 seconds
Started Jul 03 04:25:11 PM PDT 24
Finished Jul 03 04:25:12 PM PDT 24
Peak memory 195456 kb
Host smart-2c0687c2-543f-493c-9acf-f552e3d74d37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879940839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3879940839
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1673358655
Short name T796
Test name
Test status
Simulation time 15624664 ps
CPU time 0.64 seconds
Started Jul 03 04:24:51 PM PDT 24
Finished Jul 03 04:24:52 PM PDT 24
Peak memory 194292 kb
Host smart-fa561f2a-54c2-4724-9394-0cbe50e12064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673358655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1673358655
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3211831721
Short name T802
Test name
Test status
Simulation time 127176793 ps
CPU time 0.74 seconds
Started Jul 03 04:25:01 PM PDT 24
Finished Jul 03 04:25:02 PM PDT 24
Peak memory 196724 kb
Host smart-7e2ae75c-d5a3-4496-b6d5-67b44bd745f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211831721 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3211831721
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1993374020
Short name T737
Test name
Test status
Simulation time 682117720 ps
CPU time 2.71 seconds
Started Jul 03 04:24:52 PM PDT 24
Finished Jul 03 04:24:55 PM PDT 24
Peak memory 198592 kb
Host smart-24660f65-ed48-4f49-a24a-e391a296a045
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993374020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1993374020
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1476096286
Short name T792
Test name
Test status
Simulation time 103948970 ps
CPU time 0.94 seconds
Started Jul 03 04:25:08 PM PDT 24
Finished Jul 03 04:25:09 PM PDT 24
Peak memory 198500 kb
Host smart-a3c3b61e-6a1c-4225-98ff-2809aac8a146
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476096286 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1476096286
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.772144931
Short name T89
Test name
Test status
Simulation time 15128521 ps
CPU time 0.58 seconds
Started Jul 03 04:25:01 PM PDT 24
Finished Jul 03 04:25:02 PM PDT 24
Peak memory 195512 kb
Host smart-3cfb8e03-3385-4525-84f9-ac4889e4f61b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772144931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.772144931
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1562281564
Short name T785
Test name
Test status
Simulation time 11900179 ps
CPU time 0.54 seconds
Started Jul 03 04:25:17 PM PDT 24
Finished Jul 03 04:25:18 PM PDT 24
Peak memory 194148 kb
Host smart-3e5156f7-aad2-48b5-b9c4-9cc94994682f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562281564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1562281564
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4129447293
Short name T96
Test name
Test status
Simulation time 24511790 ps
CPU time 0.65 seconds
Started Jul 03 04:25:14 PM PDT 24
Finished Jul 03 04:25:15 PM PDT 24
Peak memory 195356 kb
Host smart-bae3a1dd-362a-4ffd-8642-feec409a657b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129447293 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4129447293
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3889225935
Short name T768
Test name
Test status
Simulation time 323305777 ps
CPU time 2.56 seconds
Started Jul 03 04:25:06 PM PDT 24
Finished Jul 03 04:25:09 PM PDT 24
Peak memory 198676 kb
Host smart-ae439051-e700-45ea-b818-cd51e6bdf164
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889225935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3889225935
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.703500656
Short name T836
Test name
Test status
Simulation time 1485081348 ps
CPU time 1.37 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 198584 kb
Host smart-5282bf18-1034-4762-82b6-daddcae87b94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703500656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.703500656
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1920985322
Short name T831
Test name
Test status
Simulation time 59656090 ps
CPU time 0.65 seconds
Started Jul 03 04:25:12 PM PDT 24
Finished Jul 03 04:25:13 PM PDT 24
Peak memory 197744 kb
Host smart-967b292c-13b0-4638-813f-dff8ac70a67f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920985322 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1920985322
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.839632125
Short name T742
Test name
Test status
Simulation time 13454476 ps
CPU time 0.58 seconds
Started Jul 03 04:25:10 PM PDT 24
Finished Jul 03 04:25:11 PM PDT 24
Peak memory 195368 kb
Host smart-61ca9676-b15d-416e-9aa1-ebb43987fca9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839632125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.839632125
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1431363411
Short name T830
Test name
Test status
Simulation time 18374178 ps
CPU time 0.56 seconds
Started Jul 03 04:26:27 PM PDT 24
Finished Jul 03 04:26:28 PM PDT 24
Peak memory 194180 kb
Host smart-16c548ca-2c26-45ec-a847-9bc00603fb6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431363411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1431363411
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2184534513
Short name T115
Test name
Test status
Simulation time 13538915 ps
CPU time 0.58 seconds
Started Jul 03 04:25:18 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 195064 kb
Host smart-b641db94-84da-4ade-9d25-d659523911c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184534513 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2184534513
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2860819368
Short name T797
Test name
Test status
Simulation time 262262893 ps
CPU time 2.38 seconds
Started Jul 03 04:25:15 PM PDT 24
Finished Jul 03 04:25:17 PM PDT 24
Peak memory 198584 kb
Host smart-4dc305cc-5f5d-4bab-9c4c-00164cd97f86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860819368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2860819368
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1075017419
Short name T39
Test name
Test status
Simulation time 83204046 ps
CPU time 1.08 seconds
Started Jul 03 04:26:24 PM PDT 24
Finished Jul 03 04:26:25 PM PDT 24
Peak memory 198480 kb
Host smart-aac96632-1e35-415a-b1f4-e5b236fab543
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075017419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1075017419
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3226890390
Short name T789
Test name
Test status
Simulation time 32759057 ps
CPU time 1.54 seconds
Started Jul 03 04:25:07 PM PDT 24
Finished Jul 03 04:25:09 PM PDT 24
Peak memory 198592 kb
Host smart-1ab3a707-27c1-4092-a87d-2a9d5ff8db97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226890390 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3226890390
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2272745143
Short name T824
Test name
Test status
Simulation time 29625046 ps
CPU time 0.54 seconds
Started Jul 03 04:26:31 PM PDT 24
Finished Jul 03 04:26:32 PM PDT 24
Peak memory 194956 kb
Host smart-66387ea7-ae22-40ab-9a38-9a45d4efb308
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272745143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2272745143
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2281014538
Short name T738
Test name
Test status
Simulation time 38952644 ps
CPU time 0.56 seconds
Started Jul 03 04:26:29 PM PDT 24
Finished Jul 03 04:26:30 PM PDT 24
Peak memory 194136 kb
Host smart-25db2437-65f8-4714-a9bf-63bce7c7fd45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281014538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2281014538
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1513182041
Short name T828
Test name
Test status
Simulation time 63680648 ps
CPU time 0.82 seconds
Started Jul 03 04:25:09 PM PDT 24
Finished Jul 03 04:25:10 PM PDT 24
Peak memory 196836 kb
Host smart-eba2c904-ef7f-4a57-9fa3-f774381b41c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513182041 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1513182041
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2501947669
Short name T719
Test name
Test status
Simulation time 33416316 ps
CPU time 1.76 seconds
Started Jul 03 04:25:15 PM PDT 24
Finished Jul 03 04:25:18 PM PDT 24
Peak memory 198700 kb
Host smart-2eb19f28-9695-414c-b01d-cfe561819452
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501947669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2501947669
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.289722814
Short name T791
Test name
Test status
Simulation time 162412091 ps
CPU time 0.8 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 198380 kb
Host smart-6edf3284-1c52-4fcb-8fae-72a5ddec06d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289722814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.289722814
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.766204092
Short name T761
Test name
Test status
Simulation time 177439174 ps
CPU time 1.35 seconds
Started Jul 03 04:25:17 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 198704 kb
Host smart-3b97db10-62b5-4413-9011-a52dc77492b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766204092 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.766204092
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1443144172
Short name T835
Test name
Test status
Simulation time 15720066 ps
CPU time 0.57 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 195624 kb
Host smart-386212b4-0c01-4029-85f2-428c5b51b1d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443144172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1443144172
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3879190503
Short name T781
Test name
Test status
Simulation time 41480315 ps
CPU time 0.63 seconds
Started Jul 03 04:26:05 PM PDT 24
Finished Jul 03 04:26:06 PM PDT 24
Peak memory 193980 kb
Host smart-3a7fd88b-d201-41f8-b48f-b9fb27f6ca87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879190503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3879190503
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1783617772
Short name T94
Test name
Test status
Simulation time 130339038 ps
CPU time 0.81 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 197500 kb
Host smart-da8e2e0f-6b49-4ce8-94c7-c64ad227afc8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783617772 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1783617772
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1475710454
Short name T806
Test name
Test status
Simulation time 291553969 ps
CPU time 2.83 seconds
Started Jul 03 04:26:26 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 198484 kb
Host smart-332dc622-d7a2-4777-a20e-a14cc853d9cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475710454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1475710454
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3770861627
Short name T37
Test name
Test status
Simulation time 221513968 ps
CPU time 1.35 seconds
Started Jul 03 04:25:09 PM PDT 24
Finished Jul 03 04:25:11 PM PDT 24
Peak memory 198580 kb
Host smart-4fc460d7-204b-48bc-a24b-f3786b8876c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770861627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3770861627
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1719293944
Short name T720
Test name
Test status
Simulation time 75124260 ps
CPU time 0.72 seconds
Started Jul 03 04:25:13 PM PDT 24
Finished Jul 03 04:25:14 PM PDT 24
Peak memory 198468 kb
Host smart-7cd6449f-28f4-4bc5-a3b4-c9f8532188a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719293944 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1719293944
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2632270025
Short name T838
Test name
Test status
Simulation time 11385292 ps
CPU time 0.63 seconds
Started Jul 03 04:25:11 PM PDT 24
Finished Jul 03 04:25:12 PM PDT 24
Peak memory 195076 kb
Host smart-5e03d658-d34b-4050-9fc1-117ca3e841bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632270025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2632270025
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1064838801
Short name T740
Test name
Test status
Simulation time 64930911 ps
CPU time 0.61 seconds
Started Jul 03 04:25:09 PM PDT 24
Finished Jul 03 04:25:10 PM PDT 24
Peak memory 194320 kb
Host smart-3f675572-c35e-4f5a-934b-94c0a90fcf1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064838801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1064838801
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3382189542
Short name T777
Test name
Test status
Simulation time 47082761 ps
CPU time 0.61 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 195036 kb
Host smart-561c014e-260a-4a96-b65c-fe616805f1df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382189542 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3382189542
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1853819775
Short name T805
Test name
Test status
Simulation time 202065885 ps
CPU time 2.55 seconds
Started Jul 03 04:25:13 PM PDT 24
Finished Jul 03 04:25:16 PM PDT 24
Peak memory 198620 kb
Host smart-b34e9efa-6577-442a-9349-99a045190403
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853819775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1853819775
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3319985079
Short name T834
Test name
Test status
Simulation time 258527670 ps
CPU time 1.05 seconds
Started Jul 03 04:25:16 PM PDT 24
Finished Jul 03 04:25:18 PM PDT 24
Peak memory 198568 kb
Host smart-9afd2ca1-214a-4bba-b915-6e55941c95f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319985079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3319985079
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2870426016
Short name T794
Test name
Test status
Simulation time 32062620 ps
CPU time 1.31 seconds
Started Jul 03 04:26:24 PM PDT 24
Finished Jul 03 04:26:26 PM PDT 24
Peak memory 198556 kb
Host smart-a55516dc-7c1a-46dc-9f40-be8291cb1d05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870426016 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2870426016
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.491272720
Short name T736
Test name
Test status
Simulation time 46652229 ps
CPU time 0.58 seconds
Started Jul 03 04:25:13 PM PDT 24
Finished Jul 03 04:25:14 PM PDT 24
Peak memory 195560 kb
Host smart-3de099ab-a97e-46d3-a5f2-1afbea3390cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491272720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.491272720
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3013617700
Short name T847
Test name
Test status
Simulation time 51842421 ps
CPU time 0.58 seconds
Started Jul 03 04:25:17 PM PDT 24
Finished Jul 03 04:25:18 PM PDT 24
Peak memory 195004 kb
Host smart-14d72ca4-8367-4c37-b345-d0603581d1aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013617700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3013617700
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3462604496
Short name T808
Test name
Test status
Simulation time 17560364 ps
CPU time 0.76 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 196708 kb
Host smart-f349fe31-67f2-4066-89c0-f35e9169996e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462604496 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3462604496
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1381504139
Short name T815
Test name
Test status
Simulation time 276958164 ps
CPU time 2.29 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 198552 kb
Host smart-756e6c93-ce8e-4f27-a369-6ff4eedc0f30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381504139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1381504139
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3655799129
Short name T753
Test name
Test status
Simulation time 71950387 ps
CPU time 1.08 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 198612 kb
Host smart-c7513c13-3d14-411c-aaa3-fdc440e0e291
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655799129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3655799129
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2351640271
Short name T728
Test name
Test status
Simulation time 25432416 ps
CPU time 1.22 seconds
Started Jul 03 04:25:08 PM PDT 24
Finished Jul 03 04:25:10 PM PDT 24
Peak memory 198672 kb
Host smart-0d440357-f679-4345-996f-a53ff4b0539f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351640271 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2351640271
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4210952998
Short name T772
Test name
Test status
Simulation time 18295009 ps
CPU time 0.62 seconds
Started Jul 03 04:25:15 PM PDT 24
Finished Jul 03 04:25:16 PM PDT 24
Peak memory 196084 kb
Host smart-1c33cd78-bc0e-4218-82e5-2c15b262bb4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210952998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.4210952998
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2020189012
Short name T733
Test name
Test status
Simulation time 137681677 ps
CPU time 0.54 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 194148 kb
Host smart-f7be585a-5a8a-483d-b155-b34cb5e8f0dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020189012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2020189012
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1198820971
Short name T821
Test name
Test status
Simulation time 29686622 ps
CPU time 0.78 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 196700 kb
Host smart-424eefb1-a749-4c83-b37e-35dff5b470e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198820971 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1198820971
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1021442378
Short name T723
Test name
Test status
Simulation time 223609106 ps
CPU time 2.33 seconds
Started Jul 03 04:26:27 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 198460 kb
Host smart-9c0ab2d9-d531-4cab-8169-aea54342d86a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021442378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1021442378
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1924507355
Short name T784
Test name
Test status
Simulation time 119131795 ps
CPU time 0.86 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 198452 kb
Host smart-17c94e69-3e13-45a3-b922-71f5350ec4f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924507355 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1924507355
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4234780931
Short name T748
Test name
Test status
Simulation time 47991265 ps
CPU time 0.6 seconds
Started Jul 03 04:25:16 PM PDT 24
Finished Jul 03 04:25:17 PM PDT 24
Peak memory 195484 kb
Host smart-2b72006c-dfb5-4f03-abb7-9dc87f2c7707
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234780931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4234780931
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1286062440
Short name T749
Test name
Test status
Simulation time 17672160 ps
CPU time 0.61 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 194300 kb
Host smart-f5968e54-4ce8-486e-ad76-99672a826fa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286062440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1286062440
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.565885145
Short name T829
Test name
Test status
Simulation time 118639993 ps
CPU time 0.79 seconds
Started Jul 03 04:25:16 PM PDT 24
Finished Jul 03 04:25:17 PM PDT 24
Peak memory 196856 kb
Host smart-d841b113-0820-4a8b-9b74-c86555553c7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565885145 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.565885145
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1966013003
Short name T757
Test name
Test status
Simulation time 49462874 ps
CPU time 1.07 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 198648 kb
Host smart-a1cba83c-37db-4425-931e-756842570abe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966013003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1966013003
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.445382888
Short name T130
Test name
Test status
Simulation time 92175698 ps
CPU time 1.11 seconds
Started Jul 03 04:25:13 PM PDT 24
Finished Jul 03 04:25:15 PM PDT 24
Peak memory 198684 kb
Host smart-599147a0-ff04-4319-9304-3a45b44724e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445382888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.445382888
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.481673013
Short name T827
Test name
Test status
Simulation time 68716796 ps
CPU time 0.68 seconds
Started Jul 03 04:25:19 PM PDT 24
Finished Jul 03 04:25:20 PM PDT 24
Peak memory 195832 kb
Host smart-8f76101e-e92c-40cd-a2bc-64b58ecf9430
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481673013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.481673013
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1937963029
Short name T771
Test name
Test status
Simulation time 119751080 ps
CPU time 2.13 seconds
Started Jul 03 04:26:29 PM PDT 24
Finished Jul 03 04:26:32 PM PDT 24
Peak memory 197408 kb
Host smart-9549394f-2a38-482c-8d75-5c7e06c85068
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937963029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1937963029
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1430695208
Short name T826
Test name
Test status
Simulation time 23597263 ps
CPU time 0.59 seconds
Started Jul 03 04:24:50 PM PDT 24
Finished Jul 03 04:24:51 PM PDT 24
Peak memory 195272 kb
Host smart-2fd4d883-5e8d-4456-9e22-be046b8314a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430695208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1430695208
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3869856308
Short name T755
Test name
Test status
Simulation time 77912006 ps
CPU time 1.15 seconds
Started Jul 03 04:25:06 PM PDT 24
Finished Jul 03 04:25:07 PM PDT 24
Peak memory 198704 kb
Host smart-0feef3ec-012b-45d9-8c7e-fae65c114649
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869856308 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3869856308
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2101522354
Short name T107
Test name
Test status
Simulation time 32071088 ps
CPU time 0.56 seconds
Started Jul 03 04:25:00 PM PDT 24
Finished Jul 03 04:25:01 PM PDT 24
Peak memory 194440 kb
Host smart-2ac5ada3-4cce-42f1-8c25-e5cb2290c902
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101522354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2101522354
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1021167663
Short name T832
Test name
Test status
Simulation time 31087566 ps
CPU time 0.56 seconds
Started Jul 03 04:24:53 PM PDT 24
Finished Jul 03 04:24:54 PM PDT 24
Peak memory 194856 kb
Host smart-e9dc7aeb-f5b5-44f9-8acf-f4fe438eee56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021167663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1021167663
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2028925478
Short name T117
Test name
Test status
Simulation time 188869001 ps
CPU time 0.74 seconds
Started Jul 03 04:25:06 PM PDT 24
Finished Jul 03 04:25:08 PM PDT 24
Peak memory 197332 kb
Host smart-fd33863f-02cd-4abb-9772-9bdac7b6cd04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028925478 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2028925478
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1489157196
Short name T822
Test name
Test status
Simulation time 25904016 ps
CPU time 1.21 seconds
Started Jul 03 04:26:29 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 198488 kb
Host smart-fce232da-b79a-4ef2-a2e0-4a455d3ecb45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489157196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1489157196
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1505775575
Short name T38
Test name
Test status
Simulation time 148304142 ps
CPU time 1.49 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 197080 kb
Host smart-a7d51bf7-6533-4c9c-bc64-dddf12c36e7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505775575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1505775575
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.4036296397
Short name T840
Test name
Test status
Simulation time 13323141 ps
CPU time 0.56 seconds
Started Jul 03 04:25:08 PM PDT 24
Finished Jul 03 04:25:14 PM PDT 24
Peak memory 194252 kb
Host smart-c7a60276-5799-4de5-990c-20fef2908f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036296397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.4036296397
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3519470753
Short name T746
Test name
Test status
Simulation time 13707782 ps
CPU time 0.61 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 194196 kb
Host smart-25cdefc2-af89-4715-adf7-a0aa7575df74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519470753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3519470753
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.548703841
Short name T766
Test name
Test status
Simulation time 42310910 ps
CPU time 0.58 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:25:42 PM PDT 24
Peak memory 195076 kb
Host smart-ea8dc014-4afa-4ec3-892a-af3df196ab76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548703841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.548703841
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3713452788
Short name T770
Test name
Test status
Simulation time 12873405 ps
CPU time 0.59 seconds
Started Jul 03 04:25:18 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 194248 kb
Host smart-f5e07d7a-a49f-40ab-a4b1-3088131184ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713452788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3713452788
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3536263260
Short name T727
Test name
Test status
Simulation time 13301178 ps
CPU time 0.62 seconds
Started Jul 03 04:25:15 PM PDT 24
Finished Jul 03 04:25:16 PM PDT 24
Peak memory 194980 kb
Host smart-62013f68-1141-45fb-9a62-2a4773a2e514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536263260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3536263260
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1450306372
Short name T730
Test name
Test status
Simulation time 94318462 ps
CPU time 0.6 seconds
Started Jul 03 04:25:27 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 194968 kb
Host smart-ad5bfa36-962a-4006-8e09-fe4fe4871855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450306372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1450306372
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1779816418
Short name T764
Test name
Test status
Simulation time 27143400 ps
CPU time 0.61 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:25 PM PDT 24
Peak memory 195008 kb
Host smart-01c8d46f-dd80-4589-b6ca-577506b65ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779816418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1779816418
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1261836225
Short name T837
Test name
Test status
Simulation time 57602998 ps
CPU time 0.61 seconds
Started Jul 03 04:25:13 PM PDT 24
Finished Jul 03 04:25:14 PM PDT 24
Peak memory 195024 kb
Host smart-1ff007b4-38b0-4074-9425-7b9641a08d57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261836225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1261836225
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1651785118
Short name T819
Test name
Test status
Simulation time 21954684 ps
CPU time 0.61 seconds
Started Jul 03 04:25:12 PM PDT 24
Finished Jul 03 04:25:13 PM PDT 24
Peak memory 194848 kb
Host smart-841dec11-ff94-4b74-9a23-588fac23106e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651785118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1651785118
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.578703954
Short name T810
Test name
Test status
Simulation time 104458843 ps
CPU time 0.56 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 194156 kb
Host smart-e3ed5db1-ae86-47a8-8ae9-c4c644b102ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578703954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.578703954
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2421046758
Short name T91
Test name
Test status
Simulation time 23075317 ps
CPU time 0.65 seconds
Started Jul 03 04:25:14 PM PDT 24
Finished Jul 03 04:25:18 PM PDT 24
Peak memory 195500 kb
Host smart-62ce0808-525c-40a6-800e-7a9e2129db0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421046758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2421046758
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2344164018
Short name T787
Test name
Test status
Simulation time 258747650 ps
CPU time 3.07 seconds
Started Jul 03 04:24:48 PM PDT 24
Finished Jul 03 04:24:51 PM PDT 24
Peak memory 197788 kb
Host smart-eb739861-d7e7-409a-ae4f-b8273a23fbf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344164018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2344164018
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.286506048
Short name T744
Test name
Test status
Simulation time 71833442 ps
CPU time 0.77 seconds
Started Jul 03 04:25:03 PM PDT 24
Finished Jul 03 04:25:05 PM PDT 24
Peak memory 198416 kb
Host smart-4288afd2-29e6-4931-9280-cb3ed2374039
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286506048 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.286506048
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.894730520
Short name T790
Test name
Test status
Simulation time 45332642 ps
CPU time 0.61 seconds
Started Jul 03 04:25:03 PM PDT 24
Finished Jul 03 04:25:04 PM PDT 24
Peak memory 194980 kb
Host smart-9e4f295e-fdec-4092-b3cb-a077a428bcf1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894730520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.894730520
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.582136605
Short name T778
Test name
Test status
Simulation time 15591249 ps
CPU time 0.67 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 193440 kb
Host smart-a586281c-b420-4345-abf2-4c0eebc9846c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582136605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.582136605
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3450128671
Short name T113
Test name
Test status
Simulation time 45444660 ps
CPU time 0.8 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 195868 kb
Host smart-80c97c40-781f-47f6-bd35-14ab4f0cb03e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450128671 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3450128671
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1046088768
Short name T818
Test name
Test status
Simulation time 112523341 ps
CPU time 1.38 seconds
Started Jul 03 04:24:55 PM PDT 24
Finished Jul 03 04:24:56 PM PDT 24
Peak memory 198660 kb
Host smart-c32f5e07-5369-460c-b7f3-91884eb8fead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046088768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1046088768
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3816228228
Short name T50
Test name
Test status
Simulation time 450955969 ps
CPU time 0.85 seconds
Started Jul 03 04:25:03 PM PDT 24
Finished Jul 03 04:25:04 PM PDT 24
Peak memory 197456 kb
Host smart-a994c739-85d5-4f9f-b9fb-b06dca09b15a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816228228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3816228228
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2282846590
Short name T739
Test name
Test status
Simulation time 12199674 ps
CPU time 0.56 seconds
Started Jul 03 04:25:18 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 194808 kb
Host smart-f38cc770-6ca6-4641-951a-f43a998d7737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282846590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2282846590
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1985782881
Short name T776
Test name
Test status
Simulation time 21411177 ps
CPU time 0.56 seconds
Started Jul 03 04:25:15 PM PDT 24
Finished Jul 03 04:25:16 PM PDT 24
Peak memory 194580 kb
Host smart-2516c8cc-4ae3-47d6-ab85-1b8a8315fcbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985782881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1985782881
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2331358066
Short name T762
Test name
Test status
Simulation time 39839994 ps
CPU time 0.58 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:21 PM PDT 24
Peak memory 194300 kb
Host smart-0fe3c8dc-eb45-4d44-820f-e0df1864c428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331358066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2331358066
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1187190601
Short name T813
Test name
Test status
Simulation time 13608482 ps
CPU time 0.6 seconds
Started Jul 03 04:25:18 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 194356 kb
Host smart-6266cba4-4fac-42a0-827c-69601c1cd6bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187190601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1187190601
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2921643659
Short name T795
Test name
Test status
Simulation time 13195533 ps
CPU time 0.68 seconds
Started Jul 03 04:25:30 PM PDT 24
Finished Jul 03 04:25:32 PM PDT 24
Peak memory 194920 kb
Host smart-90211711-5c37-42c5-8be7-9879f929d4bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921643659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2921643659
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2604974737
Short name T732
Test name
Test status
Simulation time 11720661 ps
CPU time 0.59 seconds
Started Jul 03 04:25:18 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 194284 kb
Host smart-4f95a073-5778-4d68-8ae0-3e8da7340c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604974737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2604974737
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1850664747
Short name T767
Test name
Test status
Simulation time 26370881 ps
CPU time 0.6 seconds
Started Jul 03 04:25:31 PM PDT 24
Finished Jul 03 04:25:32 PM PDT 24
Peak memory 194272 kb
Host smart-a3ecd20a-23d2-4fe1-9922-8b94f9c5eff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850664747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1850664747
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4258428800
Short name T800
Test name
Test status
Simulation time 81820192 ps
CPU time 0.56 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 194332 kb
Host smart-789547ba-30df-4f9c-a74c-663019939852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258428800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4258428800
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2335815702
Short name T816
Test name
Test status
Simulation time 157349229 ps
CPU time 0.61 seconds
Started Jul 03 04:25:29 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 194316 kb
Host smart-bbbc14d3-407f-4213-9a29-0b3f95f75560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335815702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2335815702
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.313091423
Short name T841
Test name
Test status
Simulation time 43406698 ps
CPU time 0.56 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 194988 kb
Host smart-917e23a4-cf85-42a5-82b9-8a89ec84bab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313091423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.313091423
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2561464275
Short name T833
Test name
Test status
Simulation time 78530835 ps
CPU time 0.64 seconds
Started Jul 03 04:25:10 PM PDT 24
Finished Jul 03 04:25:11 PM PDT 24
Peak memory 194756 kb
Host smart-1e9b6e97-31c1-4953-813b-a16e09c50825
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561464275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2561464275
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2815842110
Short name T775
Test name
Test status
Simulation time 93893953 ps
CPU time 1.49 seconds
Started Jul 03 04:25:11 PM PDT 24
Finished Jul 03 04:25:13 PM PDT 24
Peak memory 198632 kb
Host smart-e5d8445e-7784-4f76-88cf-7e1eee00d0f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815842110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2815842110
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2146529278
Short name T793
Test name
Test status
Simulation time 16312157 ps
CPU time 0.63 seconds
Started Jul 03 04:25:02 PM PDT 24
Finished Jul 03 04:25:03 PM PDT 24
Peak memory 194804 kb
Host smart-fb8f44dc-6dfb-49a6-8ed6-691c099b20c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146529278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2146529278
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2575651816
Short name T769
Test name
Test status
Simulation time 43784168 ps
CPU time 0.7 seconds
Started Jul 03 04:25:02 PM PDT 24
Finished Jul 03 04:25:03 PM PDT 24
Peak memory 196964 kb
Host smart-60282f4b-dcf4-4c4b-8661-595e9923090f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575651816 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2575651816
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3457980549
Short name T106
Test name
Test status
Simulation time 58598384 ps
CPU time 0.57 seconds
Started Jul 03 04:25:18 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 195424 kb
Host smart-37b1446a-45cc-4968-a6de-97e03b75595d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457980549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3457980549
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1352521361
Short name T848
Test name
Test status
Simulation time 48523520 ps
CPU time 0.6 seconds
Started Jul 03 04:25:02 PM PDT 24
Finished Jul 03 04:25:03 PM PDT 24
Peak memory 194324 kb
Host smart-88102f80-b532-4d44-a088-b4dc03a1135f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352521361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1352521361
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2016110756
Short name T119
Test name
Test status
Simulation time 55639015 ps
CPU time 0.76 seconds
Started Jul 03 04:24:54 PM PDT 24
Finished Jul 03 04:24:55 PM PDT 24
Peak memory 197412 kb
Host smart-4d6eb292-03c9-41ca-8390-7fb0f2330f07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016110756 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2016110756
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.99036241
Short name T763
Test name
Test status
Simulation time 77515018 ps
CPU time 1.86 seconds
Started Jul 03 04:24:54 PM PDT 24
Finished Jul 03 04:24:56 PM PDT 24
Peak memory 198688 kb
Host smart-a107acfd-1609-41f3-9646-25fb36384fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99036241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.99036241
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1573753846
Short name T782
Test name
Test status
Simulation time 47297721 ps
CPU time 0.86 seconds
Started Jul 03 04:24:51 PM PDT 24
Finished Jul 03 04:24:52 PM PDT 24
Peak memory 197636 kb
Host smart-7883c7ad-24ff-48ba-a023-c4dca926ab02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573753846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1573753846
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3051643627
Short name T760
Test name
Test status
Simulation time 44122700 ps
CPU time 0.59 seconds
Started Jul 03 04:25:29 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 194300 kb
Host smart-3f2e8ca9-67f1-4a8e-9821-638161411128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051643627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3051643627
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.97589323
Short name T801
Test name
Test status
Simulation time 13375367 ps
CPU time 0.56 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 194284 kb
Host smart-58a1a68f-5399-4065-b8be-04ee2457f98b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97589323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.97589323
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3199610060
Short name T722
Test name
Test status
Simulation time 24943389 ps
CPU time 0.61 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 194324 kb
Host smart-74050705-71cb-4b26-b93a-fdb4dd43b9e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199610060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3199610060
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2285924375
Short name T729
Test name
Test status
Simulation time 21736677 ps
CPU time 0.57 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:21 PM PDT 24
Peak memory 194312 kb
Host smart-09bd46df-3e27-46ce-80f9-6d43abb9111e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285924375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2285924375
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1040074572
Short name T758
Test name
Test status
Simulation time 11759563 ps
CPU time 0.59 seconds
Started Jul 03 04:25:38 PM PDT 24
Finished Jul 03 04:25:39 PM PDT 24
Peak memory 194288 kb
Host smart-61d38783-0375-4f15-81aa-2ca685aeda79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040074572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1040074572
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1403135918
Short name T756
Test name
Test status
Simulation time 14467307 ps
CPU time 0.62 seconds
Started Jul 03 04:25:30 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 194960 kb
Host smart-9777f943-5262-4ed2-91e6-6f82868b76df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403135918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1403135918
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.498958585
Short name T844
Test name
Test status
Simulation time 18766383 ps
CPU time 0.63 seconds
Started Jul 03 04:25:27 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 194352 kb
Host smart-f67728bd-f621-4e56-ba3a-5423b4916a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498958585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.498958585
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3533091424
Short name T751
Test name
Test status
Simulation time 39242906 ps
CPU time 0.57 seconds
Started Jul 03 04:25:17 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 194244 kb
Host smart-589efed8-7e10-489d-bf56-00603ae2223f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533091424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3533091424
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2196988368
Short name T846
Test name
Test status
Simulation time 45901782 ps
CPU time 0.55 seconds
Started Jul 03 04:25:17 PM PDT 24
Finished Jul 03 04:25:18 PM PDT 24
Peak memory 194580 kb
Host smart-2e3c1cb2-7200-4916-ade0-1b5c5f560d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196988368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2196988368
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3220269321
Short name T814
Test name
Test status
Simulation time 17235077 ps
CPU time 0.56 seconds
Started Jul 03 04:25:17 PM PDT 24
Finished Jul 03 04:25:18 PM PDT 24
Peak memory 194960 kb
Host smart-82b3a5e6-d8e5-4b15-bd7a-4be9aed4b44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220269321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3220269321
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2286939876
Short name T811
Test name
Test status
Simulation time 70284008 ps
CPU time 1.84 seconds
Started Jul 03 04:25:03 PM PDT 24
Finished Jul 03 04:25:05 PM PDT 24
Peak memory 198736 kb
Host smart-360cb488-d279-489f-95f5-1121bbe267ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286939876 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2286939876
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1499928077
Short name T112
Test name
Test status
Simulation time 12223173 ps
CPU time 0.58 seconds
Started Jul 03 04:24:53 PM PDT 24
Finished Jul 03 04:24:54 PM PDT 24
Peak memory 195092 kb
Host smart-b796d068-416a-48f5-a0a7-7c4a636a4595
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499928077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1499928077
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.530962549
Short name T825
Test name
Test status
Simulation time 33572925 ps
CPU time 0.57 seconds
Started Jul 03 04:24:59 PM PDT 24
Finished Jul 03 04:24:59 PM PDT 24
Peak memory 194292 kb
Host smart-bd194c66-f3a2-4788-9087-54f642d8d9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530962549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.530962549
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2425135733
Short name T804
Test name
Test status
Simulation time 53844941 ps
CPU time 0.71 seconds
Started Jul 03 04:24:52 PM PDT 24
Finished Jul 03 04:24:53 PM PDT 24
Peak memory 197504 kb
Host smart-8cecfc4e-68bf-43fd-b80e-db7091a1f04c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425135733 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2425135733
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.210055726
Short name T752
Test name
Test status
Simulation time 44234048 ps
CPU time 1.32 seconds
Started Jul 03 04:24:49 PM PDT 24
Finished Jul 03 04:24:51 PM PDT 24
Peak memory 198564 kb
Host smart-e3e1e830-30e4-44a7-9c78-80f26918c542
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210055726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.210055726
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4201586788
Short name T799
Test name
Test status
Simulation time 101643247 ps
CPU time 1.39 seconds
Started Jul 03 04:25:01 PM PDT 24
Finished Jul 03 04:25:03 PM PDT 24
Peak memory 198740 kb
Host smart-dcae4649-9765-4d1b-8875-854ee8b7f4ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201586788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.4201586788
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.309898814
Short name T735
Test name
Test status
Simulation time 22557797 ps
CPU time 0.79 seconds
Started Jul 03 04:25:13 PM PDT 24
Finished Jul 03 04:25:14 PM PDT 24
Peak memory 198508 kb
Host smart-19a09314-4fb0-4f77-8c3a-b1d279fccd73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309898814 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.309898814
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.657673723
Short name T129
Test name
Test status
Simulation time 31900565 ps
CPU time 0.54 seconds
Started Jul 03 04:25:12 PM PDT 24
Finished Jul 03 04:25:13 PM PDT 24
Peak memory 193812 kb
Host smart-fcdbe253-6041-4bb1-a968-f96b612985a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657673723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.657673723
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1184139757
Short name T734
Test name
Test status
Simulation time 28506881 ps
CPU time 0.59 seconds
Started Jul 03 04:25:03 PM PDT 24
Finished Jul 03 04:25:04 PM PDT 24
Peak memory 194880 kb
Host smart-317382fc-9314-4c52-b30a-37c6e97f7b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184139757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1184139757
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3782584593
Short name T839
Test name
Test status
Simulation time 19786035 ps
CPU time 0.64 seconds
Started Jul 03 04:24:50 PM PDT 24
Finished Jul 03 04:24:52 PM PDT 24
Peak memory 195152 kb
Host smart-f153c713-c536-46f2-b9dc-21107127e60b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782584593 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3782584593
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.215251344
Short name T721
Test name
Test status
Simulation time 121883655 ps
CPU time 1.2 seconds
Started Jul 03 04:25:09 PM PDT 24
Finished Jul 03 04:25:11 PM PDT 24
Peak memory 198744 kb
Host smart-beea9acd-e188-4f19-9614-bb528ec4eae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215251344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.215251344
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1426710775
Short name T803
Test name
Test status
Simulation time 177160502 ps
CPU time 0.88 seconds
Started Jul 03 04:25:13 PM PDT 24
Finished Jul 03 04:25:14 PM PDT 24
Peak memory 198436 kb
Host smart-54bae4c1-297b-47a8-8b36-4466c5ec68ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426710775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1426710775
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1235670776
Short name T750
Test name
Test status
Simulation time 153452277 ps
CPU time 1.01 seconds
Started Jul 03 04:25:05 PM PDT 24
Finished Jul 03 04:25:06 PM PDT 24
Peak memory 198496 kb
Host smart-798c58e2-434c-47f9-bf8c-83e7c63b2677
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235670776 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1235670776
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4192584263
Short name T773
Test name
Test status
Simulation time 62709146 ps
CPU time 0.61 seconds
Started Jul 03 04:25:12 PM PDT 24
Finished Jul 03 04:25:12 PM PDT 24
Peak memory 195444 kb
Host smart-e40dab46-9e0a-427e-a742-b840f5999eef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192584263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.4192584263
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3325423635
Short name T726
Test name
Test status
Simulation time 14606968 ps
CPU time 0.61 seconds
Started Jul 03 04:25:02 PM PDT 24
Finished Jul 03 04:25:03 PM PDT 24
Peak memory 194376 kb
Host smart-245a4b3c-5608-4bd4-9e5f-ed19a8ea769a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325423635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3325423635
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1435350113
Short name T118
Test name
Test status
Simulation time 246718299 ps
CPU time 0.69 seconds
Started Jul 03 04:24:50 PM PDT 24
Finished Jul 03 04:24:52 PM PDT 24
Peak memory 195160 kb
Host smart-7f5469c1-1824-4717-bd1c-68b410caadb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435350113 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1435350113
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3122645683
Short name T788
Test name
Test status
Simulation time 37191053 ps
CPU time 0.99 seconds
Started Jul 03 04:25:10 PM PDT 24
Finished Jul 03 04:25:12 PM PDT 24
Peak memory 198384 kb
Host smart-7bb116ff-bbb1-4a8b-a1ab-51e73a8156a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122645683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3122645683
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1758782758
Short name T725
Test name
Test status
Simulation time 139802826 ps
CPU time 0.87 seconds
Started Jul 03 04:25:11 PM PDT 24
Finished Jul 03 04:25:12 PM PDT 24
Peak memory 198308 kb
Host smart-84a8c069-d847-4d69-82dc-caa87ceafbbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758782758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1758782758
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3859232637
Short name T754
Test name
Test status
Simulation time 23737951 ps
CPU time 1.02 seconds
Started Jul 03 04:25:14 PM PDT 24
Finished Jul 03 04:25:15 PM PDT 24
Peak memory 198744 kb
Host smart-2ef884a1-f420-4a8a-9e37-e67287b76b00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859232637 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3859232637
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2045025005
Short name T92
Test name
Test status
Simulation time 21544462 ps
CPU time 0.57 seconds
Started Jul 03 04:26:26 PM PDT 24
Finished Jul 03 04:26:27 PM PDT 24
Peak memory 195232 kb
Host smart-1f8ee354-8e65-4f77-8bd4-9a1a06e81017
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045025005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2045025005
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1766246471
Short name T809
Test name
Test status
Simulation time 11692515 ps
CPU time 0.55 seconds
Started Jul 03 04:25:00 PM PDT 24
Finished Jul 03 04:25:01 PM PDT 24
Peak memory 194216 kb
Host smart-38eac320-8765-4830-a6c8-6541c0d16f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766246471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1766246471
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1496005743
Short name T820
Test name
Test status
Simulation time 176780706 ps
CPU time 0.73 seconds
Started Jul 03 04:24:59 PM PDT 24
Finished Jul 03 04:25:00 PM PDT 24
Peak memory 197468 kb
Host smart-fff22299-dee4-4641-9252-9334717da103
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496005743 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1496005743
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.66028427
Short name T731
Test name
Test status
Simulation time 83138157 ps
CPU time 1.82 seconds
Started Jul 03 04:25:10 PM PDT 24
Finished Jul 03 04:25:13 PM PDT 24
Peak memory 198656 kb
Host smart-2d93ca5f-07ea-48b1-a118-0ba0d4f59ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66028427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.66028427
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2864296724
Short name T54
Test name
Test status
Simulation time 163071193 ps
CPU time 0.86 seconds
Started Jul 03 04:25:11 PM PDT 24
Finished Jul 03 04:25:13 PM PDT 24
Peak memory 197656 kb
Host smart-468534fd-4e0c-447b-a30d-d4590755bce8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864296724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2864296724
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2196704218
Short name T786
Test name
Test status
Simulation time 33095675 ps
CPU time 0.81 seconds
Started Jul 03 04:25:05 PM PDT 24
Finished Jul 03 04:25:07 PM PDT 24
Peak memory 198440 kb
Host smart-2b21a030-0ab0-40ae-a920-864e3b688989
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196704218 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2196704218
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2904523385
Short name T779
Test name
Test status
Simulation time 16065605 ps
CPU time 0.58 seconds
Started Jul 03 04:25:19 PM PDT 24
Finished Jul 03 04:25:20 PM PDT 24
Peak memory 194464 kb
Host smart-f8e33162-d900-4a5c-9320-9af97b300456
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904523385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2904523385
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1932983152
Short name T780
Test name
Test status
Simulation time 43021068 ps
CPU time 0.57 seconds
Started Jul 03 04:24:53 PM PDT 24
Finished Jul 03 04:24:54 PM PDT 24
Peak memory 194952 kb
Host smart-dce994c4-1318-4dcf-a571-fd51516bc96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932983152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1932983152
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2818868029
Short name T114
Test name
Test status
Simulation time 128479711 ps
CPU time 0.91 seconds
Started Jul 03 04:25:09 PM PDT 24
Finished Jul 03 04:25:11 PM PDT 24
Peak memory 198408 kb
Host smart-aebf6069-52e8-4970-8f71-73daef75f1df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818868029 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2818868029
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1400721433
Short name T759
Test name
Test status
Simulation time 148434137 ps
CPU time 2.46 seconds
Started Jul 03 04:25:02 PM PDT 24
Finished Jul 03 04:25:05 PM PDT 24
Peak memory 198556 kb
Host smart-144e2e75-e963-4629-8482-1e5154bc84e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400721433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1400721433
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3024379086
Short name T53
Test name
Test status
Simulation time 136514458 ps
CPU time 1.19 seconds
Started Jul 03 04:25:11 PM PDT 24
Finished Jul 03 04:25:12 PM PDT 24
Peak memory 198536 kb
Host smart-4034af66-9193-4c96-b9e2-fffe535d90aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024379086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3024379086
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1903484481
Short name T159
Test name
Test status
Simulation time 37480291 ps
CPU time 0.82 seconds
Started Jul 03 04:25:17 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 197108 kb
Host smart-a5ccc9e3-0df4-4503-b72f-44358d40266f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903484481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1903484481
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2285479650
Short name T347
Test name
Test status
Simulation time 558253087 ps
CPU time 13.26 seconds
Started Jul 03 04:25:29 PM PDT 24
Finished Jul 03 04:25:44 PM PDT 24
Peak memory 197468 kb
Host smart-c45276e1-df65-4990-810f-d0144d90fb8e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285479650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2285479650
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2890430872
Short name T138
Test name
Test status
Simulation time 28771763 ps
CPU time 0.72 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 196088 kb
Host smart-06b193ee-0c32-4349-b839-9ec5dbccabf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890430872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2890430872
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3200609195
Short name T304
Test name
Test status
Simulation time 26519623 ps
CPU time 0.71 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 195976 kb
Host smart-b0e169f4-01d2-435e-8a23-4b2ab0c7f3b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200609195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3200609195
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3156315515
Short name T533
Test name
Test status
Simulation time 73594323 ps
CPU time 2.67 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 198664 kb
Host smart-2de4f8b2-0174-44c9-83ff-f5c277490d6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156315515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3156315515
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3118882361
Short name T443
Test name
Test status
Simulation time 226845174 ps
CPU time 1.88 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 197532 kb
Host smart-73facd25-0b48-49c7-9cf1-707e829d983d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118882361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3118882361
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1609645911
Short name T169
Test name
Test status
Simulation time 211653910 ps
CPU time 1.03 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:25:25 PM PDT 24
Peak memory 196396 kb
Host smart-b11709ab-52a6-458a-8487-0057b5b3fec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609645911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1609645911
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3670304455
Short name T510
Test name
Test status
Simulation time 87663363 ps
CPU time 0.76 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 195972 kb
Host smart-8ed52f32-19b6-473d-b657-0016dd796a65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670304455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3670304455
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3819783378
Short name T448
Test name
Test status
Simulation time 107220894 ps
CPU time 4.39 seconds
Started Jul 03 04:25:31 PM PDT 24
Finished Jul 03 04:25:41 PM PDT 24
Peak memory 198548 kb
Host smart-cd222b08-22d2-4c8f-84d0-9f3743148cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819783378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3819783378
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2213513177
Short name T56
Test name
Test status
Simulation time 226772514 ps
CPU time 0.84 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:25:25 PM PDT 24
Peak memory 214176 kb
Host smart-ff8f4bf7-4e2b-46ee-a107-b1f743bd1a88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213513177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2213513177
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2954242827
Short name T476
Test name
Test status
Simulation time 62186483 ps
CPU time 1.05 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:21 PM PDT 24
Peak memory 196140 kb
Host smart-7e76b361-aa08-4141-b03a-3c9fb148103d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954242827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2954242827
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1571233262
Short name T514
Test name
Test status
Simulation time 99460094 ps
CPU time 0.94 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 196840 kb
Host smart-a7df76d5-b823-46cc-8c08-a14749639146
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571233262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1571233262
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.467946993
Short name T622
Test name
Test status
Simulation time 16118110807 ps
CPU time 103.75 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 198752 kb
Host smart-59a9b093-9969-4f88-88bc-d6230ba50bf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467946993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.467946993
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.4251129046
Short name T67
Test name
Test status
Simulation time 80058529559 ps
CPU time 1560.34 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:51:23 PM PDT 24
Peak memory 198956 kb
Host smart-3aceaf4a-a62d-4a3b-9b14-81fff50482c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4251129046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.4251129046
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2913490318
Short name T683
Test name
Test status
Simulation time 48339153 ps
CPU time 0.58 seconds
Started Jul 03 04:25:30 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 194516 kb
Host smart-50ecad4f-9010-466c-829c-12dbcd0c0197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913490318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2913490318
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3513099678
Short name T437
Test name
Test status
Simulation time 22004676 ps
CPU time 0.69 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 195728 kb
Host smart-966b49d9-f4e6-472b-958e-9e5514f116af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513099678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3513099678
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3583869407
Short name T390
Test name
Test status
Simulation time 637421427 ps
CPU time 8.64 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:38 PM PDT 24
Peak memory 197348 kb
Host smart-339c5597-cd0d-49c1-b25a-b19656a19d6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583869407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3583869407
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.317670166
Short name T600
Test name
Test status
Simulation time 122528169 ps
CPU time 0.88 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 196616 kb
Host smart-fc3d29b1-3170-4bdf-97ed-2de547b9eeee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317670166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.317670166
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3972923421
Short name T185
Test name
Test status
Simulation time 34778853 ps
CPU time 0.96 seconds
Started Jul 03 04:25:29 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 196680 kb
Host smart-f862f9f8-3cd1-40d5-863c-3940527a5259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972923421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3972923421
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3109980368
Short name T268
Test name
Test status
Simulation time 241091220 ps
CPU time 2.37 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:25:25 PM PDT 24
Peak memory 198524 kb
Host smart-35497c23-6621-4507-b254-31334469284c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109980368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3109980368
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2085371495
Short name T610
Test name
Test status
Simulation time 47706894 ps
CPU time 1.03 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 196192 kb
Host smart-cbc5b025-f933-467f-b010-0a904691ae5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085371495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2085371495
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.120760260
Short name T282
Test name
Test status
Simulation time 108319905 ps
CPU time 1.17 seconds
Started Jul 03 04:25:31 PM PDT 24
Finished Jul 03 04:25:33 PM PDT 24
Peak memory 197640 kb
Host smart-28c93340-f976-453f-a582-072b48a92341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120760260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.120760260
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2222027356
Short name T214
Test name
Test status
Simulation time 93060428 ps
CPU time 0.94 seconds
Started Jul 03 04:25:35 PM PDT 24
Finished Jul 03 04:25:36 PM PDT 24
Peak memory 196456 kb
Host smart-1667c598-f1e0-4a24-a895-c001029eedc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222027356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2222027356
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2621726747
Short name T207
Test name
Test status
Simulation time 76441651 ps
CPU time 3.35 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:30 PM PDT 24
Peak memory 198472 kb
Host smart-2868c13a-52a1-45b6-956f-06f41e079beb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621726747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2621726747
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.2254826401
Short name T213
Test name
Test status
Simulation time 54136765 ps
CPU time 1.08 seconds
Started Jul 03 04:25:38 PM PDT 24
Finished Jul 03 04:25:40 PM PDT 24
Peak memory 196440 kb
Host smart-31789560-5f61-4f1e-8659-40d5b0c358f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254826401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2254826401
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1614284200
Short name T181
Test name
Test status
Simulation time 176874594 ps
CPU time 1.22 seconds
Started Jul 03 04:25:27 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 196116 kb
Host smart-75290dd2-fe52-41e0-a99e-23087dea615b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614284200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1614284200
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2620802173
Short name T230
Test name
Test status
Simulation time 74816532351 ps
CPU time 90.26 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 198640 kb
Host smart-aa0cbfcc-1fbd-4b76-bb94-ca55d19978ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620802173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2620802173
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.227826106
Short name T453
Test name
Test status
Simulation time 89004890966 ps
CPU time 2018.86 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:59:01 PM PDT 24
Peak memory 198796 kb
Host smart-8f776b2f-f52b-4e28-a58c-55b2a91e1995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=227826106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.227826106
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1367083310
Short name T554
Test name
Test status
Simulation time 36287391 ps
CPU time 0.59 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 194396 kb
Host smart-f710b9ed-a814-4cb2-ab2b-5b170450802c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367083310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1367083310
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1236453773
Short name T265
Test name
Test status
Simulation time 47417807 ps
CPU time 0.74 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 195836 kb
Host smart-c9282643-adc5-4b57-927e-5728b77c5d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236453773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1236453773
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3888868862
Short name T25
Test name
Test status
Simulation time 966918458 ps
CPU time 27.47 seconds
Started Jul 03 04:25:30 PM PDT 24
Finished Jul 03 04:25:59 PM PDT 24
Peak memory 197344 kb
Host smart-6d20aba1-f1b6-4537-bba2-5b2ad619a96e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888868862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3888868862
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3860512478
Short name T192
Test name
Test status
Simulation time 66060238 ps
CPU time 0.91 seconds
Started Jul 03 04:25:37 PM PDT 24
Finished Jul 03 04:25:38 PM PDT 24
Peak memory 198768 kb
Host smart-279fb249-dd38-43d9-ab6a-4ab0cabfdd05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860512478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3860512478
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3449494604
Short name T493
Test name
Test status
Simulation time 51651923 ps
CPU time 0.87 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 197244 kb
Host smart-9aa80745-4150-4ad1-8296-4b31f8aff10e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449494604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3449494604
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1265489660
Short name T212
Test name
Test status
Simulation time 95477086 ps
CPU time 2.03 seconds
Started Jul 03 04:25:51 PM PDT 24
Finished Jul 03 04:25:54 PM PDT 24
Peak memory 198644 kb
Host smart-a15fe717-2db4-4bc3-83b8-50dd9138b85b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265489660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1265489660
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3613199461
Short name T471
Test name
Test status
Simulation time 100312264 ps
CPU time 2.31 seconds
Started Jul 03 04:25:45 PM PDT 24
Finished Jul 03 04:25:48 PM PDT 24
Peak memory 198568 kb
Host smart-c33b6b96-8ec0-4008-8437-8732d10574ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613199461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3613199461
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.552303257
Short name T327
Test name
Test status
Simulation time 246890968 ps
CPU time 0.89 seconds
Started Jul 03 04:25:35 PM PDT 24
Finished Jul 03 04:25:36 PM PDT 24
Peak memory 197228 kb
Host smart-941e2c35-df2d-40c6-adc0-257eaa8cab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552303257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.552303257
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2216202735
Short name T257
Test name
Test status
Simulation time 132252069 ps
CPU time 1.15 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 196468 kb
Host smart-d6a42ae8-82e6-46d8-8f4e-c2cca9865b41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216202735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2216202735
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3832294033
Short name T76
Test name
Test status
Simulation time 94533253 ps
CPU time 1.67 seconds
Started Jul 03 04:25:49 PM PDT 24
Finished Jul 03 04:25:51 PM PDT 24
Peak memory 198888 kb
Host smart-e030bb11-439c-45ec-819a-d442430a97b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832294033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3832294033
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3173441900
Short name T426
Test name
Test status
Simulation time 111866918 ps
CPU time 0.91 seconds
Started Jul 03 04:26:02 PM PDT 24
Finished Jul 03 04:26:04 PM PDT 24
Peak memory 196444 kb
Host smart-1aa9fe9c-7445-4957-b6b8-95d01a8c8474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173441900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3173441900
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3045613924
Short name T13
Test name
Test status
Simulation time 518014425 ps
CPU time 1.36 seconds
Started Jul 03 04:25:54 PM PDT 24
Finished Jul 03 04:25:56 PM PDT 24
Peak memory 198528 kb
Host smart-47f8730b-8bd6-4d4a-951a-fd43a1d43da5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045613924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3045613924
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.4218867749
Short name T285
Test name
Test status
Simulation time 3878167790 ps
CPU time 93.37 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:27:18 PM PDT 24
Peak memory 198764 kb
Host smart-23b1aa11-cfaa-46c6-9151-740da8b5c8e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218867749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.4218867749
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3885297610
Short name T422
Test name
Test status
Simulation time 11972185 ps
CPU time 0.56 seconds
Started Jul 03 04:26:01 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 193436 kb
Host smart-afc51096-f616-4636-8845-f5efd4b5e637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885297610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3885297610
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3402431931
Short name T441
Test name
Test status
Simulation time 21610904 ps
CPU time 0.71 seconds
Started Jul 03 04:25:44 PM PDT 24
Finished Jul 03 04:25:46 PM PDT 24
Peak memory 195476 kb
Host smart-6e3cf89d-6dff-4f23-a7b1-0d4b90208ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402431931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3402431931
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2649104892
Short name T549
Test name
Test status
Simulation time 1396774697 ps
CPU time 24.26 seconds
Started Jul 03 04:25:38 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 197280 kb
Host smart-8e512873-9bed-424c-b6b6-f770a28ecc81
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649104892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2649104892
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.4228104437
Short name T429
Test name
Test status
Simulation time 209202752 ps
CPU time 0.83 seconds
Started Jul 03 04:25:35 PM PDT 24
Finished Jul 03 04:25:37 PM PDT 24
Peak memory 196404 kb
Host smart-8f760674-9709-49cc-884f-f3ea89db747d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228104437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.4228104437
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3818092498
Short name T469
Test name
Test status
Simulation time 96301906 ps
CPU time 0.66 seconds
Started Jul 03 04:25:27 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 194900 kb
Host smart-310c58fa-efe6-4e46-b589-aac3924d7931
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818092498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3818092498
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3286246991
Short name T184
Test name
Test status
Simulation time 153875499 ps
CPU time 2.6 seconds
Started Jul 03 04:25:30 PM PDT 24
Finished Jul 03 04:25:34 PM PDT 24
Peak memory 198540 kb
Host smart-225e1e80-f74c-44bc-85ba-ea3abf582a11
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286246991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3286246991
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2608621978
Short name T16
Test name
Test status
Simulation time 456070332 ps
CPU time 1.23 seconds
Started Jul 03 04:25:45 PM PDT 24
Finished Jul 03 04:25:47 PM PDT 24
Peak memory 197496 kb
Host smart-910e7d80-5d96-403e-bc98-c3f1c3e05cf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608621978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2608621978
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2806508386
Short name T17
Test name
Test status
Simulation time 57302018 ps
CPU time 0.77 seconds
Started Jul 03 04:25:51 PM PDT 24
Finished Jul 03 04:25:53 PM PDT 24
Peak memory 195888 kb
Host smart-1628842d-7e12-45c0-9c9e-0a41a5a9042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806508386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2806508386
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3390992551
Short name T353
Test name
Test status
Simulation time 73684182 ps
CPU time 0.94 seconds
Started Jul 03 04:25:44 PM PDT 24
Finished Jul 03 04:25:46 PM PDT 24
Peak memory 197320 kb
Host smart-a219b6e2-e13b-4752-8cad-1edace4d496c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390992551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3390992551
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3021163086
Short name T560
Test name
Test status
Simulation time 450818033 ps
CPU time 5.3 seconds
Started Jul 03 04:26:10 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 198620 kb
Host smart-9e8f8f5e-bde4-461b-a27c-61915051d3e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021163086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3021163086
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.274210180
Short name T715
Test name
Test status
Simulation time 35392303 ps
CPU time 1.02 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 196440 kb
Host smart-61a4b11a-a5e4-43d8-87e7-ea9e817fc623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274210180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.274210180
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.923164227
Short name T87
Test name
Test status
Simulation time 108094714 ps
CPU time 0.73 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 195892 kb
Host smart-ab0a5a08-90e5-4d09-b265-a4bc22b51f45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923164227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.923164227
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3860966291
Short name T393
Test name
Test status
Simulation time 10251505590 ps
CPU time 102.84 seconds
Started Jul 03 04:26:08 PM PDT 24
Finished Jul 03 04:27:52 PM PDT 24
Peak memory 198624 kb
Host smart-43e05824-479b-4032-b34b-ab549f528b72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860966291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3860966291
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.770976545
Short name T274
Test name
Test status
Simulation time 22624379 ps
CPU time 0.62 seconds
Started Jul 03 04:25:29 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 194808 kb
Host smart-a625909a-73e5-4984-849d-845f313dda5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770976545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.770976545
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3703374398
Short name T77
Test name
Test status
Simulation time 97075698 ps
CPU time 0.88 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 196480 kb
Host smart-e6de5848-167b-4847-84ce-81f670341b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703374398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3703374398
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3995260769
Short name T200
Test name
Test status
Simulation time 2473255488 ps
CPU time 17.13 seconds
Started Jul 03 04:25:55 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 197400 kb
Host smart-0decf024-43f1-4ac2-8558-e7a6fa6c8822
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995260769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3995260769
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3509628044
Short name T427
Test name
Test status
Simulation time 72194978 ps
CPU time 0.63 seconds
Started Jul 03 04:25:27 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 195812 kb
Host smart-2433af2c-1816-49c9-b4d5-23dad8c5938a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509628044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3509628044
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3637432438
Short name T556
Test name
Test status
Simulation time 26788865 ps
CPU time 0.68 seconds
Started Jul 03 04:25:55 PM PDT 24
Finished Jul 03 04:25:56 PM PDT 24
Peak memory 194988 kb
Host smart-04732888-b5ae-48bc-9291-c49a3eb76ea7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637432438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3637432438
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1706448058
Short name T505
Test name
Test status
Simulation time 82161404 ps
CPU time 0.99 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:25:45 PM PDT 24
Peak memory 196568 kb
Host smart-2a1a9867-33dc-4611-a3c4-837757ba69a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706448058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1706448058
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3707207149
Short name T180
Test name
Test status
Simulation time 536469113 ps
CPU time 2.69 seconds
Started Jul 03 04:25:40 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 197172 kb
Host smart-935c9a98-3427-40df-bc70-625dbf8d7482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707207149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3707207149
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.960256098
Short name T693
Test name
Test status
Simulation time 147972969 ps
CPU time 0.91 seconds
Started Jul 03 04:25:59 PM PDT 24
Finished Jul 03 04:26:00 PM PDT 24
Peak memory 197420 kb
Host smart-6978375e-ea72-4d0e-bbb7-e2ab1dde94eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960256098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.960256098
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2312449239
Short name T587
Test name
Test status
Simulation time 293834316 ps
CPU time 1.06 seconds
Started Jul 03 04:25:30 PM PDT 24
Finished Jul 03 04:25:32 PM PDT 24
Peak memory 197364 kb
Host smart-ffee5ecb-51f3-48ef-91da-fd022018ab55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312449239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2312449239
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.977257145
Short name T708
Test name
Test status
Simulation time 1266362763 ps
CPU time 4 seconds
Started Jul 03 04:25:56 PM PDT 24
Finished Jul 03 04:26:00 PM PDT 24
Peak memory 198536 kb
Host smart-06e0d803-20fb-4373-8ff7-becafa8c901e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977257145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.977257145
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3653664025
Short name T182
Test name
Test status
Simulation time 167229847 ps
CPU time 1.22 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 196232 kb
Host smart-0f1c4801-16e6-4ddd-854d-74000c71ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653664025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3653664025
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3899741305
Short name T512
Test name
Test status
Simulation time 106147051 ps
CPU time 0.89 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:30 PM PDT 24
Peak memory 197460 kb
Host smart-c955af31-6199-4d80-8fe3-f9c58fbaef10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899741305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3899741305
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2930027936
Short name T603
Test name
Test status
Simulation time 69384047358 ps
CPU time 155.62 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:28:17 PM PDT 24
Peak memory 198588 kb
Host smart-cf11742a-77c1-4a4c-b04d-a54268471a52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930027936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2930027936
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1288045086
Short name T672
Test name
Test status
Simulation time 55844736 ps
CPU time 0.59 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 195504 kb
Host smart-09793360-b9c8-42e3-9285-3b35611f6fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288045086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1288045086
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3099783182
Short name T170
Test name
Test status
Simulation time 438227249 ps
CPU time 0.87 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 197276 kb
Host smart-4b45cf57-cd0a-428c-bf4a-f49c96665151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099783182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3099783182
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3353551267
Short name T62
Test name
Test status
Simulation time 1545173616 ps
CPU time 11.19 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:38 PM PDT 24
Peak memory 198576 kb
Host smart-0edf89bc-9483-439b-bf98-85170acf9e7f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353551267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3353551267
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2330294839
Short name T72
Test name
Test status
Simulation time 128872302 ps
CPU time 0.87 seconds
Started Jul 03 04:26:21 PM PDT 24
Finished Jul 03 04:26:23 PM PDT 24
Peak memory 197832 kb
Host smart-80edc42f-9dc7-4a8a-983d-f212937c46b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330294839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2330294839
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.530019540
Short name T237
Test name
Test status
Simulation time 96694591 ps
CPU time 0.71 seconds
Started Jul 03 04:25:51 PM PDT 24
Finished Jul 03 04:25:52 PM PDT 24
Peak memory 195744 kb
Host smart-96522efc-a08f-448f-a57f-f836f0ca7be0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530019540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.530019540
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2337922678
Short name T236
Test name
Test status
Simulation time 209150091 ps
CPU time 2.22 seconds
Started Jul 03 04:25:31 PM PDT 24
Finished Jul 03 04:25:34 PM PDT 24
Peak memory 198664 kb
Host smart-af30b682-0013-40a6-8077-93a49c132d9c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337922678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2337922678
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2177235074
Short name T564
Test name
Test status
Simulation time 138711678 ps
CPU time 0.93 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 195988 kb
Host smart-0f856caa-20e9-488c-bf81-cb9598c74d36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177235074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2177235074
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1911912788
Short name T392
Test name
Test status
Simulation time 27009506 ps
CPU time 0.75 seconds
Started Jul 03 04:25:52 PM PDT 24
Finished Jul 03 04:25:53 PM PDT 24
Peak memory 196600 kb
Host smart-98daafb3-1a6c-4607-a6da-02685247d3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911912788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1911912788
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1380800365
Short name T688
Test name
Test status
Simulation time 37772952 ps
CPU time 0.75 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:30 PM PDT 24
Peak memory 196600 kb
Host smart-46f5d5b8-cedc-4d1d-9e93-c6375abf257a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380800365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1380800365
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2413706708
Short name T167
Test name
Test status
Simulation time 943768698 ps
CPU time 3.73 seconds
Started Jul 03 04:25:56 PM PDT 24
Finished Jul 03 04:26:00 PM PDT 24
Peak memory 198492 kb
Host smart-efbec26d-f6e8-4e67-8a82-a19cefc4b415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413706708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2413706708
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.61133339
Short name T654
Test name
Test status
Simulation time 108275926 ps
CPU time 1.35 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 198596 kb
Host smart-189571fc-093b-4653-97bb-f85f6ca3e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61133339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.61133339
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1938751522
Short name T483
Test name
Test status
Simulation time 49953127 ps
CPU time 1.06 seconds
Started Jul 03 04:25:46 PM PDT 24
Finished Jul 03 04:25:47 PM PDT 24
Peak memory 196404 kb
Host smart-7b765a7c-f0f5-4647-b503-351cfe68fb7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938751522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1938751522
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.4111660115
Short name T642
Test name
Test status
Simulation time 5806089849 ps
CPU time 119.86 seconds
Started Jul 03 04:26:02 PM PDT 24
Finished Jul 03 04:28:03 PM PDT 24
Peak memory 198652 kb
Host smart-6edab15a-234e-434a-9845-99239f7062e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111660115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.4111660115
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3928634467
Short name T528
Test name
Test status
Simulation time 54644038227 ps
CPU time 1466.2 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:50:10 PM PDT 24
Peak memory 198784 kb
Host smart-cef22d3e-d209-4930-8be4-d629d36c6502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3928634467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3928634467
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1615064706
Short name T303
Test name
Test status
Simulation time 24386641 ps
CPU time 0.57 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:25:45 PM PDT 24
Peak memory 194624 kb
Host smart-999ff223-7ff5-432d-9a25-2bb874488a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615064706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1615064706
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.452559249
Short name T319
Test name
Test status
Simulation time 46423631 ps
CPU time 0.8 seconds
Started Jul 03 04:25:52 PM PDT 24
Finished Jul 03 04:25:53 PM PDT 24
Peak memory 195400 kb
Host smart-46a25891-7553-4857-a5ed-896e7dfaa572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452559249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.452559249
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1424324637
Short name T589
Test name
Test status
Simulation time 457076687 ps
CPU time 23.32 seconds
Started Jul 03 04:25:34 PM PDT 24
Finished Jul 03 04:25:57 PM PDT 24
Peak memory 197504 kb
Host smart-37171fcd-22bd-458f-9767-6771e0d78a65
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424324637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1424324637
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2835596151
Short name T84
Test name
Test status
Simulation time 436476068 ps
CPU time 0.86 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 197028 kb
Host smart-608060ea-e6d4-4f5e-85e0-fe0306db3e9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835596151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2835596151
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.114333042
Short name T172
Test name
Test status
Simulation time 22994769 ps
CPU time 0.74 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:25:45 PM PDT 24
Peak memory 196164 kb
Host smart-26081c7c-5829-4161-993e-10dc6dc4072b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114333042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.114333042
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1713927396
Short name T611
Test name
Test status
Simulation time 204962952 ps
CPU time 2.51 seconds
Started Jul 03 04:26:08 PM PDT 24
Finished Jul 03 04:26:11 PM PDT 24
Peak memory 198620 kb
Host smart-3dc8864e-5c53-478d-9d2d-a6818b200b60
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713927396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1713927396
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3554868741
Short name T333
Test name
Test status
Simulation time 308044666 ps
CPU time 1.53 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 196644 kb
Host smart-90d6a297-8368-41f5-a0a8-67a527671c8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554868741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3554868741
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1505431920
Short name T576
Test name
Test status
Simulation time 110835086 ps
CPU time 1 seconds
Started Jul 03 04:25:51 PM PDT 24
Finished Jul 03 04:25:52 PM PDT 24
Peak memory 196560 kb
Host smart-61425a79-e405-4fe9-8f9e-b4995df3a48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505431920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1505431920
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3767738105
Short name T398
Test name
Test status
Simulation time 45721498 ps
CPU time 0.72 seconds
Started Jul 03 04:25:58 PM PDT 24
Finished Jul 03 04:25:59 PM PDT 24
Peak memory 196524 kb
Host smart-c4ec0283-fb5b-47a5-922b-745d5dfd6906
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767738105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3767738105
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1015474258
Short name T361
Test name
Test status
Simulation time 184698701 ps
CPU time 3.96 seconds
Started Jul 03 04:25:55 PM PDT 24
Finished Jul 03 04:25:59 PM PDT 24
Peak memory 198476 kb
Host smart-d79835ec-0aeb-4737-a1e3-1cfe5b73c52f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015474258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1015474258
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1165550212
Short name T348
Test name
Test status
Simulation time 38410013 ps
CPU time 1.13 seconds
Started Jul 03 04:25:36 PM PDT 24
Finished Jul 03 04:25:38 PM PDT 24
Peak memory 197120 kb
Host smart-9057217f-9575-41c8-aad1-ae166891346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165550212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1165550212
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.233236128
Short name T580
Test name
Test status
Simulation time 322321901 ps
CPU time 1.21 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:25:42 PM PDT 24
Peak memory 196952 kb
Host smart-2558a5d4-a625-4de4-8697-3da037336307
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233236128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.233236128
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3229805801
Short name T88
Test name
Test status
Simulation time 279436114648 ps
CPU time 1564.21 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:52:23 PM PDT 24
Peak memory 198876 kb
Host smart-77709eec-c68f-41a7-8b0b-c1188b3d4ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3229805801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3229805801
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.181059874
Short name T661
Test name
Test status
Simulation time 131644174 ps
CPU time 0.54 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 194608 kb
Host smart-d7395738-4122-45f5-8d35-f3c0e044938a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181059874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.181059874
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1675536991
Short name T626
Test name
Test status
Simulation time 60514224 ps
CPU time 0.7 seconds
Started Jul 03 04:26:03 PM PDT 24
Finished Jul 03 04:26:04 PM PDT 24
Peak memory 195404 kb
Host smart-f73ba653-c1ae-4154-9ab9-eb7d1bf5d9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675536991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1675536991
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3442708450
Short name T492
Test name
Test status
Simulation time 1004429593 ps
CPU time 25.85 seconds
Started Jul 03 04:25:45 PM PDT 24
Finished Jul 03 04:26:12 PM PDT 24
Peak memory 196160 kb
Host smart-e54b3193-093a-47f3-a310-f06476d7ddd8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442708450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3442708450
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3798546230
Short name T380
Test name
Test status
Simulation time 61000961 ps
CPU time 0.92 seconds
Started Jul 03 04:25:48 PM PDT 24
Finished Jul 03 04:25:50 PM PDT 24
Peak memory 198360 kb
Host smart-71181516-c85a-431e-b6a9-bc95cb3d5954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798546230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3798546230
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2588171426
Short name T149
Test name
Test status
Simulation time 36364129 ps
CPU time 0.82 seconds
Started Jul 03 04:25:58 PM PDT 24
Finished Jul 03 04:25:59 PM PDT 24
Peak memory 196276 kb
Host smart-8700b0a4-f43d-4558-a15b-c17b24bf6685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588171426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2588171426
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.312185247
Short name T604
Test name
Test status
Simulation time 143767648 ps
CPU time 2.81 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:25:44 PM PDT 24
Peak memory 196832 kb
Host smart-ef424306-e467-4ba4-87eb-0d92c5f07e53
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312185247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.312185247
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1860552442
Short name T40
Test name
Test status
Simulation time 352216462 ps
CPU time 1.96 seconds
Started Jul 03 04:25:44 PM PDT 24
Finished Jul 03 04:25:47 PM PDT 24
Peak memory 197924 kb
Host smart-24bea777-a036-4a6a-aa77-1a33645182b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860552442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1860552442
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3094615583
Short name T698
Test name
Test status
Simulation time 132574562 ps
CPU time 1.29 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:25:42 PM PDT 24
Peak memory 197584 kb
Host smart-9dd24711-c640-4789-adc7-3e926d44b096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094615583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3094615583
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.209752186
Short name T316
Test name
Test status
Simulation time 102131762 ps
CPU time 0.73 seconds
Started Jul 03 04:25:39 PM PDT 24
Finished Jul 03 04:25:40 PM PDT 24
Peak memory 195996 kb
Host smart-fc98c8b5-1e0a-4265-ac0d-fd57394c4fef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209752186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.209752186
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.249066387
Short name T195
Test name
Test status
Simulation time 705213028 ps
CPU time 4.44 seconds
Started Jul 03 04:25:55 PM PDT 24
Finished Jul 03 04:26:00 PM PDT 24
Peak memory 198472 kb
Host smart-e1000db2-3f98-44da-bd39-b4ada648dbd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249066387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.249066387
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.981334095
Short name T228
Test name
Test status
Simulation time 80854992 ps
CPU time 1.2 seconds
Started Jul 03 04:25:50 PM PDT 24
Finished Jul 03 04:25:51 PM PDT 24
Peak memory 197108 kb
Host smart-6100830f-fd39-42e1-8a0c-6db82717acd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981334095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.981334095
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.938915406
Short name T599
Test name
Test status
Simulation time 153804942 ps
CPU time 0.84 seconds
Started Jul 03 04:25:46 PM PDT 24
Finished Jul 03 04:25:48 PM PDT 24
Peak memory 196784 kb
Host smart-8e42c4f9-4942-4507-bd0f-cb1aaa539385
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938915406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.938915406
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3310226860
Short name T707
Test name
Test status
Simulation time 12101762661 ps
CPU time 152.96 seconds
Started Jul 03 04:25:52 PM PDT 24
Finished Jul 03 04:28:31 PM PDT 24
Peak memory 198696 kb
Host smart-b41bd6ee-6528-4bdb-a9df-4a5f09495f08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310226860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3310226860
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.944905408
Short name T405
Test name
Test status
Simulation time 108609102809 ps
CPU time 355.87 seconds
Started Jul 03 04:25:48 PM PDT 24
Finished Jul 03 04:31:44 PM PDT 24
Peak memory 198768 kb
Host smart-85f0ee64-070d-42d8-b721-ccd7a6d31636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=944905408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.944905408
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.4287342217
Short name T374
Test name
Test status
Simulation time 55151963 ps
CPU time 0.58 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:44 PM PDT 24
Peak memory 194488 kb
Host smart-c072e11e-1972-48f3-ac69-37c9de73404b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287342217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.4287342217
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2629226375
Short name T279
Test name
Test status
Simulation time 21624648 ps
CPU time 0.68 seconds
Started Jul 03 04:25:54 PM PDT 24
Finished Jul 03 04:25:55 PM PDT 24
Peak memory 194596 kb
Host smart-bd725da2-7569-4ec5-bac5-a93c8ab7151d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629226375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2629226375
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1234359950
Short name T410
Test name
Test status
Simulation time 391579324 ps
CPU time 10.67 seconds
Started Jul 03 04:26:04 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 196164 kb
Host smart-ce52a5e9-d6e9-4867-9700-1d64848ed95d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234359950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1234359950
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3073994232
Short name T168
Test name
Test status
Simulation time 67900484 ps
CPU time 0.78 seconds
Started Jul 03 04:26:01 PM PDT 24
Finished Jul 03 04:26:03 PM PDT 24
Peak memory 196148 kb
Host smart-fabfc3b2-fc4f-4e75-991b-baab4be3b436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073994232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3073994232
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1610951918
Short name T616
Test name
Test status
Simulation time 98218265 ps
CPU time 1.47 seconds
Started Jul 03 04:25:47 PM PDT 24
Finished Jul 03 04:25:49 PM PDT 24
Peak memory 198576 kb
Host smart-122d6e01-7bc9-411d-aec0-bbfe954ed291
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610951918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1610951918
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2289456893
Short name T526
Test name
Test status
Simulation time 69394505 ps
CPU time 2.7 seconds
Started Jul 03 04:25:53 PM PDT 24
Finished Jul 03 04:25:57 PM PDT 24
Peak memory 198580 kb
Host smart-a0f7f017-37fa-40b7-ae96-a000b2c74559
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289456893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2289456893
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3507646463
Short name T340
Test name
Test status
Simulation time 1245477483 ps
CPU time 2.38 seconds
Started Jul 03 04:25:37 PM PDT 24
Finished Jul 03 04:25:45 PM PDT 24
Peak memory 197576 kb
Host smart-b602e5f1-8f2b-49b5-a74f-55fa280772d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507646463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3507646463
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3483445713
Short name T682
Test name
Test status
Simulation time 177052047 ps
CPU time 0.93 seconds
Started Jul 03 04:25:37 PM PDT 24
Finished Jul 03 04:25:39 PM PDT 24
Peak memory 196552 kb
Host smart-e40b5f03-2caf-4848-b7fa-884ac3399a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483445713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3483445713
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2402324595
Short name T649
Test name
Test status
Simulation time 64754322 ps
CPU time 1.06 seconds
Started Jul 03 04:25:57 PM PDT 24
Finished Jul 03 04:25:59 PM PDT 24
Peak memory 196548 kb
Host smart-be6ab087-edef-4844-b00f-c30230280478
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402324595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2402324595
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.116427240
Short name T712
Test name
Test status
Simulation time 74088322 ps
CPU time 1.77 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:44 PM PDT 24
Peak memory 198012 kb
Host smart-06de714f-5532-424d-9b6b-37cc97cbd5ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116427240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.116427240
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3948191541
Short name T480
Test name
Test status
Simulation time 285852024 ps
CPU time 0.83 seconds
Started Jul 03 04:25:51 PM PDT 24
Finished Jul 03 04:25:52 PM PDT 24
Peak memory 195696 kb
Host smart-35882dd7-374c-46ea-a33a-5bff346b1c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948191541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3948191541
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1477402031
Short name T290
Test name
Test status
Simulation time 79892846 ps
CPU time 1.36 seconds
Started Jul 03 04:25:47 PM PDT 24
Finished Jul 03 04:25:49 PM PDT 24
Peak memory 197432 kb
Host smart-d727838b-d19d-4280-b92a-cc19b083f15a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477402031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1477402031
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.334178723
Short name T136
Test name
Test status
Simulation time 15381133909 ps
CPU time 97.27 seconds
Started Jul 03 04:25:59 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 198688 kb
Host smart-9182a200-b6cb-40de-8fb3-c606e4a78dda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334178723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.334178723
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2995196058
Short name T78
Test name
Test status
Simulation time 64353364669 ps
CPU time 1412.11 seconds
Started Jul 03 04:25:45 PM PDT 24
Finished Jul 03 04:49:18 PM PDT 24
Peak memory 198820 kb
Host smart-89e26cea-6162-47a1-a14a-24dded4493a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2995196058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2995196058
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2870732102
Short name T156
Test name
Test status
Simulation time 45341212 ps
CPU time 0.58 seconds
Started Jul 03 04:25:46 PM PDT 24
Finished Jul 03 04:25:47 PM PDT 24
Peak memory 194736 kb
Host smart-2579187e-3ecb-4da7-b8e2-c215e9e6c355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870732102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2870732102
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.891271048
Short name T629
Test name
Test status
Simulation time 16489651 ps
CPU time 0.66 seconds
Started Jul 03 04:25:56 PM PDT 24
Finished Jul 03 04:25:57 PM PDT 24
Peak memory 195420 kb
Host smart-c798b533-47bd-4866-b7ca-a2679850bac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891271048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.891271048
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2808600109
Short name T489
Test name
Test status
Simulation time 622418253 ps
CPU time 3.64 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 195924 kb
Host smart-64cf1ec5-e730-409f-ac0a-39c473fcce82
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808600109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2808600109
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.520129615
Short name T447
Test name
Test status
Simulation time 47605016 ps
CPU time 0.81 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 196456 kb
Host smart-91deb563-8746-45fc-811a-d925805b4d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520129615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.520129615
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3934701792
Short name T607
Test name
Test status
Simulation time 45041209 ps
CPU time 1.22 seconds
Started Jul 03 04:25:32 PM PDT 24
Finished Jul 03 04:25:33 PM PDT 24
Peak memory 197132 kb
Host smart-a84c39f6-ceb5-4161-8d14-82ee09f83e88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934701792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3934701792
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2953965132
Short name T387
Test name
Test status
Simulation time 1068509824 ps
CPU time 2.52 seconds
Started Jul 03 04:26:04 PM PDT 24
Finished Jul 03 04:26:06 PM PDT 24
Peak memory 198584 kb
Host smart-ecdabd3c-5422-41b8-b24d-6229863bdbdf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953965132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2953965132
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3505376639
Short name T175
Test name
Test status
Simulation time 204291116 ps
CPU time 2.41 seconds
Started Jul 03 04:25:59 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 197664 kb
Host smart-0988b479-65a7-4d3b-9339-cfe492da32c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505376639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3505376639
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.149418538
Short name T161
Test name
Test status
Simulation time 58076780 ps
CPU time 1.08 seconds
Started Jul 03 04:25:39 PM PDT 24
Finished Jul 03 04:25:40 PM PDT 24
Peak memory 196620 kb
Host smart-04d25a73-528a-40dc-98ad-4f2e58fb6c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149418538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.149418538
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3144753589
Short name T295
Test name
Test status
Simulation time 154647905 ps
CPU time 0.88 seconds
Started Jul 03 04:25:57 PM PDT 24
Finished Jul 03 04:25:59 PM PDT 24
Peak memory 196668 kb
Host smart-53e6c096-b730-40af-a4b3-eaf91bced5db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144753589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3144753589
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.4294584945
Short name T697
Test name
Test status
Simulation time 378653692 ps
CPU time 6.1 seconds
Started Jul 03 04:25:55 PM PDT 24
Finished Jul 03 04:26:01 PM PDT 24
Peak memory 198516 kb
Host smart-9c30f774-a5a8-41d5-bb53-b5adabcaf280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294584945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.4294584945
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1065171524
Short name T485
Test name
Test status
Simulation time 201679617 ps
CPU time 0.95 seconds
Started Jul 03 04:25:37 PM PDT 24
Finished Jul 03 04:25:39 PM PDT 24
Peak memory 196848 kb
Host smart-66519530-ad4d-46bd-bbbb-3d359e53566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065171524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1065171524
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1353939182
Short name T537
Test name
Test status
Simulation time 127931618 ps
CPU time 0.97 seconds
Started Jul 03 04:25:40 PM PDT 24
Finished Jul 03 04:25:42 PM PDT 24
Peak memory 196288 kb
Host smart-9ca44091-a5df-4fae-8f81-cfdd6533e0f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353939182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1353939182
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2269866620
Short name T440
Test name
Test status
Simulation time 7300222874 ps
CPU time 102.54 seconds
Started Jul 03 04:25:50 PM PDT 24
Finished Jul 03 04:27:34 PM PDT 24
Peak memory 198760 kb
Host smart-f8a43df3-b0a8-47c0-9d64-8ffe740b4f5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269866620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2269866620
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3767964981
Short name T83
Test name
Test status
Simulation time 42384683 ps
CPU time 0.58 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 194484 kb
Host smart-63de7803-cb2e-46fb-88a5-7e377504a885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767964981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3767964981
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1437011088
Short name T646
Test name
Test status
Simulation time 43808686 ps
CPU time 0.84 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:07 PM PDT 24
Peak memory 197044 kb
Host smart-42c3b207-2cc1-4f85-8966-355cfd91eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437011088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1437011088
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2272823737
Short name T529
Test name
Test status
Simulation time 1794860245 ps
CPU time 11.84 seconds
Started Jul 03 04:25:52 PM PDT 24
Finished Jul 03 04:26:05 PM PDT 24
Peak memory 197712 kb
Host smart-48e146d7-51c3-4ec0-a72d-594b501efb8a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272823737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2272823737
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.814739918
Short name T428
Test name
Test status
Simulation time 60248327 ps
CPU time 0.97 seconds
Started Jul 03 04:26:47 PM PDT 24
Finished Jul 03 04:26:49 PM PDT 24
Peak memory 196656 kb
Host smart-1ab6c2d4-5476-40be-913a-ffe1ca74e6b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814739918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.814739918
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2833599487
Short name T379
Test name
Test status
Simulation time 48875313 ps
CPU time 0.62 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:25:45 PM PDT 24
Peak memory 194864 kb
Host smart-52cad4f0-258e-4d24-a35f-d89c77f4c941
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833599487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2833599487
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.4023267544
Short name T286
Test name
Test status
Simulation time 325881391 ps
CPU time 3.16 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:25:47 PM PDT 24
Peak memory 198572 kb
Host smart-4e333e3c-f293-4829-9f86-828e60ddc90c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023267544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.4023267544
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3932069609
Short name T457
Test name
Test status
Simulation time 115449381 ps
CPU time 3.14 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 196288 kb
Host smart-c52defd6-86fd-4b7e-a372-cc8a8a770a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932069609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3932069609
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1742935194
Short name T650
Test name
Test status
Simulation time 57561321 ps
CPU time 0.67 seconds
Started Jul 03 04:26:01 PM PDT 24
Finished Jul 03 04:26:03 PM PDT 24
Peak memory 195540 kb
Host smart-407902db-633d-41b4-8a1a-5108baee4d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742935194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1742935194
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2923347140
Short name T407
Test name
Test status
Simulation time 72583832 ps
CPU time 0.72 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:25:45 PM PDT 24
Peak memory 195988 kb
Host smart-81027699-50f3-4bee-a770-b087c25848f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923347140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2923347140
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3310839991
Short name T628
Test name
Test status
Simulation time 284959655 ps
CPU time 4.54 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:47 PM PDT 24
Peak memory 198484 kb
Host smart-9a117a66-0aba-4678-9847-fc8bd78d13af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310839991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3310839991
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.846931829
Short name T162
Test name
Test status
Simulation time 861621718 ps
CPU time 1.32 seconds
Started Jul 03 04:25:59 PM PDT 24
Finished Jul 03 04:26:01 PM PDT 24
Peak memory 198568 kb
Host smart-ca5a81d7-9c63-4004-96da-2b2a7f0c8650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846931829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.846931829
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3647767609
Short name T41
Test name
Test status
Simulation time 40609820 ps
CPU time 0.76 seconds
Started Jul 03 04:25:53 PM PDT 24
Finished Jul 03 04:25:54 PM PDT 24
Peak memory 196564 kb
Host smart-f5138042-a0aa-4457-a90d-3b906afaedbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647767609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3647767609
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.288989499
Short name T451
Test name
Test status
Simulation time 49149916240 ps
CPU time 137.28 seconds
Started Jul 03 04:26:02 PM PDT 24
Finished Jul 03 04:28:20 PM PDT 24
Peak memory 198740 kb
Host smart-1a3bc2fc-51c9-483f-be88-eae0aeca7ea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288989499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.288989499
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1853408962
Short name T311
Test name
Test status
Simulation time 51297694 ps
CPU time 0.59 seconds
Started Jul 03 04:25:54 PM PDT 24
Finished Jul 03 04:25:55 PM PDT 24
Peak memory 194772 kb
Host smart-b45e999a-d42a-411c-9e03-00dfc62e0848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853408962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1853408962
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1264204078
Short name T262
Test name
Test status
Simulation time 53410957 ps
CPU time 0.68 seconds
Started Jul 03 04:25:56 PM PDT 24
Finished Jul 03 04:25:57 PM PDT 24
Peak memory 194736 kb
Host smart-acf9708e-f849-4a2a-9890-e2c6947c0e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264204078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1264204078
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4065703922
Short name T664
Test name
Test status
Simulation time 561393503 ps
CPU time 19.44 seconds
Started Jul 03 04:26:09 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 197284 kb
Host smart-a56f9d2f-1ddf-4aef-9a40-3193416d7320
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065703922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4065703922
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.4261079287
Short name T331
Test name
Test status
Simulation time 200406586 ps
CPU time 0.96 seconds
Started Jul 03 04:25:50 PM PDT 24
Finished Jul 03 04:25:51 PM PDT 24
Peak memory 196944 kb
Host smart-e719402c-4fa2-4fde-9da2-d154a2f38206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261079287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.4261079287
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2535698341
Short name T462
Test name
Test status
Simulation time 29453406 ps
CPU time 0.75 seconds
Started Jul 03 04:25:57 PM PDT 24
Finished Jul 03 04:25:59 PM PDT 24
Peak memory 196608 kb
Host smart-aa577ea7-484c-4763-92ca-df523f820afc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535698341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2535698341
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.75898354
Short name T694
Test name
Test status
Simulation time 576419911 ps
CPU time 1.71 seconds
Started Jul 03 04:25:59 PM PDT 24
Finished Jul 03 04:26:01 PM PDT 24
Peak memory 198772 kb
Host smart-61474bc8-be9c-4846-a056-4e7a12bf79c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75898354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.gpio_intr_with_filter_rand_intr_event.75898354
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.250503770
Short name T221
Test name
Test status
Simulation time 78633584 ps
CPU time 1.34 seconds
Started Jul 03 04:25:56 PM PDT 24
Finished Jul 03 04:25:58 PM PDT 24
Peak memory 197444 kb
Host smart-13cf7a24-0033-4c70-9e94-08fec11329b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250503770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
250503770
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2822832899
Short name T703
Test name
Test status
Simulation time 75669655 ps
CPU time 0.77 seconds
Started Jul 03 04:25:44 PM PDT 24
Finished Jul 03 04:25:46 PM PDT 24
Peak memory 196136 kb
Host smart-07e3c5ab-9c76-445d-9b0f-806919f571c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822832899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2822832899
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.530097726
Short name T248
Test name
Test status
Simulation time 266727986 ps
CPU time 0.83 seconds
Started Jul 03 04:26:01 PM PDT 24
Finished Jul 03 04:26:03 PM PDT 24
Peak memory 197036 kb
Host smart-efa74d19-0c30-4f0a-94fe-62f55d0b6847
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530097726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.530097726
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3690575727
Short name T189
Test name
Test status
Simulation time 190837107 ps
CPU time 3.37 seconds
Started Jul 03 04:25:46 PM PDT 24
Finished Jul 03 04:25:50 PM PDT 24
Peak memory 198608 kb
Host smart-4fea15a7-ca53-44b4-a59f-414e95c4c72e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690575727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3690575727
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.324119968
Short name T500
Test name
Test status
Simulation time 159728148 ps
CPU time 0.84 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:01 PM PDT 24
Peak memory 196692 kb
Host smart-fd71a5a6-7977-4e27-8b4a-a10ee03ef0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324119968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.324119968
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2124520468
Short name T502
Test name
Test status
Simulation time 181471604 ps
CPU time 1.3 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 196948 kb
Host smart-9b766380-fc65-4fa8-905b-806ef3d6975f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124520468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2124520468
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2996463758
Short name T49
Test name
Test status
Simulation time 17205500636 ps
CPU time 146.71 seconds
Started Jul 03 04:25:58 PM PDT 24
Finished Jul 03 04:28:25 PM PDT 24
Peak memory 198712 kb
Host smart-1a274adc-d214-425b-a440-73157610fdad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996463758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2996463758
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2361221889
Short name T400
Test name
Test status
Simulation time 38664426 ps
CPU time 0.55 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 195656 kb
Host smart-d31e7a90-778a-4b8d-9b6c-d8d23a241bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361221889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2361221889
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4078911834
Short name T648
Test name
Test status
Simulation time 14312183 ps
CPU time 0.59 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 194412 kb
Host smart-6a629d9c-472f-44de-9f50-e850eeb3df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078911834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4078911834
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1166601994
Short name T459
Test name
Test status
Simulation time 1284727392 ps
CPU time 10.33 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:33 PM PDT 24
Peak memory 198672 kb
Host smart-b2b40339-5596-42ed-ac3e-075c35ffffbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166601994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1166601994
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.597509447
Short name T497
Test name
Test status
Simulation time 255357596 ps
CPU time 0.95 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 197044 kb
Host smart-d9bc75b5-c48b-4deb-bf1d-3c31c15b4561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597509447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.597509447
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1848142418
Short name T511
Test name
Test status
Simulation time 405617183 ps
CPU time 1.05 seconds
Started Jul 03 04:25:45 PM PDT 24
Finished Jul 03 04:25:47 PM PDT 24
Peak memory 197516 kb
Host smart-6b616601-5860-4535-8128-f48d34f8e8de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848142418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1848142418
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4119709924
Short name T381
Test name
Test status
Simulation time 37635627 ps
CPU time 1.57 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 198624 kb
Host smart-fc01e407-b68e-4bbc-b998-73ce93c32644
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119709924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.4119709924
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.572680926
Short name T74
Test name
Test status
Simulation time 64303156 ps
CPU time 1.42 seconds
Started Jul 03 04:25:33 PM PDT 24
Finished Jul 03 04:25:34 PM PDT 24
Peak memory 196980 kb
Host smart-50a443f4-5910-4c68-b399-7dd0bd3af7b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572680926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.572680926
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2443081886
Short name T418
Test name
Test status
Simulation time 65193997 ps
CPU time 1.23 seconds
Started Jul 03 04:25:46 PM PDT 24
Finished Jul 03 04:25:48 PM PDT 24
Peak memory 197584 kb
Host smart-debc3fbc-ef40-4679-b19c-01aa60d34041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443081886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2443081886
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.23272495
Short name T254
Test name
Test status
Simulation time 56455213 ps
CPU time 1.2 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:25:25 PM PDT 24
Peak memory 198528 kb
Host smart-858d45d7-3c71-4205-964a-8b88eb8b129e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23272495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_p
ulldown.23272495
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2785284722
Short name T465
Test name
Test status
Simulation time 79484367 ps
CPU time 3.3 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:33 PM PDT 24
Peak memory 198564 kb
Host smart-f733a61e-2f0f-43dc-b867-a4d2c73d3032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785284722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2785284722
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1188842665
Short name T55
Test name
Test status
Simulation time 361425160 ps
CPU time 0.91 seconds
Started Jul 03 04:25:38 PM PDT 24
Finished Jul 03 04:25:39 PM PDT 24
Peak memory 215300 kb
Host smart-c038b9ca-bdef-4c89-a27e-97bed1b98cec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188842665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1188842665
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2225984161
Short name T468
Test name
Test status
Simulation time 54468716 ps
CPU time 1 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 196428 kb
Host smart-c639c24f-02e9-4d21-8198-1e4e54dd0194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225984161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2225984161
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1616021588
Short name T591
Test name
Test status
Simulation time 160256694 ps
CPU time 0.96 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 196796 kb
Host smart-1fe0eb31-9889-4746-9cf0-4dc6fd55b4c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616021588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1616021588
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1376048233
Short name T363
Test name
Test status
Simulation time 14595719621 ps
CPU time 139.21 seconds
Started Jul 03 04:25:27 PM PDT 24
Finished Jul 03 04:27:48 PM PDT 24
Peak memory 198588 kb
Host smart-1dba5c45-126c-4b65-abd7-d08c8d07e5db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376048233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1376048233
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.198700091
Short name T278
Test name
Test status
Simulation time 37625355 ps
CPU time 0.56 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 194436 kb
Host smart-5e7fc87b-729e-4031-91d7-90d797a56954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198700091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.198700091
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1944759809
Short name T673
Test name
Test status
Simulation time 53527762 ps
CPU time 0.76 seconds
Started Jul 03 04:25:51 PM PDT 24
Finished Jul 03 04:25:52 PM PDT 24
Peak memory 195720 kb
Host smart-15e75daa-cc75-4795-9f4a-196b04cba907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944759809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1944759809
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1767877524
Short name T187
Test name
Test status
Simulation time 1181447055 ps
CPU time 12.16 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 198436 kb
Host smart-98dcf15f-de25-48a9-8162-47d31d3f7bd1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767877524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1767877524
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1063785814
Short name T624
Test name
Test status
Simulation time 259051263 ps
CPU time 0.85 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:07 PM PDT 24
Peak memory 197020 kb
Host smart-bfed0bf7-b918-447d-b35e-d17d486ac034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063785814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1063785814
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4237869440
Short name T532
Test name
Test status
Simulation time 241504975 ps
CPU time 1.04 seconds
Started Jul 03 04:26:08 PM PDT 24
Finished Jul 03 04:26:10 PM PDT 24
Peak memory 196468 kb
Host smart-a87fd061-07d1-43dd-9116-9ed612302820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237869440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4237869440
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2862002913
Short name T296
Test name
Test status
Simulation time 94881195 ps
CPU time 3.5 seconds
Started Jul 03 04:25:58 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 198520 kb
Host smart-a9ad0390-7074-4f52-ab52-153c3f77be58
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862002913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2862002913
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2902194666
Short name T515
Test name
Test status
Simulation time 118915139 ps
CPU time 1.52 seconds
Started Jul 03 04:25:44 PM PDT 24
Finished Jul 03 04:25:47 PM PDT 24
Peak memory 196668 kb
Host smart-9366c6eb-6dd6-45dd-b347-95b310687c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902194666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2902194666
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1363642572
Short name T635
Test name
Test status
Simulation time 87908349 ps
CPU time 1.07 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:44 PM PDT 24
Peak memory 197000 kb
Host smart-929391b4-8a14-4dce-a341-828eca64a311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363642572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1363642572
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.4133214481
Short name T329
Test name
Test status
Simulation time 58495254 ps
CPU time 1.09 seconds
Started Jul 03 04:26:10 PM PDT 24
Finished Jul 03 04:26:12 PM PDT 24
Peak memory 197728 kb
Host smart-2e8b173b-fda2-445e-962f-09b7e7c2a48f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133214481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.4133214481
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1407459393
Short name T409
Test name
Test status
Simulation time 367002932 ps
CPU time 4.5 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:06 PM PDT 24
Peak memory 198604 kb
Host smart-bbcfc07a-976e-46d9-9600-b7c3235f746f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407459393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1407459393
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2342619725
Short name T482
Test name
Test status
Simulation time 134506236 ps
CPU time 1.13 seconds
Started Jul 03 04:25:52 PM PDT 24
Finished Jul 03 04:25:54 PM PDT 24
Peak memory 196268 kb
Host smart-fcba3b6d-7629-477c-b141-3880d942b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342619725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2342619725
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1415516933
Short name T559
Test name
Test status
Simulation time 58483756 ps
CPU time 1 seconds
Started Jul 03 04:25:44 PM PDT 24
Finished Jul 03 04:25:46 PM PDT 24
Peak memory 196288 kb
Host smart-a2f083ba-e8d2-4beb-ac03-463ef0c80e4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415516933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1415516933
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.830310843
Short name T21
Test name
Test status
Simulation time 14228472108 ps
CPU time 150.23 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:28:32 PM PDT 24
Peak memory 198724 kb
Host smart-552f4cca-fa26-4111-bf1f-73aa636ac2a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830310843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.830310843
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.804872511
Short name T525
Test name
Test status
Simulation time 11503466 ps
CPU time 0.58 seconds
Started Jul 03 04:26:03 PM PDT 24
Finished Jul 03 04:26:04 PM PDT 24
Peak memory 194648 kb
Host smart-145f4431-b9de-44d1-9fc7-e17bdeaa8245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804872511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.804872511
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.4054999418
Short name T527
Test name
Test status
Simulation time 79009671 ps
CPU time 0.73 seconds
Started Jul 03 04:25:56 PM PDT 24
Finished Jul 03 04:25:57 PM PDT 24
Peak memory 196564 kb
Host smart-6224d47d-f99f-49a9-914b-97db50b4f1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054999418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.4054999418
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3712464135
Short name T19
Test name
Test status
Simulation time 1208212858 ps
CPU time 17.61 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 197600 kb
Host smart-ebacd15c-2a61-4699-adce-d16b6cdf9f54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712464135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3712464135
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2076346726
Short name T565
Test name
Test status
Simulation time 1002452474 ps
CPU time 0.95 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 197748 kb
Host smart-7e548f93-6d4c-4495-af30-2761cf2a46cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076346726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2076346726
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.731032754
Short name T590
Test name
Test status
Simulation time 21809797 ps
CPU time 0.73 seconds
Started Jul 03 04:26:09 PM PDT 24
Finished Jul 03 04:26:10 PM PDT 24
Peak memory 196012 kb
Host smart-61f0e33f-ba6f-4dac-bc9d-3ec019cc35ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731032754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.731032754
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3946509429
Short name T309
Test name
Test status
Simulation time 72786026 ps
CPU time 1.6 seconds
Started Jul 03 04:26:06 PM PDT 24
Finished Jul 03 04:26:08 PM PDT 24
Peak memory 196912 kb
Host smart-396860c5-71f5-4be4-8e08-058b2150f607
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946509429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3946509429
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1533707119
Short name T178
Test name
Test status
Simulation time 412890610 ps
CPU time 3.03 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 196372 kb
Host smart-aa0298bf-ae4e-45a9-a177-4cfa7312778d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533707119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1533707119
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.4073469475
Short name T552
Test name
Test status
Simulation time 124765442 ps
CPU time 0.78 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 196944 kb
Host smart-8bdacd86-84f9-4e47-9978-70efa24cdb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073469475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.4073469475
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1092488786
Short name T70
Test name
Test status
Simulation time 214691508 ps
CPU time 1.1 seconds
Started Jul 03 04:26:05 PM PDT 24
Finished Jul 03 04:26:07 PM PDT 24
Peak memory 197876 kb
Host smart-324fd259-7b40-4b4a-b37d-fa43995b2f69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092488786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1092488786
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2916946359
Short name T310
Test name
Test status
Simulation time 43679994 ps
CPU time 2.04 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:25:46 PM PDT 24
Peak memory 198376 kb
Host smart-0709fdc3-39d7-47fc-be0a-53dd6ff34271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916946359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2916946359
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3996669883
Short name T358
Test name
Test status
Simulation time 167061952 ps
CPU time 1.31 seconds
Started Jul 03 04:26:10 PM PDT 24
Finished Jul 03 04:26:11 PM PDT 24
Peak memory 196196 kb
Host smart-59985115-82c8-4048-a564-f5c156be9f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996669883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3996669883
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1111707406
Short name T137
Test name
Test status
Simulation time 186618842 ps
CPU time 1.22 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 196788 kb
Host smart-ed024445-a071-44da-af71-b132b0f7fb37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111707406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1111707406
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1417491327
Short name T714
Test name
Test status
Simulation time 38688009481 ps
CPU time 148.97 seconds
Started Jul 03 04:25:56 PM PDT 24
Finished Jul 03 04:28:26 PM PDT 24
Peak memory 198608 kb
Host smart-ee9200c0-60b0-4819-80df-61926100b191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417491327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1417491327
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3174526400
Short name T370
Test name
Test status
Simulation time 17368673 ps
CPU time 0.57 seconds
Started Jul 03 04:26:07 PM PDT 24
Finished Jul 03 04:26:08 PM PDT 24
Peak memory 194708 kb
Host smart-ae87ef33-f20a-44c0-9705-98896f959d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174526400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3174526400
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2119621571
Short name T208
Test name
Test status
Simulation time 25835871 ps
CPU time 0.75 seconds
Started Jul 03 04:26:08 PM PDT 24
Finished Jul 03 04:26:09 PM PDT 24
Peak memory 196028 kb
Host smart-c4ba96bc-f33c-4cb5-aee1-db69ebf73bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119621571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2119621571
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3599465895
Short name T218
Test name
Test status
Simulation time 805099181 ps
CPU time 19.52 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 198564 kb
Host smart-1b2906a6-e878-43d8-8fc8-c35d228422bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599465895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3599465895
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3426427095
Short name T417
Test name
Test status
Simulation time 176294307 ps
CPU time 0.79 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 196260 kb
Host smart-fff10109-0497-4c44-91a1-3523d71b5f56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426427095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3426427095
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1263526402
Short name T155
Test name
Test status
Simulation time 488350324 ps
CPU time 1.09 seconds
Started Jul 03 04:26:05 PM PDT 24
Finished Jul 03 04:26:07 PM PDT 24
Peak memory 196388 kb
Host smart-a1cdba27-b5e7-4864-94d0-59a5050a6525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263526402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1263526402
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.541812917
Short name T226
Test name
Test status
Simulation time 359430793 ps
CPU time 3.46 seconds
Started Jul 03 04:26:08 PM PDT 24
Finished Jul 03 04:26:12 PM PDT 24
Peak memory 198624 kb
Host smart-37868107-082b-4259-83e6-b3f0474a522c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541812917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.541812917
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3201325560
Short name T325
Test name
Test status
Simulation time 133220169 ps
CPU time 2.75 seconds
Started Jul 03 04:26:07 PM PDT 24
Finished Jul 03 04:26:10 PM PDT 24
Peak memory 197576 kb
Host smart-13e4f5c2-752a-4180-b58b-b65fd9141ae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201325560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3201325560
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3363664026
Short name T365
Test name
Test status
Simulation time 86767551 ps
CPU time 1.05 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:17 PM PDT 24
Peak memory 196684 kb
Host smart-c2f76881-5dd6-442b-b1c7-3554903e32f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363664026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3363664026
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1136294698
Short name T602
Test name
Test status
Simulation time 33002499 ps
CPU time 1.05 seconds
Started Jul 03 04:26:04 PM PDT 24
Finished Jul 03 04:26:05 PM PDT 24
Peak memory 196596 kb
Host smart-4d4b0f45-dd10-4990-bdd3-dfcf4666ba03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136294698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1136294698
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4129340205
Short name T61
Test name
Test status
Simulation time 426822643 ps
CPU time 3.85 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:05 PM PDT 24
Peak memory 198636 kb
Host smart-23acb81b-d9b4-4dfc-8a57-916dbe505f9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129340205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.4129340205
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1042880785
Short name T406
Test name
Test status
Simulation time 50888728 ps
CPU time 1.05 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 196936 kb
Host smart-70780d9f-bc4d-4936-b795-be5e551eb2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042880785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1042880785
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2332138039
Short name T614
Test name
Test status
Simulation time 212892876 ps
CPU time 1.1 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 196248 kb
Host smart-80aa270f-5da1-417b-a7d5-800a791801c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332138039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2332138039
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4232273579
Short name T277
Test name
Test status
Simulation time 62249244590 ps
CPU time 180.34 seconds
Started Jul 03 04:26:03 PM PDT 24
Finished Jul 03 04:29:04 PM PDT 24
Peak memory 198760 kb
Host smart-730df14a-d41d-4162-a793-e2be4f234d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232273579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4232273579
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3777483174
Short name T323
Test name
Test status
Simulation time 12216009819 ps
CPU time 264.48 seconds
Started Jul 03 04:26:05 PM PDT 24
Finished Jul 03 04:30:30 PM PDT 24
Peak memory 198720 kb
Host smart-2f2422cd-1b18-4394-9308-feaa2016b803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3777483174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3777483174
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.269925385
Short name T640
Test name
Test status
Simulation time 19896746 ps
CPU time 0.61 seconds
Started Jul 03 04:26:01 PM PDT 24
Finished Jul 03 04:26:03 PM PDT 24
Peak memory 195196 kb
Host smart-9033af40-2af0-49cc-818a-20cbcda976b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269925385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.269925385
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2013718651
Short name T313
Test name
Test status
Simulation time 31378256 ps
CPU time 0.66 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:01 PM PDT 24
Peak memory 194688 kb
Host smart-caccaf25-0d9a-455f-bf28-94bacfaf4ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013718651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2013718651
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.599717553
Short name T620
Test name
Test status
Simulation time 1123819962 ps
CPU time 13.59 seconds
Started Jul 03 04:26:02 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 196052 kb
Host smart-0f431659-feca-4c94-9f43-2bc5c42c160e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599717553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.599717553
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2772617401
Short name T219
Test name
Test status
Simulation time 31100828 ps
CPU time 0.63 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 195068 kb
Host smart-51989561-b26d-4487-9444-cf497093b6b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772617401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2772617401
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4194218513
Short name T415
Test name
Test status
Simulation time 37486270 ps
CPU time 0.96 seconds
Started Jul 03 04:26:05 PM PDT 24
Finished Jul 03 04:26:07 PM PDT 24
Peak memory 196340 kb
Host smart-2b8c40db-e246-4ba0-a423-3e7082736490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194218513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4194218513
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1761253407
Short name T408
Test name
Test status
Simulation time 129548570 ps
CPU time 1.52 seconds
Started Jul 03 04:26:20 PM PDT 24
Finished Jul 03 04:26:23 PM PDT 24
Peak memory 197124 kb
Host smart-07235d4e-8045-4ac0-a4f3-cff86d8d2fba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761253407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1761253407
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2186644105
Short name T57
Test name
Test status
Simulation time 111454243 ps
CPU time 3.21 seconds
Started Jul 03 04:25:56 PM PDT 24
Finished Jul 03 04:26:00 PM PDT 24
Peak memory 197780 kb
Host smart-35aeb202-14d7-4d55-9fef-a748b34094f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186644105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2186644105
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.187248855
Short name T101
Test name
Test status
Simulation time 85883646 ps
CPU time 0.72 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 196024 kb
Host smart-a140b404-5e1a-41c4-a49b-461c2dd23ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187248855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.187248855
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3581419662
Short name T144
Test name
Test status
Simulation time 592730458 ps
CPU time 0.89 seconds
Started Jul 03 04:26:05 PM PDT 24
Finished Jul 03 04:26:07 PM PDT 24
Peak memory 196560 kb
Host smart-c448e15c-43d4-430c-9c99-462c6a10c75b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581419662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3581419662
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2422343658
Short name T193
Test name
Test status
Simulation time 33704026 ps
CPU time 1.35 seconds
Started Jul 03 04:26:05 PM PDT 24
Finished Jul 03 04:26:07 PM PDT 24
Peak memory 198608 kb
Host smart-d2baadee-d5a1-4bcf-96bc-7dbc6c8aa417
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422343658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2422343658
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1842168292
Short name T692
Test name
Test status
Simulation time 665508818 ps
CPU time 1.07 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 196800 kb
Host smart-668631e8-c6d8-4b21-a20a-ff61e849ffef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842168292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1842168292
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1919171749
Short name T659
Test name
Test status
Simulation time 160361254 ps
CPU time 1.16 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 198540 kb
Host smart-be168acc-5fcc-4051-837c-0a1df137e2b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919171749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1919171749
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3589307697
Short name T475
Test name
Test status
Simulation time 24638980953 ps
CPU time 91.7 seconds
Started Jul 03 04:26:01 PM PDT 24
Finished Jul 03 04:27:34 PM PDT 24
Peak memory 198652 kb
Host smart-bbfa9019-8339-492e-9173-79ce5fba13fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589307697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3589307697
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.736033740
Short name T456
Test name
Test status
Simulation time 78933960072 ps
CPU time 1596.17 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:52:50 PM PDT 24
Peak memory 198924 kb
Host smart-0f1637c9-cb6d-4339-b50b-a988d6b221b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=736033740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.736033740
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.515050817
Short name T545
Test name
Test status
Simulation time 32049948 ps
CPU time 0.56 seconds
Started Jul 03 04:26:07 PM PDT 24
Finished Jul 03 04:26:08 PM PDT 24
Peak memory 194620 kb
Host smart-ec47d1fb-fc0f-44ee-a35c-f3729386296e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515050817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.515050817
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1523770
Short name T461
Test name
Test status
Simulation time 120496552 ps
CPU time 0.77 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 195812 kb
Host smart-d05784ae-5c47-46f2-9aa5-15c48fb527f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1523770
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.680209933
Short name T232
Test name
Test status
Simulation time 324711862 ps
CPU time 3.72 seconds
Started Jul 03 04:25:59 PM PDT 24
Finished Jul 03 04:26:04 PM PDT 24
Peak memory 196516 kb
Host smart-d2930429-8ec7-44ef-9137-33caa1430a0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680209933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.680209933
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4142476028
Short name T8
Test name
Test status
Simulation time 36914611 ps
CPU time 0.59 seconds
Started Jul 03 04:26:09 PM PDT 24
Finished Jul 03 04:26:10 PM PDT 24
Peak memory 195044 kb
Host smart-d6546f32-5da0-44ae-ae4a-8040a82bdcf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142476028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4142476028
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3028527892
Short name T246
Test name
Test status
Simulation time 25206637 ps
CPU time 0.8 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 196888 kb
Host smart-51bb7d69-ea46-422b-9750-fef6e4380e11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028527892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3028527892
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.4125489274
Short name T160
Test name
Test status
Simulation time 39588641 ps
CPU time 1.58 seconds
Started Jul 03 04:26:06 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 198668 kb
Host smart-b6044fba-995c-43c5-8250-3597a6f72672
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125489274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.4125489274
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3924010201
Short name T256
Test name
Test status
Simulation time 59191152 ps
CPU time 1.93 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 197852 kb
Host smart-7fe00eaa-bc51-4804-b33a-1d31410e6a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924010201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3924010201
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1703682167
Short name T255
Test name
Test status
Simulation time 118980146 ps
CPU time 1.18 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 197664 kb
Host smart-6a6e5424-5e26-449e-bd08-d7eeccd5311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703682167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1703682167
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1579993316
Short name T143
Test name
Test status
Simulation time 110210678 ps
CPU time 1.11 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 196488 kb
Host smart-019ed841-763b-4bc2-aba3-becb40516e91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579993316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1579993316
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.835565976
Short name T22
Test name
Test status
Simulation time 1863045115 ps
CPU time 4.63 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 198608 kb
Host smart-964fbe72-ae29-4baa-a7d5-a14e910ef460
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835565976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.835565976
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3020515676
Short name T176
Test name
Test status
Simulation time 33394003 ps
CPU time 0.8 seconds
Started Jul 03 04:25:59 PM PDT 24
Finished Jul 03 04:26:01 PM PDT 24
Peak memory 195648 kb
Host smart-079966c2-2128-4ee5-bb15-dd89d4eb6c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020515676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3020515676
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1797710522
Short name T534
Test name
Test status
Simulation time 327879829 ps
CPU time 1.25 seconds
Started Jul 03 04:26:06 PM PDT 24
Finished Jul 03 04:26:08 PM PDT 24
Peak memory 196956 kb
Host smart-e96922df-bafe-4d5e-a830-12fb7d18a985
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797710522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1797710522
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2548370169
Short name T689
Test name
Test status
Simulation time 3034543354 ps
CPU time 35.12 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:50 PM PDT 24
Peak memory 198752 kb
Host smart-5eeb03a5-e188-43a7-a6c6-8d28e829f2c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548370169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2548370169
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1955618950
Short name T690
Test name
Test status
Simulation time 38470188 ps
CPU time 0.54 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 194736 kb
Host smart-af2dc069-0443-4764-a9b5-9c3a332bd207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955618950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1955618950
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.312663327
Short name T700
Test name
Test status
Simulation time 23311807 ps
CPU time 0.71 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 195696 kb
Host smart-1fe145ca-d22c-4b3b-9074-9e5317bb1a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312663327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.312663327
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2866681372
Short name T97
Test name
Test status
Simulation time 499373283 ps
CPU time 7.5 seconds
Started Jul 03 04:26:06 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 197568 kb
Host smart-601d28a2-39e9-43ac-98af-0c106a9bf5d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866681372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2866681372
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1272636164
Short name T220
Test name
Test status
Simulation time 56136109 ps
CPU time 0.92 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 196912 kb
Host smart-dda8b136-f6b9-4b49-b79c-c5a5a396c3b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272636164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1272636164
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1030217388
Short name T592
Test name
Test status
Simulation time 93292112 ps
CPU time 0.77 seconds
Started Jul 03 04:26:23 PM PDT 24
Finished Jul 03 04:26:24 PM PDT 24
Peak memory 196904 kb
Host smart-6e64eda5-0a22-4cb6-b79c-02dab7e35fa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030217388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1030217388
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.364178802
Short name T266
Test name
Test status
Simulation time 59205213 ps
CPU time 2.3 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 198476 kb
Host smart-10466c51-5c1f-467c-9383-3458ae927362
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364178802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.364178802
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.515110642
Short name T439
Test name
Test status
Simulation time 194235647 ps
CPU time 2.71 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 197368 kb
Host smart-070b4334-46c7-40bf-bf15-32f2e000a1e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515110642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
515110642
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1685366225
Short name T79
Test name
Test status
Simulation time 48534929 ps
CPU time 0.75 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:17 PM PDT 24
Peak memory 196684 kb
Host smart-692f1015-4ee8-481a-9685-818ad9723321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685366225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1685366225
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.841508297
Short name T321
Test name
Test status
Simulation time 29316843 ps
CPU time 0.82 seconds
Started Jul 03 04:26:08 PM PDT 24
Finished Jul 03 04:26:09 PM PDT 24
Peak memory 197088 kb
Host smart-cb8f09d1-7149-4845-b259-447bc5deed81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841508297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.841508297
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3394834822
Short name T699
Test name
Test status
Simulation time 46850215 ps
CPU time 2.07 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 198392 kb
Host smart-478e8a2f-fb5d-4419-91c5-9e395ed86445
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394834822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3394834822
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4181963816
Short name T454
Test name
Test status
Simulation time 100797012 ps
CPU time 0.89 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 196920 kb
Host smart-40dff921-255b-4bf6-a67c-048a3f71baff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181963816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4181963816
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.4171442255
Short name T239
Test name
Test status
Simulation time 790786158 ps
CPU time 1.38 seconds
Started Jul 03 04:26:10 PM PDT 24
Finished Jul 03 04:26:12 PM PDT 24
Peak memory 197376 kb
Host smart-6cdcaf17-0653-4e0e-b907-3cb34e83de1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171442255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.4171442255
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.4232151709
Short name T691
Test name
Test status
Simulation time 67665627628 ps
CPU time 142.62 seconds
Started Jul 03 04:26:09 PM PDT 24
Finished Jul 03 04:28:32 PM PDT 24
Peak memory 198536 kb
Host smart-3c6848d6-adb0-453b-97f8-0d027055dfa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232151709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.4232151709
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2696730695
Short name T47
Test name
Test status
Simulation time 47548881 ps
CPU time 0.56 seconds
Started Jul 03 04:26:09 PM PDT 24
Finished Jul 03 04:26:09 PM PDT 24
Peak memory 195508 kb
Host smart-d6a5e18d-8a10-4bf0-bfce-fa38d7587f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696730695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2696730695
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1966862279
Short name T617
Test name
Test status
Simulation time 62170447 ps
CPU time 0.67 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 194860 kb
Host smart-07e85c63-0779-4968-9fee-d129b1af4cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966862279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1966862279
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1031027203
Short name T652
Test name
Test status
Simulation time 1860208212 ps
CPU time 15.58 seconds
Started Jul 03 04:26:10 PM PDT 24
Finished Jul 03 04:26:26 PM PDT 24
Peak memory 197436 kb
Host smart-0a54a326-48f4-4fe2-b9f1-4cd093c83070
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031027203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1031027203
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.443977417
Short name T263
Test name
Test status
Simulation time 26643948 ps
CPU time 0.73 seconds
Started Jul 03 04:26:21 PM PDT 24
Finished Jul 03 04:26:23 PM PDT 24
Peak memory 196036 kb
Host smart-35f648c3-7784-4a6d-92c5-67b2dd8ec217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443977417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.443977417
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3885657758
Short name T558
Test name
Test status
Simulation time 153902474 ps
CPU time 1.06 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 196788 kb
Host smart-3cd26777-e2bb-483c-9cee-24e0508311a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885657758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3885657758
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.119057502
Short name T421
Test name
Test status
Simulation time 34276764 ps
CPU time 1.37 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 198692 kb
Host smart-17cb7a89-6d6a-40ff-b6b4-ac5ee11d356e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119057502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.119057502
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3416079840
Short name T251
Test name
Test status
Simulation time 755950539 ps
CPU time 3.13 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 198668 kb
Host smart-dcff1727-1902-40a1-ae1f-505273ebd5bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416079840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3416079840
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1658273772
Short name T354
Test name
Test status
Simulation time 19778515 ps
CPU time 0.64 seconds
Started Jul 03 04:26:22 PM PDT 24
Finished Jul 03 04:26:23 PM PDT 24
Peak memory 195536 kb
Host smart-c86cfee2-2f1b-4d34-944a-b91380aec65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658273772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1658273772
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.989966590
Short name T579
Test name
Test status
Simulation time 34331001 ps
CPU time 1.11 seconds
Started Jul 03 04:26:06 PM PDT 24
Finished Jul 03 04:26:07 PM PDT 24
Peak memory 197516 kb
Host smart-b86e5bd7-85d9-441d-b184-0d2eb73675f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989966590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.989966590
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1929505537
Short name T335
Test name
Test status
Simulation time 157080947 ps
CPU time 1.28 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 198608 kb
Host smart-23365024-0c51-484e-9099-63695ee3b6d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929505537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1929505537
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1872255829
Short name T197
Test name
Test status
Simulation time 46483540 ps
CPU time 0.92 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 196220 kb
Host smart-ffe543f0-0f27-40d4-b403-9097cbed8b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872255829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1872255829
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1031935066
Short name T27
Test name
Test status
Simulation time 59431632 ps
CPU time 1.15 seconds
Started Jul 03 04:26:07 PM PDT 24
Finished Jul 03 04:26:08 PM PDT 24
Peak memory 197080 kb
Host smart-a4725711-ff0e-4a1d-b9c2-358c423934c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031935066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1031935066
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3621162147
Short name T389
Test name
Test status
Simulation time 52005667458 ps
CPU time 175.59 seconds
Started Jul 03 04:26:20 PM PDT 24
Finished Jul 03 04:29:17 PM PDT 24
Peak memory 198740 kb
Host smart-29469ced-2e11-498c-82c7-95e419adb285
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621162147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3621162147
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2925942039
Short name T261
Test name
Test status
Simulation time 369282890378 ps
CPU time 1856.58 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:57:13 PM PDT 24
Peak memory 198916 kb
Host smart-9b7daba4-3234-481d-bb98-8126a4a478a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2925942039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2925942039
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.982422593
Short name T46
Test name
Test status
Simulation time 15274766 ps
CPU time 0.55 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 194568 kb
Host smart-0d521257-8ba1-4e8a-ae0f-8abb3a5d3daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982422593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.982422593
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.979121362
Short name T449
Test name
Test status
Simulation time 16442743 ps
CPU time 0.61 seconds
Started Jul 03 04:26:25 PM PDT 24
Finished Jul 03 04:26:26 PM PDT 24
Peak memory 195196 kb
Host smart-1f354b48-4324-4a94-80bc-d3390303067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979121362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.979121362
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.49089779
Short name T300
Test name
Test status
Simulation time 177086737 ps
CPU time 8.62 seconds
Started Jul 03 04:26:10 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 197468 kb
Host smart-c930def0-9c49-4150-968f-ad12c6b66ea0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49089779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress
.49089779
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1915222684
Short name T395
Test name
Test status
Simulation time 241688013 ps
CPU time 0.95 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 198436 kb
Host smart-60259e6e-f60a-414a-b291-72a6faab4a0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915222684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1915222684
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.4079888858
Short name T430
Test name
Test status
Simulation time 45083334 ps
CPU time 0.81 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 197276 kb
Host smart-7d67066b-c7cf-4bb8-b902-84a0744e861b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079888858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.4079888858
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1886316938
Short name T190
Test name
Test status
Simulation time 125946898 ps
CPU time 1.49 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 198708 kb
Host smart-8e7f3c50-20db-4f52-961b-323c7d6e6750
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886316938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1886316938
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1576107188
Short name T396
Test name
Test status
Simulation time 124410758 ps
CPU time 2.81 seconds
Started Jul 03 04:26:09 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 197596 kb
Host smart-3fad93a8-7321-4a6b-967d-a01952991b5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576107188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1576107188
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.4107549674
Short name T205
Test name
Test status
Simulation time 17987599 ps
CPU time 0.79 seconds
Started Jul 03 04:26:04 PM PDT 24
Finished Jul 03 04:26:05 PM PDT 24
Peak memory 196936 kb
Host smart-9fdd301b-a064-4940-a555-127b844fd07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107549674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.4107549674
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2745909264
Short name T399
Test name
Test status
Simulation time 104905581 ps
CPU time 1.05 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 196472 kb
Host smart-4e3b1eda-daa8-41ce-a0b1-94d1f084dcc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745909264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2745909264
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1936673445
Short name T516
Test name
Test status
Simulation time 504834917 ps
CPU time 5.08 seconds
Started Jul 03 04:26:25 PM PDT 24
Finished Jul 03 04:26:30 PM PDT 24
Peak memory 197692 kb
Host smart-33f5ebfd-8512-4651-8616-6803d232b0a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936673445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1936673445
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2343616602
Short name T71
Test name
Test status
Simulation time 184874683 ps
CPU time 0.96 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:17 PM PDT 24
Peak memory 196248 kb
Host smart-c673ebf9-7b30-4a62-b714-2fd9127ac3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343616602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2343616602
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1659391391
Short name T343
Test name
Test status
Simulation time 98389827 ps
CPU time 1.38 seconds
Started Jul 03 04:26:09 PM PDT 24
Finished Jul 03 04:26:11 PM PDT 24
Peak memory 196192 kb
Host smart-e86f84cf-a995-4e8e-9ec2-cbd0d17f84fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659391391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1659391391
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.4133474268
Short name T401
Test name
Test status
Simulation time 16952295821 ps
CPU time 48.56 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 198724 kb
Host smart-04de7aee-ba50-4b77-8e12-aaaf4b01a5e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133474268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4133474268
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3426891828
Short name T667
Test name
Test status
Simulation time 43642790 ps
CPU time 0.55 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 194824 kb
Host smart-e1c0fdc5-6364-4fe3-b578-0582c5bda9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426891828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3426891828
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2051074594
Short name T330
Test name
Test status
Simulation time 64896227 ps
CPU time 0.85 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 195836 kb
Host smart-efa97bb8-1c30-4624-bf41-62c19c9b20a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051074594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2051074594
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.839655115
Short name T423
Test name
Test status
Simulation time 2953068198 ps
CPU time 11.08 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 197492 kb
Host smart-17398891-e254-4d41-a1ba-a620b8100d78
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839655115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.839655115
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3770521258
Short name T478
Test name
Test status
Simulation time 64169412 ps
CPU time 0.71 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:13 PM PDT 24
Peak memory 197080 kb
Host smart-df079a43-81d7-427a-95a4-0166643a37b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770521258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3770521258
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1850063395
Short name T367
Test name
Test status
Simulation time 43414105 ps
CPU time 0.79 seconds
Started Jul 03 04:26:46 PM PDT 24
Finished Jul 03 04:26:47 PM PDT 24
Peak memory 196204 kb
Host smart-3a27cf9b-250f-4ef3-a7fa-9c7940aa302e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850063395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1850063395
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.791073969
Short name T243
Test name
Test status
Simulation time 254648594 ps
CPU time 2.54 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 197772 kb
Host smart-305cdab5-4fdb-4c80-8f28-62a54397a2a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791073969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.791073969
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1126636026
Short name T100
Test name
Test status
Simulation time 1386671904 ps
CPU time 2.2 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 197116 kb
Host smart-e209ae7b-9746-46cf-9f78-01ee6431c464
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126636026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1126636026
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3757203817
Short name T585
Test name
Test status
Simulation time 63217634 ps
CPU time 1.3 seconds
Started Jul 03 04:26:23 PM PDT 24
Finished Jul 03 04:26:25 PM PDT 24
Peak memory 198592 kb
Host smart-d6b59030-3deb-4a31-bdc6-8b828aeccebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757203817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3757203817
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.889176626
Short name T631
Test name
Test status
Simulation time 15909793 ps
CPU time 0.65 seconds
Started Jul 03 04:26:33 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 194756 kb
Host smart-715ee76a-50b1-455b-93eb-7e2a4ab29e89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889176626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.889176626
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.449207962
Short name T639
Test name
Test status
Simulation time 44528108 ps
CPU time 1.78 seconds
Started Jul 03 04:26:34 PM PDT 24
Finished Jul 03 04:26:37 PM PDT 24
Peak memory 198616 kb
Host smart-831319f8-27b5-41f3-9b2b-8c9ba32befa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449207962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.449207962
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.429538631
Short name T86
Test name
Test status
Simulation time 38765943 ps
CPU time 0.91 seconds
Started Jul 03 04:26:27 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 196456 kb
Host smart-242e16d4-f80c-42ad-b941-5a2c111bb20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429538631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.429538631
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.929842134
Short name T633
Test name
Test status
Simulation time 136962883 ps
CPU time 1.11 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 197048 kb
Host smart-ee0e553e-9700-413b-ab9b-15dc356d5cd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929842134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.929842134
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2564254763
Short name T20
Test name
Test status
Simulation time 19115388361 ps
CPU time 193.81 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:29:27 PM PDT 24
Peak memory 198648 kb
Host smart-4eee1257-b273-455a-b7b8-bdc1c619cf0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564254763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2564254763
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3230351240
Short name T69
Test name
Test status
Simulation time 45152651424 ps
CPU time 483.09 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:34:32 PM PDT 24
Peak memory 198808 kb
Host smart-5b9dfc46-9b5e-406b-9963-4b464e886eea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3230351240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3230351240
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2793381461
Short name T30
Test name
Test status
Simulation time 13911486 ps
CPU time 0.59 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 194656 kb
Host smart-025951dc-2495-4b2a-aba3-bf6638f2276e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793381461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2793381461
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4162881541
Short name T292
Test name
Test status
Simulation time 36927324 ps
CPU time 0.82 seconds
Started Jul 03 04:26:20 PM PDT 24
Finished Jul 03 04:26:22 PM PDT 24
Peak memory 196968 kb
Host smart-6bf308f8-2a4c-40ea-a6b0-715f58910816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162881541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4162881541
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2197046912
Short name T444
Test name
Test status
Simulation time 3033496227 ps
CPU time 23.73 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:39 PM PDT 24
Peak memory 198644 kb
Host smart-05e93322-7d29-4d87-8c55-1004f0e1d3c4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197046912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2197046912
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.844830733
Short name T260
Test name
Test status
Simulation time 155943767 ps
CPU time 0.75 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 196488 kb
Host smart-2a311a37-d8ba-467e-987c-1112f9ead2dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844830733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.844830733
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3762138844
Short name T676
Test name
Test status
Simulation time 160251082 ps
CPU time 1.05 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 196416 kb
Host smart-ce2500fc-c6de-4d30-a8f9-221cd351e222
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762138844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3762138844
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1612933547
Short name T269
Test name
Test status
Simulation time 84914796 ps
CPU time 1.65 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 197820 kb
Host smart-8e0a66c2-9778-45d1-8dd6-be2b5f24e653
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612933547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1612933547
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1286070932
Short name T419
Test name
Test status
Simulation time 51752052 ps
CPU time 1.49 seconds
Started Jul 03 04:26:27 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 197364 kb
Host smart-1f38ad5f-8d84-499c-920b-ca05ae27ef34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286070932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1286070932
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.764960239
Short name T464
Test name
Test status
Simulation time 31659275 ps
CPU time 0.83 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:12 PM PDT 24
Peak memory 196676 kb
Host smart-a645c8ae-14a6-4dd2-9797-ee220052fc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764960239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.764960239
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.84391725
Short name T210
Test name
Test status
Simulation time 36839991 ps
CPU time 0.81 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 196144 kb
Host smart-b52fe4ab-8cd7-415a-a363-8757f890d4c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84391725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup_
pulldown.84391725
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2363709334
Short name T433
Test name
Test status
Simulation time 74422901 ps
CPU time 2.92 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 198368 kb
Host smart-7867062c-2f19-45f1-a594-4e5f6561bb2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363709334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2363709334
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.946979857
Short name T128
Test name
Test status
Simulation time 67831588 ps
CPU time 1.18 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 196416 kb
Host smart-bda06bba-e9a2-4880-9be5-8f4ea150180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946979857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.946979857
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3761406890
Short name T547
Test name
Test status
Simulation time 124381660 ps
CPU time 0.77 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:17 PM PDT 24
Peak memory 195760 kb
Host smart-dc62f5bd-db4b-46cf-b6d2-ae8869d2f1be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761406890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3761406890
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3290827006
Short name T386
Test name
Test status
Simulation time 12493836698 ps
CPU time 69.72 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:28:00 PM PDT 24
Peak memory 198748 kb
Host smart-bf87d928-f05e-4aa7-96d0-641f55e881a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290827006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3290827006
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.4219515143
Short name T711
Test name
Test status
Simulation time 39414414 ps
CPU time 0.55 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 195184 kb
Host smart-29895862-7d52-4385-8e04-86ad8aa829c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219515143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.4219515143
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.4064275050
Short name T339
Test name
Test status
Simulation time 76591486 ps
CPU time 0.69 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:25:25 PM PDT 24
Peak memory 195452 kb
Host smart-0d2ada5b-a084-4315-a8e3-5b9cfd6f4e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064275050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.4064275050
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.672993470
Short name T569
Test name
Test status
Simulation time 3821875125 ps
CPU time 22.41 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:25:45 PM PDT 24
Peak memory 197460 kb
Host smart-3d742733-771a-4229-ab25-e62812e91c44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672993470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.672993470
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.733278871
Short name T570
Test name
Test status
Simulation time 53384611 ps
CPU time 0.82 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 198232 kb
Host smart-f2c3896e-eaeb-4ea6-8a8d-903fa3bd4391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733278871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.733278871
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2712856704
Short name T142
Test name
Test status
Simulation time 71214562 ps
CPU time 1.1 seconds
Started Jul 03 04:25:35 PM PDT 24
Finished Jul 03 04:25:37 PM PDT 24
Peak memory 196748 kb
Host smart-ae6d5fe2-ed56-42fa-ba47-51ec442a57e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712856704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2712856704
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.4137502462
Short name T506
Test name
Test status
Simulation time 200504418 ps
CPU time 2.81 seconds
Started Jul 03 04:25:38 PM PDT 24
Finished Jul 03 04:25:41 PM PDT 24
Peak memory 198548 kb
Host smart-f2832a14-08f9-48ed-a626-5d4f6f02a957
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137502462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
4137502462
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1957359769
Short name T152
Test name
Test status
Simulation time 39743749 ps
CPU time 0.6 seconds
Started Jul 03 04:25:27 PM PDT 24
Finished Jul 03 04:25:38 PM PDT 24
Peak memory 194732 kb
Host smart-f2334b66-328a-4846-b216-ca8264779ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957359769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1957359769
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3900169043
Short name T302
Test name
Test status
Simulation time 26398977 ps
CPU time 0.93 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 196456 kb
Host smart-f6cf9174-4af9-4a93-9176-7addeaba25c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900169043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3900169043
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3016310082
Short name T550
Test name
Test status
Simulation time 110135448 ps
CPU time 1.43 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 198576 kb
Host smart-5635cb80-00a2-459e-826c-8852809e62d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016310082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3016310082
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3323940701
Short name T43
Test name
Test status
Simulation time 83977684 ps
CPU time 0.92 seconds
Started Jul 03 04:25:35 PM PDT 24
Finished Jul 03 04:25:36 PM PDT 24
Peak memory 215176 kb
Host smart-f0ec8030-140d-4a18-95e0-dea6dd9b61a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323940701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3323940701
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.660948909
Short name T705
Test name
Test status
Simulation time 49852329 ps
CPU time 0.63 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 194720 kb
Host smart-956c568e-f066-476a-aecd-b21201cae121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660948909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.660948909
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3952952758
Short name T458
Test name
Test status
Simulation time 37282628 ps
CPU time 1.05 seconds
Started Jul 03 04:25:30 PM PDT 24
Finished Jul 03 04:25:32 PM PDT 24
Peak memory 196456 kb
Host smart-6fa91186-156a-4a6d-83dc-95d259d0fc36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952952758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3952952758
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.602065076
Short name T188
Test name
Test status
Simulation time 9180131237 ps
CPU time 108.91 seconds
Started Jul 03 04:25:44 PM PDT 24
Finished Jul 03 04:27:34 PM PDT 24
Peak memory 198684 kb
Host smart-a900bf4c-cdd0-4699-8c6b-8dd43f57eaba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602065076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.602065076
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.993736088
Short name T582
Test name
Test status
Simulation time 21659920819 ps
CPU time 87.89 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 198816 kb
Host smart-981affdd-9c84-4c5d-9fe6-0e3771589745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=993736088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.993736088
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3396027848
Short name T562
Test name
Test status
Simulation time 15902770 ps
CPU time 0.54 seconds
Started Jul 03 04:26:31 PM PDT 24
Finished Jul 03 04:26:32 PM PDT 24
Peak memory 194588 kb
Host smart-676de15f-b413-4741-8a36-d6af5b7428a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396027848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3396027848
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.215829520
Short name T573
Test name
Test status
Simulation time 56629919 ps
CPU time 0.81 seconds
Started Jul 03 04:26:42 PM PDT 24
Finished Jul 03 04:26:43 PM PDT 24
Peak memory 197124 kb
Host smart-fc89a0b6-eeb1-4be2-ad3c-5932ff758159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215829520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.215829520
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.71824634
Short name T632
Test name
Test status
Simulation time 1249252439 ps
CPU time 19.48 seconds
Started Jul 03 04:26:52 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 197376 kb
Host smart-19639701-7778-4f8b-b6e0-0600995a2a0e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71824634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stress
.71824634
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3811610224
Short name T643
Test name
Test status
Simulation time 670264108 ps
CPU time 0.95 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 198364 kb
Host smart-83ea03b8-c012-40bd-bc08-24dac3817973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811610224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3811610224
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3443635291
Short name T235
Test name
Test status
Simulation time 169020429 ps
CPU time 1.29 seconds
Started Jul 03 04:26:32 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 197196 kb
Host smart-bb1a0ba9-f754-4c0e-80a3-89c6bdd30658
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443635291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3443635291
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3943682814
Short name T326
Test name
Test status
Simulation time 66614586 ps
CPU time 2.54 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:14 PM PDT 24
Peak memory 198632 kb
Host smart-02a05c5f-5d3f-43ee-b6a7-8a0eab81f554
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943682814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3943682814
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.372962228
Short name T283
Test name
Test status
Simulation time 1340074928 ps
CPU time 2.6 seconds
Started Jul 03 04:26:19 PM PDT 24
Finished Jul 03 04:26:23 PM PDT 24
Peak memory 198576 kb
Host smart-f53c8dbe-9558-4e56-b142-24bac3d38d2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372962228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
372962228
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3602243859
Short name T272
Test name
Test status
Simulation time 59396532 ps
CPU time 1.21 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 197596 kb
Host smart-945ed4ee-1b4d-4a5d-8217-811851d898e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602243859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3602243859
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3801551580
Short name T653
Test name
Test status
Simulation time 57366247 ps
CPU time 1.23 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 197468 kb
Host smart-e5712c83-73d3-48b9-bc2a-e5de5e11e5c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801551580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3801551580
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1837234551
Short name T362
Test name
Test status
Simulation time 1297955337 ps
CPU time 5.64 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:26:47 PM PDT 24
Peak memory 198508 kb
Host smart-884d9486-1aff-44ef-9ff1-9fc3053be5ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837234551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1837234551
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3692575788
Short name T678
Test name
Test status
Simulation time 1324497575 ps
CPU time 1.22 seconds
Started Jul 03 04:26:26 PM PDT 24
Finished Jul 03 04:26:28 PM PDT 24
Peak memory 196116 kb
Host smart-c96c37e7-1505-4447-94b2-1203c9b8ec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692575788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3692575788
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2305770053
Short name T344
Test name
Test status
Simulation time 43556397 ps
CPU time 1.06 seconds
Started Jul 03 04:26:07 PM PDT 24
Finished Jul 03 04:26:08 PM PDT 24
Peak memory 196256 kb
Host smart-240f7ede-e2bb-45ca-b14b-01eafb0aa8af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305770053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2305770053
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.4041630349
Short name T14
Test name
Test status
Simulation time 89958924863 ps
CPU time 118.76 seconds
Started Jul 03 04:26:06 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 198712 kb
Host smart-de9131c0-84e1-4f0d-947f-77f8e20a29b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041630349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.4041630349
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.651484966
Short name T670
Test name
Test status
Simulation time 18870003 ps
CPU time 0.56 seconds
Started Jul 03 04:26:44 PM PDT 24
Finished Jul 03 04:26:46 PM PDT 24
Peak memory 194652 kb
Host smart-6d2f9c1d-5c61-4a85-a58b-d7456961a4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651484966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.651484966
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3086980268
Short name T663
Test name
Test status
Simulation time 13077484 ps
CPU time 0.58 seconds
Started Jul 03 04:26:47 PM PDT 24
Finished Jul 03 04:26:48 PM PDT 24
Peak memory 194556 kb
Host smart-3a35b0d8-c840-4b7d-826e-d9b05d95aa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086980268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3086980268
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1425012226
Short name T199
Test name
Test status
Simulation time 706327951 ps
CPU time 20.14 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:27:02 PM PDT 24
Peak memory 198620 kb
Host smart-ede362e9-2fcf-4ec5-b410-b4c964a1dff2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425012226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1425012226
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.4034086549
Short name T217
Test name
Test status
Simulation time 170473098 ps
CPU time 0.82 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:26:42 PM PDT 24
Peak memory 196656 kb
Host smart-0809e741-df9f-43a7-9132-a3544942c161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034086549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.4034086549
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3736731350
Short name T33
Test name
Test status
Simulation time 621704712 ps
CPU time 0.99 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 196684 kb
Host smart-e9b93936-56f7-45ca-91fe-69b8f699d499
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736731350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3736731350
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1330166338
Short name T80
Test name
Test status
Simulation time 267340734 ps
CPU time 2.44 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:22 PM PDT 24
Peak memory 198596 kb
Host smart-617daf29-d769-4bf1-97bb-4661b637c247
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330166338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1330166338
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3468193551
Short name T555
Test name
Test status
Simulation time 54123887 ps
CPU time 1.33 seconds
Started Jul 03 04:27:11 PM PDT 24
Finished Jul 03 04:27:15 PM PDT 24
Peak memory 197744 kb
Host smart-c8e20461-16fd-4554-93df-71d75d76c559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468193551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3468193551
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1502899215
Short name T231
Test name
Test status
Simulation time 36662318 ps
CPU time 0.8 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 197856 kb
Host smart-7fac5ee5-72e8-4908-9121-037589bc5b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502899215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1502899215
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3060264481
Short name T657
Test name
Test status
Simulation time 159542658 ps
CPU time 0.65 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 194844 kb
Host smart-c4c55b74-dbb5-412c-9092-72096a868fee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060264481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3060264481
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3501855467
Short name T436
Test name
Test status
Simulation time 1191038847 ps
CPU time 4.75 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:24 PM PDT 24
Peak memory 197876 kb
Host smart-7cf3c0ad-926c-47a4-8159-509b1b26c406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501855467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3501855467
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.160188190
Short name T394
Test name
Test status
Simulation time 277230235 ps
CPU time 1.23 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:26:43 PM PDT 24
Peak memory 198628 kb
Host smart-9d5bc3f0-4ea8-4e52-972d-4271e7c75285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160188190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.160188190
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2947544537
Short name T597
Test name
Test status
Simulation time 87754294 ps
CPU time 1.15 seconds
Started Jul 03 04:26:43 PM PDT 24
Finished Jul 03 04:26:44 PM PDT 24
Peak memory 196912 kb
Host smart-314ce5b8-2ce0-4b0a-82ca-49758525f800
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947544537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2947544537
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2197835399
Short name T578
Test name
Test status
Simulation time 24983211612 ps
CPU time 56.87 seconds
Started Jul 03 04:26:56 PM PDT 24
Finished Jul 03 04:27:53 PM PDT 24
Peak memory 198584 kb
Host smart-9a34187b-238f-4880-aa55-8433ba78b017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197835399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2197835399
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2370382312
Short name T520
Test name
Test status
Simulation time 121028934764 ps
CPU time 480.18 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:34:19 PM PDT 24
Peak memory 198848 kb
Host smart-70f427d7-315f-4756-93b3-18d4996993fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2370382312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2370382312
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.4152272539
Short name T696
Test name
Test status
Simulation time 11930585 ps
CPU time 0.57 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 195324 kb
Host smart-aaa151c2-9c76-47fa-b59d-f0ee55e1c735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152272539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.4152272539
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3583012930
Short name T59
Test name
Test status
Simulation time 149093249 ps
CPU time 0.83 seconds
Started Jul 03 04:27:10 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 195928 kb
Host smart-88948334-d15d-4258-ab58-48557af43190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583012930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3583012930
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2927091896
Short name T31
Test name
Test status
Simulation time 150229041 ps
CPU time 6.9 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:24 PM PDT 24
Peak memory 197640 kb
Host smart-c09888fc-4b95-405b-bc3f-d66d82515c91
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927091896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2927091896
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2748961623
Short name T517
Test name
Test status
Simulation time 57129954 ps
CPU time 0.75 seconds
Started Jul 03 04:26:11 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 196296 kb
Host smart-f446b079-c37e-4e4b-8e72-2606650609fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748961623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2748961623
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2148350815
Short name T412
Test name
Test status
Simulation time 124481603 ps
CPU time 1.43 seconds
Started Jul 03 04:26:57 PM PDT 24
Finished Jul 03 04:26:59 PM PDT 24
Peak memory 197848 kb
Host smart-6372cfd5-da06-4208-835e-cf7d359719ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148350815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2148350815
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2718167636
Short name T134
Test name
Test status
Simulation time 1202386534 ps
CPU time 2.89 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 198644 kb
Host smart-e54ad8b9-83e1-442b-b073-6de67afae8be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718167636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2718167636
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.252106072
Short name T463
Test name
Test status
Simulation time 112542076 ps
CPU time 1.79 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 196812 kb
Host smart-f5dba9eb-6ff2-4858-b47d-edb7152d60d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252106072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
252106072
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2426207761
Short name T432
Test name
Test status
Simulation time 64155424 ps
CPU time 0.83 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 196680 kb
Host smart-a75ff3e9-7751-4900-bb83-c713c97cd7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426207761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2426207761
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2027598652
Short name T105
Test name
Test status
Simulation time 53016509 ps
CPU time 0.81 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 195880 kb
Host smart-eef5d9ed-14f6-4eba-8bbd-c5994fe6dc35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027598652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2027598652
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1462225708
Short name T702
Test name
Test status
Simulation time 102636608 ps
CPU time 4.45 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 198532 kb
Host smart-f5326ff1-e7c8-4f4b-b6ef-08b5c0326578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462225708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1462225708
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3746776184
Short name T598
Test name
Test status
Simulation time 116013876 ps
CPU time 1.17 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 197260 kb
Host smart-260e7e2d-43e1-4133-b2aa-4862ef7c8636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746776184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3746776184
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.428252734
Short name T157
Test name
Test status
Simulation time 144883218 ps
CPU time 0.94 seconds
Started Jul 03 04:26:48 PM PDT 24
Finished Jul 03 04:26:49 PM PDT 24
Peak memory 197856 kb
Host smart-4819089c-3ff6-41b2-becc-219be87451f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428252734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.428252734
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2004231467
Short name T98
Test name
Test status
Simulation time 30266359436 ps
CPU time 186.9 seconds
Started Jul 03 04:26:26 PM PDT 24
Finished Jul 03 04:29:33 PM PDT 24
Peak memory 198728 kb
Host smart-f1abdc58-03fe-4063-b165-4ed8e4f8ca3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004231467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2004231467
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1450513615
Short name T601
Test name
Test status
Simulation time 20825594 ps
CPU time 0.54 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 195252 kb
Host smart-44b8fab1-3ec7-4dff-b925-7915e39051e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450513615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1450513615
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.459339265
Short name T320
Test name
Test status
Simulation time 65839718 ps
CPU time 0.7 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 196460 kb
Host smart-4b455ba7-73b2-44b8-8fa9-8078990c9f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459339265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.459339265
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3945360368
Short name T215
Test name
Test status
Simulation time 573027352 ps
CPU time 15.53 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:33 PM PDT 24
Peak memory 197044 kb
Host smart-80bddb8e-6387-4485-be8b-831dc8a338f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945360368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3945360368
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2482260606
Short name T619
Test name
Test status
Simulation time 93712266 ps
CPU time 1.03 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 197108 kb
Host smart-7f879d6a-8a36-4991-b8c8-0f1a3559d9ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482260606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2482260606
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3061700417
Short name T227
Test name
Test status
Simulation time 229674123 ps
CPU time 1.35 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 197620 kb
Host smart-ab9f4eeb-df5b-46a8-83a8-5602ce747dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061700417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3061700417
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2803461362
Short name T584
Test name
Test status
Simulation time 147505437 ps
CPU time 1.57 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 197364 kb
Host smart-610e5fe2-e5b5-4e85-b7bd-e5833e0364bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803461362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2803461362
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2284165015
Short name T15
Test name
Test status
Simulation time 198765721 ps
CPU time 3.22 seconds
Started Jul 03 04:26:27 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 197672 kb
Host smart-9b4345e0-9ef1-4b92-a202-92ef914a696f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284165015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2284165015
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2713044559
Short name T32
Test name
Test status
Simulation time 18557175 ps
CPU time 0.7 seconds
Started Jul 03 04:26:33 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 196056 kb
Host smart-3eb3fab0-1115-465a-a1cd-f3bb0a24b8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713044559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2713044559
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3804953819
Short name T571
Test name
Test status
Simulation time 73526032 ps
CPU time 1.2 seconds
Started Jul 03 04:26:35 PM PDT 24
Finished Jul 03 04:26:37 PM PDT 24
Peak memory 197712 kb
Host smart-7f2136dd-e591-4fa2-8e74-d2110568ed61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804953819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3804953819
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3787099573
Short name T540
Test name
Test status
Simulation time 115919033 ps
CPU time 4.69 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:22 PM PDT 24
Peak memory 198420 kb
Host smart-a73107d5-8fbc-4130-8c33-48a658b0a0bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787099573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3787099573
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3654781924
Short name T481
Test name
Test status
Simulation time 131506869 ps
CPU time 0.85 seconds
Started Jul 03 04:26:29 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 197820 kb
Host smart-4bc3d1bd-5f92-4b5d-b825-77cb3258d728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654781924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3654781924
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2371322668
Short name T124
Test name
Test status
Simulation time 344800855 ps
CPU time 1.34 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 197196 kb
Host smart-b7a91e42-13c2-4789-8cf0-741a79341553
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371322668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2371322668
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.833042805
Short name T349
Test name
Test status
Simulation time 16582349045 ps
CPU time 89.91 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:27:50 PM PDT 24
Peak memory 198740 kb
Host smart-a5107dd4-fdb4-4fc9-8881-09ec13fe9723
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833042805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.833042805
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2487625836
Short name T198
Test name
Test status
Simulation time 19452557 ps
CPU time 0.56 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 194640 kb
Host smart-78d2a9a3-8423-4659-942a-707a221b2725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487625836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2487625836
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3068377697
Short name T674
Test name
Test status
Simulation time 113274039 ps
CPU time 0.85 seconds
Started Jul 03 04:26:29 PM PDT 24
Finished Jul 03 04:26:30 PM PDT 24
Peak memory 196632 kb
Host smart-1ce5a108-1965-43bd-9390-795e6298cd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068377697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3068377697
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2708494245
Short name T153
Test name
Test status
Simulation time 482221957 ps
CPU time 11.7 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 197580 kb
Host smart-81c829e3-f330-4903-9d9b-45321ab292a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708494245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2708494245
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3219825696
Short name T6
Test name
Test status
Simulation time 54606629 ps
CPU time 0.76 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 197228 kb
Host smart-7093d7f2-b96a-4082-915e-528e76899b80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219825696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3219825696
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2706320617
Short name T360
Test name
Test status
Simulation time 204145143 ps
CPU time 1.22 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:26:30 PM PDT 24
Peak memory 198296 kb
Host smart-326aa6a8-da8f-4188-815c-f8855d56f648
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706320617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2706320617
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1003945080
Short name T18
Test name
Test status
Simulation time 185628349 ps
CPU time 3.39 seconds
Started Jul 03 04:26:22 PM PDT 24
Finished Jul 03 04:26:27 PM PDT 24
Peak memory 198544 kb
Host smart-4932aee7-11ca-4a67-a5be-e17452800765
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003945080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1003945080
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.69164073
Short name T284
Test name
Test status
Simulation time 173351357 ps
CPU time 2.5 seconds
Started Jul 03 04:26:26 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 197664 kb
Host smart-e99a7073-81ea-4102-b1f0-c353cc3b2c8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69164073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.69164073
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1993485279
Short name T402
Test name
Test status
Simulation time 136958752 ps
CPU time 1.4 seconds
Started Jul 03 04:26:31 PM PDT 24
Finished Jul 03 04:26:33 PM PDT 24
Peak memory 197628 kb
Host smart-3ed2a357-89f0-4cae-a033-d4ffaede68a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993485279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1993485279
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1455577786
Short name T496
Test name
Test status
Simulation time 546384574 ps
CPU time 1.22 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 197808 kb
Host smart-61a34d71-8b2a-431a-9ede-a5314ff0854b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455577786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1455577786
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1446417696
Short name T568
Test name
Test status
Simulation time 638780699 ps
CPU time 2.9 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:22 PM PDT 24
Peak memory 198452 kb
Host smart-75643945-39bc-45eb-bdcf-581162f886ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446417696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1446417696
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2119238160
Short name T404
Test name
Test status
Simulation time 137328244 ps
CPU time 1 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:23 PM PDT 24
Peak memory 196376 kb
Host smart-ffe267c9-856e-40d1-922a-9b61b8d0b082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119238160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2119238160
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.481179297
Short name T538
Test name
Test status
Simulation time 380105805 ps
CPU time 1.34 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 198940 kb
Host smart-5f356ee4-fd9a-4453-9e67-4e6f2fc57ba2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481179297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.481179297
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2473140479
Short name T4
Test name
Test status
Simulation time 92205285740 ps
CPU time 182.53 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:29:20 PM PDT 24
Peak memory 198708 kb
Host smart-3f7cf1f5-26c8-49de-b1fd-38a3b3bf0f69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473140479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2473140479
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.519828559
Short name T65
Test name
Test status
Simulation time 16058031830 ps
CPU time 316.5 seconds
Started Jul 03 04:26:19 PM PDT 24
Finished Jul 03 04:31:37 PM PDT 24
Peak memory 198888 kb
Host smart-cff6e9f2-c477-4e97-835a-f62b2d6bd1c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=519828559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.519828559
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.357731362
Short name T289
Test name
Test status
Simulation time 25572619 ps
CPU time 0.57 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 194588 kb
Host smart-6fd18e49-2da6-40e9-9dbb-f2fe26f7a1fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357731362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.357731362
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1282120810
Short name T368
Test name
Test status
Simulation time 107310629 ps
CPU time 0.57 seconds
Started Jul 03 04:26:37 PM PDT 24
Finished Jul 03 04:26:38 PM PDT 24
Peak memory 194524 kb
Host smart-0101a280-a026-4b05-a90b-11233f488ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282120810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1282120810
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1461130099
Short name T383
Test name
Test status
Simulation time 3220240690 ps
CPU time 25.59 seconds
Started Jul 03 04:26:35 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 198648 kb
Host smart-95ffd8d1-1a47-4819-bb85-14ef4b21c13c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461130099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1461130099
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2221302844
Short name T163
Test name
Test status
Simulation time 656887120 ps
CPU time 0.9 seconds
Started Jul 03 04:26:12 PM PDT 24
Finished Jul 03 04:26:14 PM PDT 24
Peak memory 197028 kb
Host smart-2365b7cd-fd6a-4f91-99ea-b14741f6f7e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221302844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2221302844
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3889397358
Short name T154
Test name
Test status
Simulation time 47355597 ps
CPU time 0.91 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:26:30 PM PDT 24
Peak memory 197368 kb
Host smart-523a4116-aebe-43ea-9f97-00fb20366cc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889397358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3889397358
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3167742824
Short name T484
Test name
Test status
Simulation time 136938189 ps
CPU time 2.69 seconds
Started Jul 03 04:26:31 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 198700 kb
Host smart-0c547fb8-2ccd-4942-9ac9-3189e2f11a11
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167742824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3167742824
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.516525003
Short name T593
Test name
Test status
Simulation time 63391001 ps
CPU time 1.49 seconds
Started Jul 03 04:26:32 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 196592 kb
Host smart-41911469-1848-45a2-8879-acb230bca8b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516525003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
516525003
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.992253667
Short name T345
Test name
Test status
Simulation time 77010694 ps
CPU time 0.86 seconds
Started Jul 03 04:26:25 PM PDT 24
Finished Jul 03 04:26:26 PM PDT 24
Peak memory 197228 kb
Host smart-206aa4c8-3498-4ad5-9b9e-6e434a4301a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992253667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.992253667
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.462255235
Short name T191
Test name
Test status
Simulation time 17960011 ps
CPU time 0.7 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 194872 kb
Host smart-c9321188-b01f-4dab-b9c8-86a18d7e0f37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462255235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.462255235
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2781590646
Short name T575
Test name
Test status
Simulation time 1078196149 ps
CPU time 5.26 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:23 PM PDT 24
Peak memory 198412 kb
Host smart-32859d01-a6e5-4961-80c9-2a89d8039e46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781590646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2781590646
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2663599078
Short name T352
Test name
Test status
Simulation time 33708643 ps
CPU time 0.85 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:17 PM PDT 24
Peak memory 197024 kb
Host smart-2599d9c8-ada0-452d-895f-7886f4dca695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663599078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2663599078
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2897135225
Short name T82
Test name
Test status
Simulation time 49443429 ps
CPU time 1.22 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 198496 kb
Host smart-17e67c7b-122a-462a-953a-a9e508ed6ece
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897135225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2897135225
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.775544332
Short name T455
Test name
Test status
Simulation time 6635617365 ps
CPU time 86.25 seconds
Started Jul 03 04:26:20 PM PDT 24
Finished Jul 03 04:27:47 PM PDT 24
Peak memory 198728 kb
Host smart-7aafc74b-d130-41c4-a2ea-eb4753807821
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775544332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.775544332
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3825765836
Short name T66
Test name
Test status
Simulation time 322186667182 ps
CPU time 2013.95 seconds
Started Jul 03 04:26:24 PM PDT 24
Finished Jul 03 04:59:58 PM PDT 24
Peak memory 198808 kb
Host smart-7d788daf-6d1b-4a47-aebd-be0c37cb81e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3825765836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3825765836
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.713607076
Short name T625
Test name
Test status
Simulation time 13446775 ps
CPU time 0.56 seconds
Started Jul 03 04:26:30 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 194612 kb
Host smart-69b73529-f10f-4d40-867f-9af474a33a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713607076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.713607076
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2967111546
Short name T234
Test name
Test status
Simulation time 49837777 ps
CPU time 0.78 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 195888 kb
Host smart-ae830266-08a1-401e-8b75-42b85f5e2986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967111546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2967111546
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.435693523
Short name T125
Test name
Test status
Simulation time 1348475623 ps
CPU time 7.16 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:22 PM PDT 24
Peak memory 197292 kb
Host smart-feff519c-725b-4618-9cc1-25f708448de4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435693523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.435693523
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.303290330
Short name T658
Test name
Test status
Simulation time 22329110 ps
CPU time 0.72 seconds
Started Jul 03 04:26:36 PM PDT 24
Finished Jul 03 04:26:37 PM PDT 24
Peak memory 196108 kb
Host smart-bba35a00-9db9-48b8-a25a-ea24a8fee982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303290330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.303290330
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2405683523
Short name T509
Test name
Test status
Simulation time 64845336 ps
CPU time 2 seconds
Started Jul 03 04:26:30 PM PDT 24
Finished Jul 03 04:26:33 PM PDT 24
Peak memory 198632 kb
Host smart-14caefa3-ac04-4030-87a2-43be64ad7763
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405683523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2405683523
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.100008769
Short name T145
Test name
Test status
Simulation time 73574841 ps
CPU time 2.12 seconds
Started Jul 03 04:26:37 PM PDT 24
Finished Jul 03 04:26:40 PM PDT 24
Peak memory 198464 kb
Host smart-d5f27d20-0362-4d74-b543-16f430dbe64b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100008769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
100008769
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.725808867
Short name T280
Test name
Test status
Simulation time 123206568 ps
CPU time 1.08 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 197484 kb
Host smart-da2b94ab-7429-40d6-a289-50e80d9f7315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725808867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.725808867
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3628880884
Short name T501
Test name
Test status
Simulation time 26746628 ps
CPU time 0.93 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:26:30 PM PDT 24
Peak memory 196868 kb
Host smart-6ad4f0e8-a13a-40a4-825a-d71eb1b01a1f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628880884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3628880884
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3379061779
Short name T356
Test name
Test status
Simulation time 369909170 ps
CPU time 5.08 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:22 PM PDT 24
Peak memory 198612 kb
Host smart-f30252f6-fbb4-4de0-9be5-3c630fa6ca76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379061779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3379061779
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2359393285
Short name T287
Test name
Test status
Simulation time 184884437 ps
CPU time 0.99 seconds
Started Jul 03 04:26:24 PM PDT 24
Finished Jul 03 04:26:26 PM PDT 24
Peak memory 196280 kb
Host smart-f3bc9ac3-a85e-4aee-a691-93c5a4c2804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359393285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2359393285
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.659640305
Short name T704
Test name
Test status
Simulation time 165722297 ps
CPU time 1.07 seconds
Started Jul 03 04:26:27 PM PDT 24
Finished Jul 03 04:26:28 PM PDT 24
Peak memory 196120 kb
Host smart-62e7e39a-5bcc-4fc8-b494-bbab22d0b69b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659640305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.659640305
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.202057882
Short name T9
Test name
Test status
Simulation time 19357884067 ps
CPU time 204.6 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:29:40 PM PDT 24
Peak memory 198248 kb
Host smart-6746c18e-9fe8-4e1f-a57c-8f47e8a28ade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202057882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.202057882
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1480902875
Short name T660
Test name
Test status
Simulation time 105980317572 ps
CPU time 2212.82 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 05:03:21 PM PDT 24
Peak memory 198904 kb
Host smart-1d9de69f-7daf-4a51-addd-9ba66c0ff91f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1480902875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1480902875
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2657581023
Short name T324
Test name
Test status
Simulation time 11373555 ps
CPU time 0.57 seconds
Started Jul 03 04:26:48 PM PDT 24
Finished Jul 03 04:26:49 PM PDT 24
Peak memory 195336 kb
Host smart-cd40efed-8ef0-4ad9-9ce3-1ea19933b9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657581023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2657581023
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1107331595
Short name T548
Test name
Test status
Simulation time 59865178 ps
CPU time 0.71 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:17 PM PDT 24
Peak memory 195888 kb
Host smart-b08ec4fe-cfb3-40f6-8201-687d1fd5b97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107331595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1107331595
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2017149885
Short name T716
Test name
Test status
Simulation time 1616646011 ps
CPU time 20.33 seconds
Started Jul 03 04:26:34 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 197400 kb
Host smart-90ae1a8d-ee83-48fd-9fd3-0b54f1b97eb6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017149885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2017149885
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1131762314
Short name T621
Test name
Test status
Simulation time 60108210 ps
CPU time 0.77 seconds
Started Jul 03 04:26:35 PM PDT 24
Finished Jul 03 04:26:37 PM PDT 24
Peak memory 196552 kb
Host smart-1536d9ee-c652-4115-84b3-6df5be287126
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131762314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1131762314
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1316602825
Short name T477
Test name
Test status
Simulation time 81075037 ps
CPU time 1.38 seconds
Started Jul 03 04:26:33 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 197104 kb
Host smart-35db1358-16f5-497f-a74c-17c5a3780f6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316602825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1316602825
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3612604238
Short name T366
Test name
Test status
Simulation time 35173769 ps
CPU time 1.47 seconds
Started Jul 03 04:26:21 PM PDT 24
Finished Jul 03 04:26:23 PM PDT 24
Peak memory 196840 kb
Host smart-b9de3d2f-d69c-4cb2-a285-0d96cf86c8ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612604238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3612604238
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3763428037
Short name T166
Test name
Test status
Simulation time 1747674430 ps
CPU time 2.18 seconds
Started Jul 03 04:26:19 PM PDT 24
Finished Jul 03 04:26:22 PM PDT 24
Peak memory 197060 kb
Host smart-543517ec-5d9a-4001-80ea-f268d10d47c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763428037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3763428037
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.201883007
Short name T351
Test name
Test status
Simulation time 40928984 ps
CPU time 0.64 seconds
Started Jul 03 04:26:15 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 194780 kb
Host smart-0e351d8b-1de7-47f1-a55a-0486505d5222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201883007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.201883007
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.227497228
Short name T133
Test name
Test status
Simulation time 33215438 ps
CPU time 1.12 seconds
Started Jul 03 04:26:30 PM PDT 24
Finished Jul 03 04:26:32 PM PDT 24
Peak memory 197716 kb
Host smart-c5610955-469d-42d0-94d9-06b2b67c516d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227497228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.227497228
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.792977387
Short name T606
Test name
Test status
Simulation time 137827205 ps
CPU time 2.52 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 198576 kb
Host smart-b696718b-a222-4e3d-89a3-e818771682e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792977387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.792977387
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1179014070
Short name T596
Test name
Test status
Simulation time 84358687 ps
CPU time 1 seconds
Started Jul 03 04:26:44 PM PDT 24
Finished Jul 03 04:26:46 PM PDT 24
Peak memory 196316 kb
Host smart-68023424-05fd-48a3-a0eb-9baddc7acee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179014070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1179014070
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3226418574
Short name T12
Test name
Test status
Simulation time 87163194 ps
CPU time 0.92 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:16 PM PDT 24
Peak memory 196240 kb
Host smart-eac1517e-ce19-4bad-9f8a-7891682d9b46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226418574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3226418574
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2122901584
Short name T337
Test name
Test status
Simulation time 24953249745 ps
CPU time 168.07 seconds
Started Jul 03 04:26:24 PM PDT 24
Finished Jul 03 04:29:13 PM PDT 24
Peak memory 198752 kb
Host smart-0bb91480-4a74-49fc-b8d7-c24f9341e30b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122901584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2122901584
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1151179689
Short name T535
Test name
Test status
Simulation time 74954521070 ps
CPU time 932.35 seconds
Started Jul 03 04:26:40 PM PDT 24
Finished Jul 03 04:42:13 PM PDT 24
Peak memory 198924 kb
Host smart-c27d9d2e-cce6-4a9c-bcca-876df736be78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1151179689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1151179689
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.27841293
Short name T519
Test name
Test status
Simulation time 66029945 ps
CPU time 0.56 seconds
Started Jul 03 04:26:35 PM PDT 24
Finished Jul 03 04:26:36 PM PDT 24
Peak memory 194808 kb
Host smart-9d3fe2f8-7b93-4c41-a4ee-fb84d9cdb35a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27841293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.27841293
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1491837046
Short name T522
Test name
Test status
Simulation time 52005316 ps
CPU time 0.65 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 194716 kb
Host smart-874248e0-459f-4267-a285-0f16f5c3dedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491837046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1491837046
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1880932308
Short name T445
Test name
Test status
Simulation time 851942331 ps
CPU time 21.38 seconds
Started Jul 03 04:26:43 PM PDT 24
Finished Jul 03 04:27:05 PM PDT 24
Peak memory 197508 kb
Host smart-be93d311-5fd7-4209-84b6-16215dca9b78
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880932308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1880932308
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.4230183922
Short name T473
Test name
Test status
Simulation time 63333201 ps
CPU time 0.83 seconds
Started Jul 03 04:26:16 PM PDT 24
Finished Jul 03 04:26:19 PM PDT 24
Peak memory 197476 kb
Host smart-da702d32-6693-45a6-b45d-1890b64dbd16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230183922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.4230183922
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1705985495
Short name T308
Test name
Test status
Simulation time 24010780 ps
CPU time 0.68 seconds
Started Jul 03 04:26:22 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 195816 kb
Host smart-27e4a366-6ed5-4bef-8e2d-ef19af5b69c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705985495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1705985495
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1069048726
Short name T623
Test name
Test status
Simulation time 177130768 ps
CPU time 2.36 seconds
Started Jul 03 04:26:47 PM PDT 24
Finished Jul 03 04:26:50 PM PDT 24
Peak memory 198700 kb
Host smart-d7a60ce1-f8bf-40a4-871a-f1847305389d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069048726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1069048726
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1494711924
Short name T126
Test name
Test status
Simulation time 120207150 ps
CPU time 1.38 seconds
Started Jul 03 04:26:56 PM PDT 24
Finished Jul 03 04:26:58 PM PDT 24
Peak memory 197332 kb
Host smart-cc6fe1e7-068d-4056-9158-fdf83d1fb27b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494711924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1494711924
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3759218821
Short name T618
Test name
Test status
Simulation time 43694887 ps
CPU time 1.03 seconds
Started Jul 03 04:26:30 PM PDT 24
Finished Jul 03 04:26:32 PM PDT 24
Peak memory 196628 kb
Host smart-68b751ea-2f21-429e-acfd-487328566e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759218821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3759218821
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.813096850
Short name T317
Test name
Test status
Simulation time 62506306 ps
CPU time 1.2 seconds
Started Jul 03 04:26:44 PM PDT 24
Finished Jul 03 04:26:46 PM PDT 24
Peak memory 197640 kb
Host smart-a94e34c6-e002-462f-a3b9-d0505f8aad7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813096850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.813096850
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.417596580
Short name T301
Test name
Test status
Simulation time 330986436 ps
CPU time 4.79 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 198472 kb
Host smart-38049a71-9fd7-4128-a8fc-8bf10ce45ca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417596580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.417596580
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3512658694
Short name T194
Test name
Test status
Simulation time 56960485 ps
CPU time 0.95 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 196396 kb
Host smart-b59f302c-2a30-4267-96bc-fe2e38facf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512658694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3512658694
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1168327674
Short name T209
Test name
Test status
Simulation time 149905841 ps
CPU time 1.08 seconds
Started Jul 03 04:26:34 PM PDT 24
Finished Jul 03 04:26:35 PM PDT 24
Peak memory 196128 kb
Host smart-4b4f40b7-a5fb-43a9-a3c9-a2a373eeb6c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168327674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1168327674
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1576859252
Short name T608
Test name
Test status
Simulation time 24611023282 ps
CPU time 80.53 seconds
Started Jul 03 04:26:14 PM PDT 24
Finished Jul 03 04:27:37 PM PDT 24
Peak memory 198596 kb
Host smart-b823050a-854d-4e55-9265-4dbbbb7338a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576859252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1576859252
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.170331927
Short name T35
Test name
Test status
Simulation time 89027104936 ps
CPU time 2184.74 seconds
Started Jul 03 04:26:45 PM PDT 24
Finished Jul 03 05:03:10 PM PDT 24
Peak memory 198800 kb
Host smart-23e80f82-fa09-40eb-9daf-448ae7f1d4cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=170331927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.170331927
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2594137347
Short name T572
Test name
Test status
Simulation time 23505604 ps
CPU time 0.55 seconds
Started Jul 03 04:26:19 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 195420 kb
Host smart-f1cdf011-ca7e-46c5-bdc7-50b3512349da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594137347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2594137347
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3969871328
Short name T314
Test name
Test status
Simulation time 44035975 ps
CPU time 0.8 seconds
Started Jul 03 04:26:32 PM PDT 24
Finished Jul 03 04:26:33 PM PDT 24
Peak memory 196900 kb
Host smart-a41eab84-8f26-4f73-9891-270e1f8fcf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969871328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3969871328
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2737144383
Short name T244
Test name
Test status
Simulation time 2188387265 ps
CPU time 27.92 seconds
Started Jul 03 04:26:34 PM PDT 24
Finished Jul 03 04:27:02 PM PDT 24
Peak memory 198704 kb
Host smart-dc925325-44b1-4d5a-ae10-8fec88d473fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737144383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2737144383
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1526863905
Short name T397
Test name
Test status
Simulation time 39013596 ps
CPU time 0.7 seconds
Started Jul 03 04:26:35 PM PDT 24
Finished Jul 03 04:26:37 PM PDT 24
Peak memory 195992 kb
Host smart-aa3dda24-be47-4336-a3df-bc76e650b42f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526863905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1526863905
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4065917177
Short name T140
Test name
Test status
Simulation time 23608565 ps
CPU time 0.63 seconds
Started Jul 03 04:26:13 PM PDT 24
Finished Jul 03 04:26:15 PM PDT 24
Peak memory 195628 kb
Host smart-3a75c4c0-6992-4d66-a51e-6c0b886e77ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065917177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4065917177
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.743148791
Short name T636
Test name
Test status
Simulation time 248574396 ps
CPU time 2.61 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:22 PM PDT 24
Peak memory 198588 kb
Host smart-1bf49f57-1ae5-49d2-a9f9-97aae1e71451
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743148791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.743148791
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.4245540292
Short name T479
Test name
Test status
Simulation time 69929820 ps
CPU time 1.61 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 196604 kb
Host smart-635c6e65-80e5-484c-8786-47b42ee1dcc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245540292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.4245540292
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.612488475
Short name T147
Test name
Test status
Simulation time 193746460 ps
CPU time 1.12 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 197572 kb
Host smart-c9d6719f-e689-4880-bee4-c35c34808fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612488475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.612488475
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2997373318
Short name T438
Test name
Test status
Simulation time 135948356 ps
CPU time 1.22 seconds
Started Jul 03 04:26:30 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 196448 kb
Host smart-5e1345b3-2526-4319-975f-2a3e9a4bc9f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997373318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2997373318
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2821871495
Short name T299
Test name
Test status
Simulation time 51436120 ps
CPU time 1.02 seconds
Started Jul 03 04:26:20 PM PDT 24
Finished Jul 03 04:26:22 PM PDT 24
Peak memory 196788 kb
Host smart-550a776d-5df5-4cb4-a06b-197210ea6c01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821871495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2821871495
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.823822346
Short name T669
Test name
Test status
Simulation time 46684432 ps
CPU time 1.24 seconds
Started Jul 03 04:26:48 PM PDT 24
Finished Jul 03 04:26:50 PM PDT 24
Peak memory 197296 kb
Host smart-dbe8535b-491c-4dbf-87d3-7809713ed7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823822346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.823822346
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1190027738
Short name T373
Test name
Test status
Simulation time 150468686 ps
CPU time 1.22 seconds
Started Jul 03 04:26:42 PM PDT 24
Finished Jul 03 04:26:44 PM PDT 24
Peak memory 197476 kb
Host smart-10f8adb8-73b8-46e2-8f33-9da359af3e33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190027738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1190027738
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4027962865
Short name T371
Test name
Test status
Simulation time 16004182148 ps
CPU time 167.02 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:29:06 PM PDT 24
Peak memory 198792 kb
Host smart-877c567b-3ecd-4117-844d-fbf584baf6eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027962865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4027962865
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3716320710
Short name T644
Test name
Test status
Simulation time 13276365 ps
CPU time 0.56 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 194956 kb
Host smart-63a46f2b-fc9d-4c15-a702-f169c0d08c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716320710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3716320710
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.404731536
Short name T615
Test name
Test status
Simulation time 20353397 ps
CPU time 0.71 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 196548 kb
Host smart-4513c9cd-2301-43f0-b97d-368e10c02073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404731536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.404731536
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2712834952
Short name T543
Test name
Test status
Simulation time 963515459 ps
CPU time 26.56 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:52 PM PDT 24
Peak memory 196052 kb
Host smart-f9684619-7ccd-4c97-b7b0-3b5a20d8b34c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712834952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2712834952
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.441149496
Short name T298
Test name
Test status
Simulation time 135563506 ps
CPU time 0.72 seconds
Started Jul 03 04:25:35 PM PDT 24
Finished Jul 03 04:25:36 PM PDT 24
Peak memory 195360 kb
Host smart-9d5f0458-e43f-4514-9477-456a8cf3c792
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441149496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.441149496
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3885362976
Short name T542
Test name
Test status
Simulation time 32395990 ps
CPU time 0.73 seconds
Started Jul 03 04:25:30 PM PDT 24
Finished Jul 03 04:25:32 PM PDT 24
Peak memory 195868 kb
Host smart-24039e7a-6473-440b-b2aa-904120fa7a38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885362976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3885362976
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.904211650
Short name T288
Test name
Test status
Simulation time 92578330 ps
CPU time 1.15 seconds
Started Jul 03 04:25:35 PM PDT 24
Finished Jul 03 04:25:36 PM PDT 24
Peak memory 198044 kb
Host smart-4c09f672-43d5-417e-96de-a1145c14a20a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904211650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.904211650
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2392561180
Short name T24
Test name
Test status
Simulation time 890430937 ps
CPU time 1.52 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 196632 kb
Host smart-f73e90de-e144-471f-9e51-690229e4d6fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392561180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2392561180
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3018521828
Short name T346
Test name
Test status
Simulation time 751302270 ps
CPU time 1.19 seconds
Started Jul 03 04:25:45 PM PDT 24
Finished Jul 03 04:25:47 PM PDT 24
Peak memory 197704 kb
Host smart-208b9fa4-68be-4d08-bb79-35d345847598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018521828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3018521828
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.135518381
Short name T567
Test name
Test status
Simulation time 522689346 ps
CPU time 1.25 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 197556 kb
Host smart-fd17d106-6ca9-42e8-b620-57960659b7a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135518381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.135518381
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2219367713
Short name T411
Test name
Test status
Simulation time 417041149 ps
CPU time 5.07 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 198592 kb
Host smart-88181f65-4db4-44a5-9a77-5174647c5cc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219367713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2219367713
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1990908724
Short name T44
Test name
Test status
Simulation time 209034900 ps
CPU time 0.87 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 214160 kb
Host smart-b0cb3a4c-22aa-4055-a0f3-8088a9a4b70f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990908724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1990908724
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.269519861
Short name T656
Test name
Test status
Simulation time 68826512 ps
CPU time 1.04 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 196192 kb
Host smart-23e79b0b-a713-4e0a-a30a-d28587eb9ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269519861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.269519861
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2757553179
Short name T513
Test name
Test status
Simulation time 161853573 ps
CPU time 1.24 seconds
Started Jul 03 04:25:37 PM PDT 24
Finished Jul 03 04:25:39 PM PDT 24
Peak memory 197424 kb
Host smart-82cc7430-188b-49a6-a315-029468c5003f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757553179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2757553179
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.892614859
Short name T666
Test name
Test status
Simulation time 29768878963 ps
CPU time 192.37 seconds
Started Jul 03 04:25:48 PM PDT 24
Finished Jul 03 04:29:01 PM PDT 24
Peak memory 198772 kb
Host smart-70657c58-6f67-4418-8eac-69b3ca5e6e0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892614859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.892614859
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.255767801
Short name T64
Test name
Test status
Simulation time 403124783062 ps
CPU time 1933.52 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:57:36 PM PDT 24
Peak memory 198948 kb
Host smart-e448739c-8dfa-43a5-ab19-7424f7534ecd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=255767801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.255767801
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.429536511
Short name T369
Test name
Test status
Simulation time 52467624 ps
CPU time 0.59 seconds
Started Jul 03 04:26:37 PM PDT 24
Finished Jul 03 04:26:38 PM PDT 24
Peak memory 194544 kb
Host smart-efa4e479-a68c-4951-98b1-24c1aae66574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429536511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.429536511
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1682591906
Short name T452
Test name
Test status
Simulation time 43338683 ps
CPU time 0.79 seconds
Started Jul 03 04:26:27 PM PDT 24
Finished Jul 03 04:26:28 PM PDT 24
Peak memory 195768 kb
Host smart-5573da10-96c6-45ad-8e2a-0c72a444f148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682591906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1682591906
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.606024294
Short name T127
Test name
Test status
Simulation time 675326699 ps
CPU time 17.62 seconds
Started Jul 03 04:26:45 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 197476 kb
Host smart-39cd7e85-a99b-4629-b48f-36e33a03e9c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606024294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.606024294
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.263388286
Short name T7
Test name
Test status
Simulation time 179609231 ps
CPU time 1.06 seconds
Started Jul 03 04:26:21 PM PDT 24
Finished Jul 03 04:26:23 PM PDT 24
Peak memory 197140 kb
Host smart-397b7f78-bb72-4587-8b96-b3d17eb037ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263388286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.263388286
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3909047776
Short name T494
Test name
Test status
Simulation time 50856995 ps
CPU time 0.94 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:05 PM PDT 24
Peak memory 197284 kb
Host smart-badd5d8a-821f-4d3d-91f9-e6932039821f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909047776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3909047776
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2536629
Short name T586
Test name
Test status
Simulation time 30722972 ps
CPU time 1.46 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 197208 kb
Host smart-666a13e0-5e1b-4cfe-81cd-115c17aec56c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.gpio_intr_with_filter_rand_intr_event.2536629
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1299857473
Short name T487
Test name
Test status
Simulation time 92300199 ps
CPU time 2.57 seconds
Started Jul 03 04:26:21 PM PDT 24
Finished Jul 03 04:26:24 PM PDT 24
Peak memory 197612 kb
Host smart-ece13249-491a-498c-b2ea-2625a2f42cde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299857473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1299857473
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2303653104
Short name T424
Test name
Test status
Simulation time 33425089 ps
CPU time 1.26 seconds
Started Jul 03 04:26:40 PM PDT 24
Finished Jul 03 04:26:42 PM PDT 24
Peak memory 197724 kb
Host smart-2b8f49b8-12ea-4238-83bc-e3c68822c2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303653104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2303653104
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4189867464
Short name T662
Test name
Test status
Simulation time 62103594 ps
CPU time 0.85 seconds
Started Jul 03 04:26:27 PM PDT 24
Finished Jul 03 04:26:29 PM PDT 24
Peak memory 197208 kb
Host smart-906d3f26-5e29-4138-9e4b-b3288a0a3dd7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189867464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4189867464
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2372525895
Short name T651
Test name
Test status
Simulation time 571194058 ps
CPU time 3.33 seconds
Started Jul 03 04:26:20 PM PDT 24
Finished Jul 03 04:26:24 PM PDT 24
Peak memory 198516 kb
Host smart-9cd7480b-835e-4ba3-9880-3c1c1069e235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372525895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2372525895
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2794239665
Short name T499
Test name
Test status
Simulation time 61455750 ps
CPU time 1.34 seconds
Started Jul 03 04:26:33 PM PDT 24
Finished Jul 03 04:26:35 PM PDT 24
Peak memory 196044 kb
Host smart-45156603-0910-48e5-88aa-06ab14e0987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794239665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2794239665
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.273122620
Short name T238
Test name
Test status
Simulation time 62361956 ps
CPU time 0.96 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:20 PM PDT 24
Peak memory 197144 kb
Host smart-3f203e11-1372-4bc3-9af0-7348465087a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273122620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.273122620
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.23435150
Short name T561
Test name
Test status
Simulation time 7050305582 ps
CPU time 39.17 seconds
Started Jul 03 04:26:20 PM PDT 24
Finished Jul 03 04:27:00 PM PDT 24
Peak memory 198612 kb
Host smart-1474d6d0-3045-4718-86f8-277b19cca6ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23435150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gp
io_stress_all.23435150
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2756023959
Short name T425
Test name
Test status
Simulation time 261556068909 ps
CPU time 1432.74 seconds
Started Jul 03 04:26:38 PM PDT 24
Finished Jul 03 04:50:32 PM PDT 24
Peak memory 198824 kb
Host smart-27331ff3-07b8-4341-8282-be417e3ed588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2756023959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.2756023959
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2409445070
Short name T474
Test name
Test status
Simulation time 13868137 ps
CPU time 0.54 seconds
Started Jul 03 04:26:36 PM PDT 24
Finished Jul 03 04:26:37 PM PDT 24
Peak memory 194496 kb
Host smart-9032dced-a7ad-4ece-a8dd-c7d7cc020b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409445070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2409445070
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2784567166
Short name T223
Test name
Test status
Simulation time 44428510 ps
CPU time 0.89 seconds
Started Jul 03 04:26:45 PM PDT 24
Finished Jul 03 04:26:46 PM PDT 24
Peak memory 197084 kb
Host smart-b458a25a-4a2f-4c76-aa78-0f426855b614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784567166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2784567166
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2564087153
Short name T630
Test name
Test status
Simulation time 109328585 ps
CPU time 5.35 seconds
Started Jul 03 04:26:20 PM PDT 24
Finished Jul 03 04:26:26 PM PDT 24
Peak memory 197468 kb
Host smart-e6434b8d-01de-4ee9-800f-80f0501e9d17
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564087153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2564087153
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2035530634
Short name T467
Test name
Test status
Simulation time 128453098 ps
CPU time 0.78 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 197056 kb
Host smart-a9f0de5c-ff53-4a0b-a08d-ba3dd898ff0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035530634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2035530634
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1145198305
Short name T442
Test name
Test status
Simulation time 43749317 ps
CPU time 1.18 seconds
Started Jul 03 04:26:39 PM PDT 24
Finished Jul 03 04:26:40 PM PDT 24
Peak memory 197624 kb
Host smart-2189ea1a-4f69-45a6-80bf-f13639174410
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145198305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1145198305
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2070597773
Short name T158
Test name
Test status
Simulation time 76454796 ps
CPU time 2.75 seconds
Started Jul 03 04:26:17 PM PDT 24
Finished Jul 03 04:26:26 PM PDT 24
Peak memory 198668 kb
Host smart-49f8fa20-20ec-4dc0-8396-067f102412af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070597773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2070597773
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1569581144
Short name T609
Test name
Test status
Simulation time 294413443 ps
CPU time 1.76 seconds
Started Jul 03 04:26:38 PM PDT 24
Finished Jul 03 04:26:40 PM PDT 24
Peak memory 197488 kb
Host smart-13ac4fbe-5cd0-4476-a2a6-16de151ed4ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569581144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1569581144
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2598180460
Short name T252
Test name
Test status
Simulation time 109273533 ps
CPU time 0.8 seconds
Started Jul 03 04:26:38 PM PDT 24
Finished Jul 03 04:26:39 PM PDT 24
Peak memory 196148 kb
Host smart-05673b8a-e574-4e79-b0c6-bb15d3808615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598180460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2598180460
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3748030924
Short name T553
Test name
Test status
Simulation time 128632979 ps
CPU time 0.87 seconds
Started Jul 03 04:26:18 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 196672 kb
Host smart-93de5f5e-e9aa-40b8-8531-898eb47bbc4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748030924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3748030924
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1062873881
Short name T709
Test name
Test status
Simulation time 137288850 ps
CPU time 3.03 seconds
Started Jul 03 04:26:20 PM PDT 24
Finished Jul 03 04:26:24 PM PDT 24
Peak memory 198600 kb
Host smart-5dcfb549-f879-4b40-a50e-fcc39961db4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062873881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1062873881
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1761072252
Short name T174
Test name
Test status
Simulation time 30210396 ps
CPU time 0.92 seconds
Started Jul 03 04:26:51 PM PDT 24
Finished Jul 03 04:26:52 PM PDT 24
Peak memory 196276 kb
Host smart-e585331e-35c6-44ee-8d06-33a8a141f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761072252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1761072252
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2478241650
Short name T677
Test name
Test status
Simulation time 972379453 ps
CPU time 1.22 seconds
Started Jul 03 04:26:40 PM PDT 24
Finished Jul 03 04:26:42 PM PDT 24
Peak memory 196896 kb
Host smart-9e5017c2-af69-4ef1-bf21-c0c38350cb24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478241650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2478241650
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2437678623
Short name T241
Test name
Test status
Simulation time 1438256970 ps
CPU time 31.4 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:27:13 PM PDT 24
Peak memory 198612 kb
Host smart-9a7e8933-63e6-48d0-8a14-4d4e311420d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437678623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2437678623
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2736467931
Short name T671
Test name
Test status
Simulation time 132325160523 ps
CPU time 534.09 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:35:23 PM PDT 24
Peak memory 206612 kb
Host smart-6fd1e3f1-05c0-4a9b-aedd-0ba50161c4f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2736467931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.2736467931
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1287521790
Short name T665
Test name
Test status
Simulation time 32978856 ps
CPU time 0.56 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 194704 kb
Host smart-6f0cbd8d-a6b8-4c6e-ba7a-4436ee5dd20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287521790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1287521790
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.330331025
Short name T253
Test name
Test status
Simulation time 30208229 ps
CPU time 0.71 seconds
Started Jul 03 04:26:57 PM PDT 24
Finished Jul 03 04:26:58 PM PDT 24
Peak memory 195800 kb
Host smart-165ab2c7-a490-4ce2-9e77-2edc8d1d2500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330331025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.330331025
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4140882136
Short name T281
Test name
Test status
Simulation time 460738284 ps
CPU time 5.96 seconds
Started Jul 03 04:26:50 PM PDT 24
Finished Jul 03 04:26:57 PM PDT 24
Peak memory 196876 kb
Host smart-460fb297-9e46-46e8-92f7-75c66fbfc298
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140882136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4140882136
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1424361590
Short name T486
Test name
Test status
Simulation time 35494003 ps
CPU time 0.63 seconds
Started Jul 03 04:26:35 PM PDT 24
Finished Jul 03 04:26:36 PM PDT 24
Peak memory 195992 kb
Host smart-befc4603-079b-447b-931d-45a7db42556e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424361590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1424361590
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1480120910
Short name T99
Test name
Test status
Simulation time 37081225 ps
CPU time 0.76 seconds
Started Jul 03 04:26:35 PM PDT 24
Finished Jul 03 04:26:36 PM PDT 24
Peak memory 196100 kb
Host smart-786ab6b9-065a-405b-bf3c-352468c596ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480120910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1480120910
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2278368668
Short name T85
Test name
Test status
Simulation time 59840129 ps
CPU time 1.27 seconds
Started Jul 03 04:26:31 PM PDT 24
Finished Jul 03 04:26:33 PM PDT 24
Peak memory 197288 kb
Host smart-ea413d01-6f36-49a3-8939-59fa70049539
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278368668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2278368668
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2442471433
Short name T132
Test name
Test status
Simulation time 548244762 ps
CPU time 3.01 seconds
Started Jul 03 04:26:33 PM PDT 24
Finished Jul 03 04:26:37 PM PDT 24
Peak memory 198592 kb
Host smart-f982161c-c5b9-4d7e-b8a4-31875cf313fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442471433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2442471433
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.4256145813
Short name T332
Test name
Test status
Simulation time 199620163 ps
CPU time 1.02 seconds
Started Jul 03 04:26:51 PM PDT 24
Finished Jul 03 04:26:52 PM PDT 24
Peak memory 196580 kb
Host smart-7714c36f-e8d3-4c4a-90a3-2210a635200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256145813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.4256145813
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.969961415
Short name T645
Test name
Test status
Simulation time 448224339 ps
CPU time 1.19 seconds
Started Jul 03 04:26:44 PM PDT 24
Finished Jul 03 04:26:46 PM PDT 24
Peak memory 197280 kb
Host smart-36770d7e-ebb0-47c7-a2fd-7a5a99566ccc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969961415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.969961415
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2510509743
Short name T435
Test name
Test status
Simulation time 639140117 ps
CPU time 4.72 seconds
Started Jul 03 04:26:51 PM PDT 24
Finished Jul 03 04:27:02 PM PDT 24
Peak memory 198532 kb
Host smart-2924b70b-4eb2-4ee8-889f-72b96bfcffdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510509743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2510509743
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3915818542
Short name T710
Test name
Test status
Simulation time 58590571 ps
CPU time 1.1 seconds
Started Jul 03 04:26:38 PM PDT 24
Finished Jul 03 04:26:39 PM PDT 24
Peak memory 196028 kb
Host smart-72263364-022a-4e2e-b295-735e0e67d5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915818542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3915818542
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.207325003
Short name T216
Test name
Test status
Simulation time 152578598 ps
CPU time 1.08 seconds
Started Jul 03 04:26:32 PM PDT 24
Finished Jul 03 04:26:34 PM PDT 24
Peak memory 196312 kb
Host smart-33637533-da74-4eb8-8fb7-0678fc6fd93d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207325003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.207325003
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.4229016529
Short name T472
Test name
Test status
Simulation time 88295530145 ps
CPU time 130.61 seconds
Started Jul 03 04:26:22 PM PDT 24
Finished Jul 03 04:28:34 PM PDT 24
Peak memory 198612 kb
Host smart-4ec8125a-a006-4e08-b76a-3d4f200dab5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229016529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.4229016529
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3235011190
Short name T566
Test name
Test status
Simulation time 225953607523 ps
CPU time 1421.11 seconds
Started Jul 03 04:26:29 PM PDT 24
Finished Jul 03 04:50:11 PM PDT 24
Peak memory 198888 kb
Host smart-1dda5a99-6e09-4010-a46b-0f4b139552fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3235011190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3235011190
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3014256975
Short name T557
Test name
Test status
Simulation time 41937561 ps
CPU time 0.57 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:05 PM PDT 24
Peak memory 194864 kb
Host smart-77d76d37-42e1-4b15-bdd4-a7d7fd2ff6fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014256975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3014256975
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2480470077
Short name T594
Test name
Test status
Simulation time 337415176 ps
CPU time 0.84 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:26:50 PM PDT 24
Peak memory 197808 kb
Host smart-86a4dd67-3041-4b57-b0c9-bbd5703d723d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480470077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2480470077
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1389097188
Short name T416
Test name
Test status
Simulation time 1622303144 ps
CPU time 12.24 seconds
Started Jul 03 04:26:45 PM PDT 24
Finished Jul 03 04:26:58 PM PDT 24
Peak memory 197696 kb
Host smart-d4b42dc3-a1b0-42ad-8631-f14472afc93f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389097188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1389097188
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3178165012
Short name T403
Test name
Test status
Simulation time 89568143 ps
CPU time 0.92 seconds
Started Jul 03 04:26:57 PM PDT 24
Finished Jul 03 04:26:59 PM PDT 24
Peak memory 197568 kb
Host smart-c3cff574-f5b3-451a-bcaf-852d7344aa3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178165012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3178165012
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1416844331
Short name T391
Test name
Test status
Simulation time 49625973 ps
CPU time 0.78 seconds
Started Jul 03 04:26:42 PM PDT 24
Finished Jul 03 04:26:43 PM PDT 24
Peak memory 196092 kb
Host smart-f8ad23c1-73d4-4f11-ad3f-78dfad0ef8d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416844331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1416844331
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3248117604
Short name T685
Test name
Test status
Simulation time 44647010 ps
CPU time 1.76 seconds
Started Jul 03 04:26:36 PM PDT 24
Finished Jul 03 04:26:38 PM PDT 24
Peak memory 197816 kb
Host smart-f1733b09-d53c-40d8-8993-bd2d670c1f99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248117604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3248117604
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3702124225
Short name T364
Test name
Test status
Simulation time 85739749 ps
CPU time 1.78 seconds
Started Jul 03 04:26:45 PM PDT 24
Finished Jul 03 04:26:47 PM PDT 24
Peak memory 197200 kb
Host smart-8a259ba4-25e9-4ecd-9fce-cbb82b64f6dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702124225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3702124225
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1205235594
Short name T420
Test name
Test status
Simulation time 68523051 ps
CPU time 0.91 seconds
Started Jul 03 04:26:39 PM PDT 24
Finished Jul 03 04:26:40 PM PDT 24
Peak memory 197172 kb
Host smart-50ecad82-c35a-4289-a7ee-f6b7e06e148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205235594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1205235594
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3804075664
Short name T245
Test name
Test status
Simulation time 98289378 ps
CPU time 0.99 seconds
Started Jul 03 04:26:35 PM PDT 24
Finished Jul 03 04:26:37 PM PDT 24
Peak memory 196604 kb
Host smart-91b48510-8a79-4151-91ed-3fdecde55493
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804075664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3804075664
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.374137109
Short name T359
Test name
Test status
Simulation time 308574694 ps
CPU time 4.1 seconds
Started Jul 03 04:26:57 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 198604 kb
Host smart-342de797-1f89-4ed5-aec1-d16725c753a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374137109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.374137109
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3916996787
Short name T222
Test name
Test status
Simulation time 31836658 ps
CPU time 0.76 seconds
Started Jul 03 04:26:29 PM PDT 24
Finished Jul 03 04:26:30 PM PDT 24
Peak memory 196400 kb
Host smart-40873b8b-5a70-4cc1-b664-61e773d878bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916996787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3916996787
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.393939159
Short name T490
Test name
Test status
Simulation time 47129924 ps
CPU time 1.26 seconds
Started Jul 03 04:26:28 PM PDT 24
Finished Jul 03 04:26:30 PM PDT 24
Peak memory 196204 kb
Host smart-6890add5-7f20-4c7c-a38f-de6e9732acdc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393939159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.393939159
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.789129609
Short name T577
Test name
Test status
Simulation time 7739584816 ps
CPU time 100.9 seconds
Started Jul 03 04:26:33 PM PDT 24
Finished Jul 03 04:28:14 PM PDT 24
Peak memory 198728 kb
Host smart-74b12b57-e8d3-4c45-9a4a-4dd2bcb79674
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789129609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.789129609
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1316965174
Short name T531
Test name
Test status
Simulation time 22237281 ps
CPU time 0.58 seconds
Started Jul 03 04:26:57 PM PDT 24
Finished Jul 03 04:26:58 PM PDT 24
Peak memory 194636 kb
Host smart-e6ff73b7-8500-4438-8326-556c9482498a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316965174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1316965174
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1155256649
Short name T450
Test name
Test status
Simulation time 26344305 ps
CPU time 0.87 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:26:51 PM PDT 24
Peak memory 197124 kb
Host smart-ca258286-8333-4db6-8d6d-e6053fee4dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155256649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1155256649
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.4286221749
Short name T350
Test name
Test status
Simulation time 710044641 ps
CPU time 5.45 seconds
Started Jul 03 04:26:32 PM PDT 24
Finished Jul 03 04:26:38 PM PDT 24
Peak memory 197172 kb
Host smart-bf20590b-617d-49a9-a7f7-592d4df63b32
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286221749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.4286221749
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3909123887
Short name T225
Test name
Test status
Simulation time 55886782 ps
CPU time 0.8 seconds
Started Jul 03 04:26:55 PM PDT 24
Finished Jul 03 04:26:56 PM PDT 24
Peak memory 196300 kb
Host smart-aa423eac-1166-4fb6-a15a-a2112cd180d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909123887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3909123887
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1847907391
Short name T322
Test name
Test status
Simulation time 297391342 ps
CPU time 0.8 seconds
Started Jul 03 04:26:34 PM PDT 24
Finished Jul 03 04:26:35 PM PDT 24
Peak memory 197160 kb
Host smart-2821f453-55f9-4a3e-b011-262187ffc740
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847907391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1847907391
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.294189653
Short name T26
Test name
Test status
Simulation time 708027036 ps
CPU time 3.2 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:26:44 PM PDT 24
Peak memory 196812 kb
Host smart-c7e1c438-f5c5-4944-bd63-eca301066747
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294189653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.294189653
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2193875801
Short name T336
Test name
Test status
Simulation time 464285754 ps
CPU time 3.3 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 198668 kb
Host smart-1b86afd5-322d-4c69-8b78-459646bc6cb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193875801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2193875801
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3183825848
Short name T541
Test name
Test status
Simulation time 194731255 ps
CPU time 1 seconds
Started Jul 03 04:26:30 PM PDT 24
Finished Jul 03 04:26:31 PM PDT 24
Peak memory 197252 kb
Host smart-79ad6ef6-b07d-4b4c-b79f-f0f5d622781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183825848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3183825848
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3317705317
Short name T388
Test name
Test status
Simulation time 191419716 ps
CPU time 1.13 seconds
Started Jul 03 04:26:23 PM PDT 24
Finished Jul 03 04:26:25 PM PDT 24
Peak memory 196416 kb
Host smart-e7e81e9e-3b24-48ee-9fc1-8d460a98bce6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317705317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3317705317
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.902836721
Short name T23
Test name
Test status
Simulation time 552044262 ps
CPU time 1.92 seconds
Started Jul 03 04:26:52 PM PDT 24
Finished Jul 03 04:26:54 PM PDT 24
Peak memory 198616 kb
Host smart-29563f9b-8f1c-40fb-80b1-25a02463a690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902836721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.902836721
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.297003855
Short name T413
Test name
Test status
Simulation time 37121962 ps
CPU time 1.08 seconds
Started Jul 03 04:26:38 PM PDT 24
Finished Jul 03 04:26:39 PM PDT 24
Peak memory 197092 kb
Host smart-87a5582d-b5b8-433d-aa31-64f9131fa5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297003855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.297003855
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3221508542
Short name T131
Test name
Test status
Simulation time 177537408 ps
CPU time 0.94 seconds
Started Jul 03 04:26:40 PM PDT 24
Finished Jul 03 04:26:41 PM PDT 24
Peak memory 196308 kb
Host smart-12b696e5-a85a-494b-83e4-735e714bddcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221508542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3221508542
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1737403066
Short name T103
Test name
Test status
Simulation time 82542210390 ps
CPU time 145.77 seconds
Started Jul 03 04:26:34 PM PDT 24
Finished Jul 03 04:29:01 PM PDT 24
Peak memory 198700 kb
Host smart-ec722e61-9bdf-4bcd-924e-dfaa8126ff88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737403066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1737403066
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2668634817
Short name T523
Test name
Test status
Simulation time 28319392116 ps
CPU time 410.98 seconds
Started Jul 03 04:26:30 PM PDT 24
Finished Jul 03 04:33:21 PM PDT 24
Peak memory 198876 kb
Host smart-7729370f-e8b4-4a26-9b9b-dece88b2e765
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2668634817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2668634817
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3683682594
Short name T203
Test name
Test status
Simulation time 22741866 ps
CPU time 0.59 seconds
Started Jul 03 04:26:46 PM PDT 24
Finished Jul 03 04:26:47 PM PDT 24
Peak memory 194820 kb
Host smart-0e43b0b4-5b9a-4fa2-aa6a-1615ce28af50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683682594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3683682594
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2806149343
Short name T240
Test name
Test status
Simulation time 65215828 ps
CPU time 0.72 seconds
Started Jul 03 04:26:48 PM PDT 24
Finished Jul 03 04:26:49 PM PDT 24
Peak memory 196396 kb
Host smart-a7fe4374-eb61-409b-978d-1a77552bc393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806149343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2806149343
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.548204676
Short name T293
Test name
Test status
Simulation time 612307276 ps
CPU time 21.77 seconds
Started Jul 03 04:26:59 PM PDT 24
Finished Jul 03 04:27:21 PM PDT 24
Peak memory 197512 kb
Host smart-b187390a-0792-471d-9729-24e8f4d76eb1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548204676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.548204676
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.369976973
Short name T3
Test name
Test status
Simulation time 78640148 ps
CPU time 0.93 seconds
Started Jul 03 04:26:58 PM PDT 24
Finished Jul 03 04:26:59 PM PDT 24
Peak memory 196780 kb
Host smart-4b4c0efa-5fa0-4242-99e6-2b933e9ed253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369976973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.369976973
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1155890895
Short name T122
Test name
Test status
Simulation time 24340702 ps
CPU time 0.66 seconds
Started Jul 03 04:26:59 PM PDT 24
Finished Jul 03 04:27:00 PM PDT 24
Peak memory 195692 kb
Host smart-34f80462-9979-4a48-aca2-85032bc4aaed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155890895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1155890895
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2801739064
Short name T544
Test name
Test status
Simulation time 74542203 ps
CPU time 1.55 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 197224 kb
Host smart-d0412a03-0efe-4d1c-b951-adbd4f5e9e61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801739064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2801739064
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3187966259
Short name T641
Test name
Test status
Simulation time 128534511 ps
CPU time 3.5 seconds
Started Jul 03 04:26:48 PM PDT 24
Finished Jul 03 04:26:52 PM PDT 24
Peak memory 198696 kb
Host smart-9cff95f0-c693-46f2-81d9-287e7e315d43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187966259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3187966259
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2450697019
Short name T539
Test name
Test status
Simulation time 45952782 ps
CPU time 0.73 seconds
Started Jul 03 04:26:38 PM PDT 24
Finished Jul 03 04:26:40 PM PDT 24
Peak memory 196632 kb
Host smart-d791a8cd-14f6-43c6-bcf2-791472dc1519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450697019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2450697019
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1151529307
Short name T574
Test name
Test status
Simulation time 83312393 ps
CPU time 1.14 seconds
Started Jul 03 04:26:46 PM PDT 24
Finished Jul 03 04:26:48 PM PDT 24
Peak memory 197468 kb
Host smart-88c14b65-5491-44d4-b5c2-dfbe698c31a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151529307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1151529307
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1348117935
Short name T627
Test name
Test status
Simulation time 203618059 ps
CPU time 4.55 seconds
Started Jul 03 04:26:50 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 198560 kb
Host smart-f8af9b7a-3b28-41a1-bc64-0e738102102a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348117935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1348117935
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1960763707
Short name T102
Test name
Test status
Simulation time 37690414 ps
CPU time 1.11 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:26:51 PM PDT 24
Peak memory 196472 kb
Host smart-d48a159d-3378-42cc-ace3-d46330247858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960763707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1960763707
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1095168252
Short name T206
Test name
Test status
Simulation time 28340430 ps
CPU time 0.79 seconds
Started Jul 03 04:26:38 PM PDT 24
Finished Jul 03 04:26:40 PM PDT 24
Peak memory 195772 kb
Host smart-25109fd9-80a9-4da0-ab0f-d4accb9b6a1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095168252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1095168252
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2661737753
Short name T382
Test name
Test status
Simulation time 42209262053 ps
CPU time 63.88 seconds
Started Jul 03 04:26:51 PM PDT 24
Finished Jul 03 04:27:55 PM PDT 24
Peak memory 198600 kb
Host smart-fba79ecc-2db7-4c48-a3ac-e2a4b9fc6a20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661737753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2661737753
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.850768761
Short name T121
Test name
Test status
Simulation time 45016699072 ps
CPU time 1264.44 seconds
Started Jul 03 04:26:33 PM PDT 24
Finished Jul 03 04:47:38 PM PDT 24
Peak memory 198840 kb
Host smart-b322a8a4-fa40-46f4-b917-592c13e0942f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=850768761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.850768761
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3164678586
Short name T123
Test name
Test status
Simulation time 16451788 ps
CPU time 0.55 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:26:54 PM PDT 24
Peak memory 193372 kb
Host smart-1f3ceff7-3da6-4ff3-afc5-2b156186760d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164678586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3164678586
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2665184732
Short name T385
Test name
Test status
Simulation time 28065316 ps
CPU time 0.77 seconds
Started Jul 03 04:26:46 PM PDT 24
Finished Jul 03 04:26:47 PM PDT 24
Peak memory 196580 kb
Host smart-0215954b-d953-41bb-9ebb-3a26cc281f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665184732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2665184732
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3696082047
Short name T357
Test name
Test status
Simulation time 1540137756 ps
CPU time 3.49 seconds
Started Jul 03 04:26:42 PM PDT 24
Finished Jul 03 04:26:46 PM PDT 24
Peak memory 196932 kb
Host smart-10be3b9b-d0dd-483f-8611-dbd5b7a3d494
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696082047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3696082047
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1926268940
Short name T686
Test name
Test status
Simulation time 56930227 ps
CPU time 0.92 seconds
Started Jul 03 04:26:48 PM PDT 24
Finished Jul 03 04:26:50 PM PDT 24
Peak memory 197644 kb
Host smart-a005d84d-d5fe-4699-acc0-9e8e8140d244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926268940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1926268940
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2843178217
Short name T563
Test name
Test status
Simulation time 30485040 ps
CPU time 0.9 seconds
Started Jul 03 04:26:48 PM PDT 24
Finished Jul 03 04:26:50 PM PDT 24
Peak memory 197044 kb
Host smart-dc215b52-6dfd-4cd1-a9ca-4908ecc76db2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843178217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2843178217
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2573460368
Short name T275
Test name
Test status
Simulation time 272101585 ps
CPU time 2.82 seconds
Started Jul 03 04:26:58 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 198720 kb
Host smart-3a50464d-32c6-45bb-a770-c82d00a493fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573460368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2573460368
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2520717292
Short name T675
Test name
Test status
Simulation time 479078047 ps
CPU time 2.56 seconds
Started Jul 03 04:27:01 PM PDT 24
Finished Jul 03 04:27:05 PM PDT 24
Peak memory 198620 kb
Host smart-cbb2ad67-50e1-4f4f-9119-3f99d67b2431
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520717292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2520717292
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.63326478
Short name T637
Test name
Test status
Simulation time 31840873 ps
CPU time 0.89 seconds
Started Jul 03 04:27:05 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 197044 kb
Host smart-dc3d3d2c-7557-4de4-9c41-dcb57421afce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63326478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.63326478
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1447243888
Short name T135
Test name
Test status
Simulation time 145167708 ps
CPU time 1.28 seconds
Started Jul 03 04:26:47 PM PDT 24
Finished Jul 03 04:26:49 PM PDT 24
Peak memory 197588 kb
Host smart-f0791e72-df12-4081-b02b-922234bfcb7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447243888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1447243888
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3681096087
Short name T297
Test name
Test status
Simulation time 227523558 ps
CPU time 3.57 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:26:46 PM PDT 24
Peak memory 198380 kb
Host smart-50d24cc1-87d7-4aeb-b601-e27f0596d158
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681096087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3681096087
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1873416988
Short name T378
Test name
Test status
Simulation time 164090174 ps
CPU time 0.87 seconds
Started Jul 03 04:26:39 PM PDT 24
Finished Jul 03 04:26:40 PM PDT 24
Peak memory 196312 kb
Host smart-fdae86a7-a1e4-4a3d-98ae-cf49760aff06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873416988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1873416988
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1897110651
Short name T605
Test name
Test status
Simulation time 162392839 ps
CPU time 0.99 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 196348 kb
Host smart-7f1d3d6d-a028-43cd-aa0d-6ba6a01959c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897110651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1897110651
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.181689932
Short name T638
Test name
Test status
Simulation time 11802604746 ps
CPU time 123.59 seconds
Started Jul 03 04:26:58 PM PDT 24
Finished Jul 03 04:29:07 PM PDT 24
Peak memory 198620 kb
Host smart-ec8cc2fb-32d4-48fa-b4df-c07311d1d97c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181689932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.181689932
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2110727604
Short name T36
Test name
Test status
Simulation time 45101685449 ps
CPU time 912.88 seconds
Started Jul 03 04:27:52 PM PDT 24
Finished Jul 03 04:43:05 PM PDT 24
Peak memory 198872 kb
Host smart-c59cb441-2a35-4edb-9d31-7d826330c2ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2110727604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2110727604
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3717832311
Short name T45
Test name
Test status
Simulation time 12524577 ps
CPU time 0.59 seconds
Started Jul 03 04:27:24 PM PDT 24
Finished Jul 03 04:27:25 PM PDT 24
Peak memory 194684 kb
Host smart-efbac6e4-c1ec-40a0-9460-b7715f6c3c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717832311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3717832311
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2642366674
Short name T148
Test name
Test status
Simulation time 508259518 ps
CPU time 0.87 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 196296 kb
Host smart-be4d3d89-baa7-42fb-9435-6ee943f75cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642366674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2642366674
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.266385899
Short name T250
Test name
Test status
Simulation time 1685710125 ps
CPU time 24.3 seconds
Started Jul 03 04:26:31 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 197512 kb
Host smart-a19fd05c-7897-4dd9-a396-404a702c3abc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266385899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.266385899
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.702830752
Short name T521
Test name
Test status
Simulation time 203356620 ps
CPU time 0.88 seconds
Started Jul 03 04:27:25 PM PDT 24
Finished Jul 03 04:27:26 PM PDT 24
Peak memory 197340 kb
Host smart-59af0eaf-e70d-4a2b-8c24-e1aeb9277fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702830752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.702830752
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1317717668
Short name T647
Test name
Test status
Simulation time 33341983 ps
CPU time 0.71 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:26:51 PM PDT 24
Peak memory 196040 kb
Host smart-d5867821-fc5c-47ec-b00c-17547e0fc8ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317717668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1317717668
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3634246833
Short name T583
Test name
Test status
Simulation time 38044281 ps
CPU time 1.49 seconds
Started Jul 03 04:26:52 PM PDT 24
Finished Jul 03 04:26:54 PM PDT 24
Peak memory 197472 kb
Host smart-dc7f502a-26e4-4d8f-a689-12ef1d48c98e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634246833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3634246833
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1876522151
Short name T328
Test name
Test status
Simulation time 123224036 ps
CPU time 2.55 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:26:44 PM PDT 24
Peak memory 198676 kb
Host smart-0870b479-48c3-4570-a1f2-c0e058a88bf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876522151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1876522151
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.473812903
Short name T701
Test name
Test status
Simulation time 74459834 ps
CPU time 0.76 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:26:42 PM PDT 24
Peak memory 195900 kb
Host smart-a139d8ff-387a-49d5-b952-86a3d9a22bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473812903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.473812903
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.636540305
Short name T146
Test name
Test status
Simulation time 127143066 ps
CPU time 1.26 seconds
Started Jul 03 04:26:48 PM PDT 24
Finished Jul 03 04:26:50 PM PDT 24
Peak memory 196308 kb
Host smart-61f9b43a-5acf-4095-b4c8-a9a5f6585daf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636540305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.636540305
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1126094272
Short name T179
Test name
Test status
Simulation time 62915646 ps
CPU time 1.54 seconds
Started Jul 03 04:27:27 PM PDT 24
Finished Jul 03 04:27:29 PM PDT 24
Peak memory 198532 kb
Host smart-4f93e41a-4943-4303-a023-42bb96bab059
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126094272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1126094272
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4111455876
Short name T73
Test name
Test status
Simulation time 71080773 ps
CPU time 1.31 seconds
Started Jul 03 04:27:15 PM PDT 24
Finished Jul 03 04:27:17 PM PDT 24
Peak memory 197292 kb
Host smart-c0d57c59-aeef-43b6-8eb9-e0bde030719f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111455876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4111455876
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1465154739
Short name T546
Test name
Test status
Simulation time 37576586 ps
CPU time 1.02 seconds
Started Jul 03 04:26:45 PM PDT 24
Finished Jul 03 04:26:46 PM PDT 24
Peak memory 196192 kb
Host smart-74266472-6391-486c-bc02-9289deb05cca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465154739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1465154739
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2191810791
Short name T305
Test name
Test status
Simulation time 13524675365 ps
CPU time 196.17 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:30:06 PM PDT 24
Peak memory 198740 kb
Host smart-056d0c2a-def0-435a-982b-e91c3ccd0438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191810791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2191810791
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.60531203
Short name T680
Test name
Test status
Simulation time 42193617 ps
CPU time 0.57 seconds
Started Jul 03 04:26:58 PM PDT 24
Finished Jul 03 04:26:59 PM PDT 24
Peak memory 194536 kb
Host smart-fa91cfa4-95d8-4a22-bff6-ffac1dd12bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60531203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.60531203
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2700566685
Short name T414
Test name
Test status
Simulation time 46346534 ps
CPU time 0.91 seconds
Started Jul 03 04:26:51 PM PDT 24
Finished Jul 03 04:26:53 PM PDT 24
Peak memory 197868 kb
Host smart-390f96ba-9a23-40ec-9b43-fb184ee33af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700566685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2700566685
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2555320462
Short name T488
Test name
Test status
Simulation time 1448228270 ps
CPU time 21.85 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 197344 kb
Host smart-4f250abe-c7a2-4c8f-a0e9-b7e4a6571605
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555320462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2555320462
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3679787467
Short name T229
Test name
Test status
Simulation time 235053758 ps
CPU time 0.9 seconds
Started Jul 03 04:26:55 PM PDT 24
Finished Jul 03 04:26:56 PM PDT 24
Peak memory 197784 kb
Host smart-d4b41d9f-aa4d-4cb5-9d1a-092743c212ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679787467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3679787467
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1731471735
Short name T165
Test name
Test status
Simulation time 42638089 ps
CPU time 0.8 seconds
Started Jul 03 04:26:42 PM PDT 24
Finished Jul 03 04:26:43 PM PDT 24
Peak memory 196940 kb
Host smart-6e78e62d-b627-462d-8834-ac87fc85ac7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731471735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1731471735
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.696313720
Short name T247
Test name
Test status
Simulation time 200886620 ps
CPU time 2.23 seconds
Started Jul 03 04:26:42 PM PDT 24
Finished Jul 03 04:26:45 PM PDT 24
Peak memory 198644 kb
Host smart-92a2e1ec-926e-4531-9e15-067cba7c292a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696313720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.696313720
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3173449492
Short name T342
Test name
Test status
Simulation time 77874409 ps
CPU time 2.22 seconds
Started Jul 03 04:27:04 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 198540 kb
Host smart-26956268-e330-4737-9277-fcccc57281d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173449492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3173449492
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1259427992
Short name T258
Test name
Test status
Simulation time 61924020 ps
CPU time 1.2 seconds
Started Jul 03 04:26:51 PM PDT 24
Finished Jul 03 04:26:53 PM PDT 24
Peak memory 198516 kb
Host smart-e9e42a71-a858-47e8-972e-9f89301bb6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259427992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1259427992
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.988626721
Short name T717
Test name
Test status
Simulation time 108051865 ps
CPU time 0.95 seconds
Started Jul 03 04:26:58 PM PDT 24
Finished Jul 03 04:26:59 PM PDT 24
Peak memory 196432 kb
Host smart-d35c0b6f-8c4e-480f-b495-3224579e4ef9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988626721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.988626721
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.4242399283
Short name T151
Test name
Test status
Simulation time 95959787 ps
CPU time 1.7 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 198544 kb
Host smart-95012810-25f0-474d-8f7c-3845c9241985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242399283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.4242399283
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2647423053
Short name T58
Test name
Test status
Simulation time 63545654 ps
CPU time 1.08 seconds
Started Jul 03 04:26:55 PM PDT 24
Finished Jul 03 04:26:57 PM PDT 24
Peak memory 196044 kb
Host smart-25f6e72a-4511-4036-8a19-4c9f47b023e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647423053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2647423053
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2336698387
Short name T530
Test name
Test status
Simulation time 185194850 ps
CPU time 1.35 seconds
Started Jul 03 04:26:59 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 198528 kb
Host smart-7c265ac2-6496-4bb6-836d-cd0b4c35f76c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336698387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2336698387
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.311881164
Short name T524
Test name
Test status
Simulation time 8724587465 ps
CPU time 116.91 seconds
Started Jul 03 04:26:49 PM PDT 24
Finished Jul 03 04:28:47 PM PDT 24
Peak memory 198700 kb
Host smart-b3db3d96-2663-4943-bd10-314c415c0c45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311881164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.311881164
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2502898118
Short name T63
Test name
Test status
Simulation time 58822568573 ps
CPU time 402.83 seconds
Started Jul 03 04:26:37 PM PDT 24
Finished Jul 03 04:33:21 PM PDT 24
Peak memory 198708 kb
Host smart-ebe4ba19-aa30-4ae1-a77b-5cba59304913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2502898118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2502898118
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.517077585
Short name T372
Test name
Test status
Simulation time 46050934 ps
CPU time 0.58 seconds
Started Jul 03 04:27:09 PM PDT 24
Finished Jul 03 04:27:11 PM PDT 24
Peak memory 196368 kb
Host smart-08514701-69ee-426f-b394-4f4f4bd6ba92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517077585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.517077585
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.857575055
Short name T224
Test name
Test status
Simulation time 20577857 ps
CPU time 0.68 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:26:54 PM PDT 24
Peak memory 195308 kb
Host smart-f332c914-7fb4-497e-bbe6-b282cf992ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857575055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.857575055
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2468191810
Short name T706
Test name
Test status
Simulation time 1018787920 ps
CPU time 25.21 seconds
Started Jul 03 04:26:51 PM PDT 24
Finished Jul 03 04:27:16 PM PDT 24
Peak memory 197400 kb
Host smart-795b57d2-d9a2-4c78-8a40-0a868be17627
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468191810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2468191810
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2102102369
Short name T291
Test name
Test status
Simulation time 122928749 ps
CPU time 0.69 seconds
Started Jul 03 04:27:00 PM PDT 24
Finished Jul 03 04:27:06 PM PDT 24
Peak memory 195180 kb
Host smart-d62449aa-e0d4-47f4-9c77-ffc7d859139d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102102369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2102102369
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2152490512
Short name T270
Test name
Test status
Simulation time 26601937 ps
CPU time 0.64 seconds
Started Jul 03 04:26:59 PM PDT 24
Finished Jul 03 04:27:00 PM PDT 24
Peak memory 194996 kb
Host smart-05dc1b2c-5d3a-4a19-bdc6-ae1873184fc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152490512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2152490512
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2511137820
Short name T177
Test name
Test status
Simulation time 126220051 ps
CPU time 2.59 seconds
Started Jul 03 04:26:52 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 198608 kb
Host smart-e36e53f9-6992-4e70-a901-feeb4f159617
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511137820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2511137820
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.653589135
Short name T183
Test name
Test status
Simulation time 38980037 ps
CPU time 1.2 seconds
Started Jul 03 04:26:46 PM PDT 24
Finished Jul 03 04:26:48 PM PDT 24
Peak memory 197732 kb
Host smart-f558542d-c2d5-46b5-a27f-177e5bcf8e5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653589135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
653589135
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.141053795
Short name T267
Test name
Test status
Simulation time 49471762 ps
CPU time 1.05 seconds
Started Jul 03 04:27:02 PM PDT 24
Finished Jul 03 04:27:04 PM PDT 24
Peak memory 197344 kb
Host smart-1bfd05c2-5bad-464e-a5ff-3a58c53a5579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141053795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.141053795
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2542434670
Short name T173
Test name
Test status
Simulation time 262918980 ps
CPU time 1.23 seconds
Started Jul 03 04:27:06 PM PDT 24
Finished Jul 03 04:27:09 PM PDT 24
Peak memory 198728 kb
Host smart-0020161e-7b64-4cc0-82fc-d78eee45770d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542434670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2542434670
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1840067082
Short name T713
Test name
Test status
Simulation time 429884726 ps
CPU time 4.69 seconds
Started Jul 03 04:26:41 PM PDT 24
Finished Jul 03 04:26:47 PM PDT 24
Peak memory 198472 kb
Host smart-820246d5-1b25-4090-9d73-789061f9e769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840067082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1840067082
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2257669356
Short name T315
Test name
Test status
Simulation time 39015169 ps
CPU time 0.86 seconds
Started Jul 03 04:26:56 PM PDT 24
Finished Jul 03 04:26:57 PM PDT 24
Peak memory 196900 kb
Host smart-55e12031-864a-4473-81ee-500c8ad5d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257669356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2257669356
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2890707985
Short name T384
Test name
Test status
Simulation time 79670275 ps
CPU time 0.91 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 197736 kb
Host smart-3e9dec39-9317-4e00-8e8a-da99a05dabf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890707985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2890707985
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.144671010
Short name T695
Test name
Test status
Simulation time 16931667299 ps
CPU time 98.16 seconds
Started Jul 03 04:26:58 PM PDT 24
Finished Jul 03 04:28:37 PM PDT 24
Peak memory 198644 kb
Host smart-6b4b46f7-52d6-4cd8-9d34-a8868560f6c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144671010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.144671010
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.204796
Short name T508
Test name
Test status
Simulation time 71593260026 ps
CPU time 477.8 seconds
Started Jul 03 04:26:53 PM PDT 24
Finished Jul 03 04:34:51 PM PDT 24
Peak memory 198804 kb
Host smart-87afa70f-e209-4a72-a435-4c8aebd3689e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=204796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.204796
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1504870493
Short name T264
Test name
Test status
Simulation time 10218504 ps
CPU time 0.55 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 194488 kb
Host smart-d1969293-e891-4846-a216-55bc845351b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504870493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1504870493
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.175480992
Short name T536
Test name
Test status
Simulation time 59080158 ps
CPU time 0.58 seconds
Started Jul 03 04:25:34 PM PDT 24
Finished Jul 03 04:25:35 PM PDT 24
Peak memory 195268 kb
Host smart-5a8c5b93-a8bb-4b99-bc6f-714540327134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175480992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.175480992
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3001967281
Short name T595
Test name
Test status
Simulation time 883626519 ps
CPU time 11.89 seconds
Started Jul 03 04:26:06 PM PDT 24
Finished Jul 03 04:26:18 PM PDT 24
Peak memory 196860 kb
Host smart-01baf88b-7961-4ea3-b6ca-7faa2af9efa1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001967281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3001967281
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3481343582
Short name T104
Test name
Test status
Simulation time 82398746 ps
CPU time 0.94 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 197532 kb
Host smart-9125a2f4-c982-4c83-a19f-cbd37c27c341
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481343582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3481343582
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3775196973
Short name T196
Test name
Test status
Simulation time 167503640 ps
CPU time 1.33 seconds
Started Jul 03 04:25:33 PM PDT 24
Finished Jul 03 04:25:35 PM PDT 24
Peak memory 197776 kb
Host smart-742331aa-303e-4c0d-8df7-28c38f79d792
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775196973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3775196973
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3514152308
Short name T29
Test name
Test status
Simulation time 68417555 ps
CPU time 1.36 seconds
Started Jul 03 04:25:19 PM PDT 24
Finished Jul 03 04:25:21 PM PDT 24
Peak memory 197208 kb
Host smart-a9883bcf-9097-46b7-ac9c-53b2163b5fd8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514152308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3514152308
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3466315667
Short name T466
Test name
Test status
Simulation time 521141132 ps
CPU time 2.46 seconds
Started Jul 03 04:25:34 PM PDT 24
Finished Jul 03 04:25:37 PM PDT 24
Peak memory 198628 kb
Host smart-415914ca-6a60-45b9-9fda-9660f8b284a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466315667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3466315667
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1957153819
Short name T341
Test name
Test status
Simulation time 111967680 ps
CPU time 1.12 seconds
Started Jul 03 04:25:20 PM PDT 24
Finished Jul 03 04:25:22 PM PDT 24
Peak memory 197444 kb
Host smart-838b893b-8acf-4b18-a6f5-108571e3df46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957153819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1957153819
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3409145330
Short name T139
Test name
Test status
Simulation time 450164255 ps
CPU time 0.94 seconds
Started Jul 03 04:25:55 PM PDT 24
Finished Jul 03 04:25:57 PM PDT 24
Peak memory 197260 kb
Host smart-f1177038-0ab6-4161-a475-2ce3957ac03a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409145330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3409145330
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1260004173
Short name T60
Test name
Test status
Simulation time 1972558756 ps
CPU time 1.89 seconds
Started Jul 03 04:25:48 PM PDT 24
Finished Jul 03 04:25:50 PM PDT 24
Peak memory 198380 kb
Host smart-3f95ca6f-4863-4043-b157-ee6bedd870f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260004173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1260004173
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1552155309
Short name T150
Test name
Test status
Simulation time 571656000 ps
CPU time 1.34 seconds
Started Jul 03 04:25:46 PM PDT 24
Finished Jul 03 04:25:48 PM PDT 24
Peak memory 196168 kb
Host smart-521232c9-77c0-4e81-a133-f49f81ea06e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552155309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1552155309
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2099264998
Short name T259
Test name
Test status
Simulation time 40143135 ps
CPU time 1.04 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 196328 kb
Host smart-abfaced9-6075-4c1d-9201-f5e5ddabe86c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099264998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2099264998
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1365205355
Short name T338
Test name
Test status
Simulation time 14356122600 ps
CPU time 166.48 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:28:13 PM PDT 24
Peak memory 198576 kb
Host smart-7c91f81a-e1b8-4a80-80b4-466df2c59eab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365205355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1365205355
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2671100966
Short name T581
Test name
Test status
Simulation time 12115750 ps
CPU time 0.56 seconds
Started Jul 03 04:25:49 PM PDT 24
Finished Jul 03 04:25:49 PM PDT 24
Peak memory 194532 kb
Host smart-a8f54e4e-5004-49ad-bea4-f046e39b0e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671100966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2671100966
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.4111611350
Short name T375
Test name
Test status
Simulation time 36496695 ps
CPU time 0.84 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 196476 kb
Host smart-e9c99ad0-af4a-4699-8a6c-8fd5f4523e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111611350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.4111611350
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.991569945
Short name T377
Test name
Test status
Simulation time 14989148433 ps
CPU time 21.89 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:26:06 PM PDT 24
Peak memory 197104 kb
Host smart-03d6ca15-b47c-4d4a-882c-5134dd38b5f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991569945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.991569945
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3101169638
Short name T75
Test name
Test status
Simulation time 551581902 ps
CPU time 1.01 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:02 PM PDT 24
Peak memory 197248 kb
Host smart-2873af2f-d2f3-45e7-b4a5-66af2d10da38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101169638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3101169638
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.302486560
Short name T233
Test name
Test status
Simulation time 144533761 ps
CPU time 0.91 seconds
Started Jul 03 04:25:22 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 196820 kb
Host smart-e2702512-175e-485a-8e20-f8db5885a507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302486560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.302486560
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2446933669
Short name T687
Test name
Test status
Simulation time 52245514 ps
CPU time 2.13 seconds
Started Jul 03 04:25:48 PM PDT 24
Finished Jul 03 04:25:50 PM PDT 24
Peak memory 198544 kb
Host smart-0adb8af4-9352-43ec-aa9e-3621cff98324
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446933669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2446933669
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.568298824
Short name T204
Test name
Test status
Simulation time 373291319 ps
CPU time 2.71 seconds
Started Jul 03 04:25:44 PM PDT 24
Finished Jul 03 04:25:48 PM PDT 24
Peak memory 197460 kb
Host smart-3f553697-cae0-4353-b9cb-3e6862cda629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568298824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.568298824
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.506080580
Short name T498
Test name
Test status
Simulation time 351484261 ps
CPU time 0.81 seconds
Started Jul 03 04:25:35 PM PDT 24
Finished Jul 03 04:25:36 PM PDT 24
Peak memory 197736 kb
Host smart-48ef3f64-2066-4761-8f60-b41afca04acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506080580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.506080580
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.4004033524
Short name T211
Test name
Test status
Simulation time 31621249 ps
CPU time 1.12 seconds
Started Jul 03 04:25:44 PM PDT 24
Finished Jul 03 04:25:46 PM PDT 24
Peak memory 197664 kb
Host smart-ebf76146-8fc3-46fb-8592-71cc87b2d286
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004033524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.4004033524
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.636609651
Short name T5
Test name
Test status
Simulation time 874527584 ps
CPU time 4.81 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:34 PM PDT 24
Peak memory 198568 kb
Host smart-39ff2568-c567-4eff-b8a2-83f404481076
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636609651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.636609651
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.962646141
Short name T28
Test name
Test status
Simulation time 43650449 ps
CPU time 1.16 seconds
Started Jul 03 04:25:21 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 198556 kb
Host smart-801b41b6-bd8d-4436-ba89-946bdbb38695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962646141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.962646141
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1251938123
Short name T588
Test name
Test status
Simulation time 149765678 ps
CPU time 1.09 seconds
Started Jul 03 04:25:47 PM PDT 24
Finished Jul 03 04:25:49 PM PDT 24
Peak memory 196112 kb
Host smart-afe1d38e-2cef-4214-8b43-2c387b85c97c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251938123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1251938123
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3436223884
Short name T10
Test name
Test status
Simulation time 24116035652 ps
CPU time 36.93 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:26:06 PM PDT 24
Peak memory 198692 kb
Host smart-666d8a51-caeb-41b2-80f6-b13d8e052f40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436223884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3436223884
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3950282488
Short name T446
Test name
Test status
Simulation time 47803765 ps
CPU time 0.56 seconds
Started Jul 03 04:25:45 PM PDT 24
Finished Jul 03 04:25:46 PM PDT 24
Peak memory 195496 kb
Host smart-b588c399-2714-40bd-b575-de475af839bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950282488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3950282488
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.456495330
Short name T271
Test name
Test status
Simulation time 40561847 ps
CPU time 0.94 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:25:45 PM PDT 24
Peak memory 197188 kb
Host smart-d5974931-b8be-4477-9531-48645b27544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456495330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.456495330
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.526884820
Short name T276
Test name
Test status
Simulation time 1700707974 ps
CPU time 6.27 seconds
Started Jul 03 04:25:45 PM PDT 24
Finished Jul 03 04:25:52 PM PDT 24
Peak memory 197372 kb
Host smart-963f1986-7e73-49b5-b66c-c6a05b05dfd5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526884820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.526884820
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.388627720
Short name T470
Test name
Test status
Simulation time 158938904 ps
CPU time 0.82 seconds
Started Jul 03 04:25:49 PM PDT 24
Finished Jul 03 04:25:50 PM PDT 24
Peak memory 196520 kb
Host smart-9c82d219-75ed-42d8-baea-b48e0a73b30c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388627720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.388627720
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1779428962
Short name T201
Test name
Test status
Simulation time 142708052 ps
CPU time 1.41 seconds
Started Jul 03 04:25:54 PM PDT 24
Finished Jul 03 04:25:57 PM PDT 24
Peak memory 196404 kb
Host smart-28e3b601-08a3-4801-88bc-faa35afc618b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779428962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1779428962
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3945753478
Short name T634
Test name
Test status
Simulation time 368178860 ps
CPU time 3.65 seconds
Started Jul 03 04:25:43 PM PDT 24
Finished Jul 03 04:25:48 PM PDT 24
Peak memory 198664 kb
Host smart-917dfc6e-2b7d-4455-b81a-2b0c63c1a204
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945753478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3945753478
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1578525009
Short name T518
Test name
Test status
Simulation time 2300573306 ps
CPU time 2.6 seconds
Started Jul 03 04:26:00 PM PDT 24
Finished Jul 03 04:26:04 PM PDT 24
Peak memory 198756 kb
Host smart-9081f7f0-4f53-48db-8d3d-d051ce1b959b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578525009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1578525009
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3580715749
Short name T81
Test name
Test status
Simulation time 117446987 ps
CPU time 0.93 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 197116 kb
Host smart-2c8b270e-906d-4280-8d99-8f4da6c5be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580715749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3580715749
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2356245508
Short name T202
Test name
Test status
Simulation time 242442924 ps
CPU time 0.74 seconds
Started Jul 03 04:25:19 PM PDT 24
Finished Jul 03 04:25:21 PM PDT 24
Peak memory 196120 kb
Host smart-f4256f08-f73d-4200-becb-0f7474cff4d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356245508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2356245508
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.707113454
Short name T504
Test name
Test status
Simulation time 1125948207 ps
CPU time 4.17 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 198436 kb
Host smart-ec8b29f4-406d-4a5b-bd61-ce73c74ac1f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707113454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.707113454
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1904923137
Short name T679
Test name
Test status
Simulation time 48552881 ps
CPU time 0.81 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:30 PM PDT 24
Peak memory 195876 kb
Host smart-c5ccc218-8787-487e-ba77-df8b424d5d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904923137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1904923137
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2181015573
Short name T434
Test name
Test status
Simulation time 21787157 ps
CPU time 0.68 seconds
Started Jul 03 04:25:38 PM PDT 24
Finished Jul 03 04:25:39 PM PDT 24
Peak memory 194760 kb
Host smart-b56d5fc6-84c0-4a48-b246-af8597a3ce15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181015573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2181015573
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2367452760
Short name T376
Test name
Test status
Simulation time 6465398191 ps
CPU time 75.58 seconds
Started Jul 03 04:26:02 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 198076 kb
Host smart-50fc09ba-90af-43fb-91e1-19f61582f7ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367452760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2367452760
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.3068671062
Short name T68
Test name
Test status
Simulation time 526321674363 ps
CPU time 2772.02 seconds
Started Jul 03 04:25:27 PM PDT 24
Finished Jul 03 05:11:41 PM PDT 24
Peak memory 198856 kb
Host smart-83d22ffd-2a7e-461f-80f1-eb5f3fb2abd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3068671062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.3068671062
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3021619074
Short name T249
Test name
Test status
Simulation time 119156290 ps
CPU time 0.56 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 194652 kb
Host smart-3340a33b-7e6b-4f42-afdb-543eb688ce10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021619074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3021619074
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1639144574
Short name T655
Test name
Test status
Simulation time 68985901 ps
CPU time 0.79 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 195916 kb
Host smart-c0a6019a-ba9a-40bb-a39d-9187addcd26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639144574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1639144574
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3945246794
Short name T164
Test name
Test status
Simulation time 445980740 ps
CPU time 14.9 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:42 PM PDT 24
Peak memory 198428 kb
Host smart-13b18aaf-1308-487b-9c65-92571e220d56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945246794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3945246794
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2373769020
Short name T312
Test name
Test status
Simulation time 108845640 ps
CPU time 0.9 seconds
Started Jul 03 04:25:29 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 196636 kb
Host smart-200f2329-2729-4f23-ad4b-d8fa42c6f6fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373769020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2373769020
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.627659341
Short name T668
Test name
Test status
Simulation time 491750461 ps
CPU time 0.92 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 196740 kb
Host smart-327d633e-fcc1-494f-a25b-10902fe876d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627659341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.627659341
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3521315858
Short name T306
Test name
Test status
Simulation time 60991862 ps
CPU time 2.32 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:28 PM PDT 24
Peak memory 198572 kb
Host smart-b9463497-771c-48ae-9410-fb0c35a87c90
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521315858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3521315858
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2839996780
Short name T294
Test name
Test status
Simulation time 507756445 ps
CPU time 2.77 seconds
Started Jul 03 04:25:46 PM PDT 24
Finished Jul 03 04:25:49 PM PDT 24
Peak memory 198644 kb
Host smart-c81dc630-bc61-4f37-9853-69597c7716b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839996780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2839996780
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2485432500
Short name T307
Test name
Test status
Simulation time 21406680 ps
CPU time 0.79 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 197032 kb
Host smart-ff68f7e6-ad61-425a-b210-2752e07b20f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485432500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2485432500
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3669358020
Short name T507
Test name
Test status
Simulation time 84010687 ps
CPU time 0.77 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 196868 kb
Host smart-d1feb6e0-9fb8-484b-997f-665de4d92aa8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669358020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3669358020
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.26251183
Short name T612
Test name
Test status
Simulation time 48461924 ps
CPU time 1.63 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 198404 kb
Host smart-732380c9-3c1c-4c6a-a2e6-a25d2e083f20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26251183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rando
m_long_reg_writes_reg_reads.26251183
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.459449453
Short name T495
Test name
Test status
Simulation time 50251924 ps
CPU time 1.28 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 197344 kb
Host smart-6f8c8ec1-4df8-4a12-bdf2-7708b39c28af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459449453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.459449453
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.586908196
Short name T431
Test name
Test status
Simulation time 32464757 ps
CPU time 0.73 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 195716 kb
Host smart-06367aac-8086-4c04-94b1-fe94edf7007e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586908196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.586908196
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3662912013
Short name T141
Test name
Test status
Simulation time 27763717253 ps
CPU time 173.34 seconds
Started Jul 03 04:25:23 PM PDT 24
Finished Jul 03 04:28:23 PM PDT 24
Peak memory 198656 kb
Host smart-b703aed5-d487-46ed-9892-87ddba50a247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662912013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3662912013
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.446181495
Short name T355
Test name
Test status
Simulation time 47026772 ps
CPU time 0.56 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:30 PM PDT 24
Peak memory 194640 kb
Host smart-1696f4c2-d1e1-489a-8904-932331ec3ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446181495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.446181495
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3452485585
Short name T503
Test name
Test status
Simulation time 67570169 ps
CPU time 0.81 seconds
Started Jul 03 04:25:24 PM PDT 24
Finished Jul 03 04:25:26 PM PDT 24
Peak memory 197020 kb
Host smart-ba77114b-3776-4da6-af62-644456ac656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452485585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3452485585
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.470003748
Short name T551
Test name
Test status
Simulation time 2431496457 ps
CPU time 17.03 seconds
Started Jul 03 04:25:25 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 196400 kb
Host smart-624aee4a-81f9-4b3e-9b1a-129b94feb43e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470003748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.470003748
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3118707535
Short name T681
Test name
Test status
Simulation time 41802647 ps
CPU time 0.68 seconds
Started Jul 03 04:26:08 PM PDT 24
Finished Jul 03 04:26:09 PM PDT 24
Peak memory 195272 kb
Host smart-02d6d3d7-77b4-4168-97a2-cb273410fa5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118707535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3118707535
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.281923024
Short name T242
Test name
Test status
Simulation time 442675001 ps
CPU time 1.32 seconds
Started Jul 03 04:25:28 PM PDT 24
Finished Jul 03 04:25:31 PM PDT 24
Peak memory 197752 kb
Host smart-78504115-f440-4802-9bc0-5c9c8473a51c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281923024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.281923024
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2283948222
Short name T491
Test name
Test status
Simulation time 573767253 ps
CPU time 3.16 seconds
Started Jul 03 04:25:57 PM PDT 24
Finished Jul 03 04:26:01 PM PDT 24
Peak memory 198624 kb
Host smart-cbc2d004-41a3-44a1-b829-2d2781f64ac5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283948222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2283948222
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.4094362016
Short name T460
Test name
Test status
Simulation time 110943706 ps
CPU time 2.34 seconds
Started Jul 03 04:27:07 PM PDT 24
Finished Jul 03 04:27:10 PM PDT 24
Peak memory 197528 kb
Host smart-05e308b7-a3c5-4f8c-87e8-1b053bef77bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094362016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
4094362016
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2912393717
Short name T186
Test name
Test status
Simulation time 161130115 ps
CPU time 1.07 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 198504 kb
Host smart-e2e7a311-8604-4dcd-a637-53282a59629f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912393717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2912393717
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3975107773
Short name T273
Test name
Test status
Simulation time 65450024 ps
CPU time 0.61 seconds
Started Jul 03 04:25:50 PM PDT 24
Finished Jul 03 04:25:51 PM PDT 24
Peak memory 195388 kb
Host smart-c91dd8b7-b06d-4166-b4f0-7bbadb8d80dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975107773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3975107773
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2612782557
Short name T334
Test name
Test status
Simulation time 223239833 ps
CPU time 3.62 seconds
Started Jul 03 04:25:50 PM PDT 24
Finished Jul 03 04:25:55 PM PDT 24
Peak memory 198520 kb
Host smart-86c0d36c-107e-4df0-becf-cdf62ea3a860
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612782557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2612782557
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.727554911
Short name T318
Test name
Test status
Simulation time 226984389 ps
CPU time 0.87 seconds
Started Jul 03 04:25:42 PM PDT 24
Finished Jul 03 04:25:44 PM PDT 24
Peak memory 196872 kb
Host smart-3c1b4a0e-ab2d-4d4b-a2ee-63ff68afd904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727554911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.727554911
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.213049803
Short name T684
Test name
Test status
Simulation time 55167270 ps
CPU time 1.38 seconds
Started Jul 03 04:25:41 PM PDT 24
Finished Jul 03 04:25:43 PM PDT 24
Peak memory 198664 kb
Host smart-47a39af0-c44c-4df3-9761-782d4e466e6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213049803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.213049803
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3923935097
Short name T613
Test name
Test status
Simulation time 20478693580 ps
CPU time 156.54 seconds
Started Jul 03 04:25:26 PM PDT 24
Finished Jul 03 04:28:04 PM PDT 24
Peak memory 198652 kb
Host smart-8422db94-61a1-4087-8d7f-93e0992ba23b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923935097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3923935097
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1435095726
Short name T891
Test name
Test status
Simulation time 30580120 ps
CPU time 0.93 seconds
Started Jul 03 04:47:30 PM PDT 24
Finished Jul 03 04:47:32 PM PDT 24
Peak memory 196592 kb
Host smart-c3760767-72e2-4dd8-9f5e-d62c71c407bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1435095726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1435095726
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.67263139
Short name T908
Test name
Test status
Simulation time 27917735 ps
CPU time 0.86 seconds
Started Jul 03 04:47:30 PM PDT 24
Finished Jul 03 04:47:31 PM PDT 24
Peak memory 196984 kb
Host smart-4800bae6-f832-4dd3-b147-1f3336acebc8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67263139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.67263139
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3427626369
Short name T915
Test name
Test status
Simulation time 127863201 ps
CPU time 1.19 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:33 PM PDT 24
Peak memory 198388 kb
Host smart-58dedb4a-3e60-4140-a53a-433c73c8f571
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3427626369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3427626369
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3576416810
Short name T884
Test name
Test status
Simulation time 76986044 ps
CPU time 1.48 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 198372 kb
Host smart-adee1f27-d44d-4eb9-bde7-29d0ae597449
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576416810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3576416810
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1038943121
Short name T922
Test name
Test status
Simulation time 277610394 ps
CPU time 1.07 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 196852 kb
Host smart-fc409aca-c01a-4acc-830e-41d30cc86a37
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1038943121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1038943121
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3361906110
Short name T916
Test name
Test status
Simulation time 45087945 ps
CPU time 1.22 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:36 PM PDT 24
Peak memory 196904 kb
Host smart-6a6256a8-48c7-4fc3-82c3-c32dc8449e5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361906110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3361906110
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.208600225
Short name T860
Test name
Test status
Simulation time 81006617 ps
CPU time 0.82 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 195540 kb
Host smart-031dae0d-0b3d-4621-a567-207fb8674d6c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=208600225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.208600225
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2267092974
Short name T901
Test name
Test status
Simulation time 98221368 ps
CPU time 0.94 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 198264 kb
Host smart-a817612b-2f6b-45b9-88ba-10bb1d7331aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267092974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2267092974
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1250876077
Short name T868
Test name
Test status
Simulation time 57897109 ps
CPU time 1.17 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:36 PM PDT 24
Peak memory 198400 kb
Host smart-1ed273ce-6c99-48ce-9e61-907dfe46f879
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1250876077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1250876077
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1244465806
Short name T893
Test name
Test status
Simulation time 179539716 ps
CPU time 0.94 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 197036 kb
Host smart-f8ad7965-067b-421b-aca7-ea881bf3867a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244465806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1244465806
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3363050639
Short name T897
Test name
Test status
Simulation time 31952764 ps
CPU time 1 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:34 PM PDT 24
Peak memory 196972 kb
Host smart-f29d6eab-fe12-4078-8403-90f2e76332c4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3363050639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3363050639
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.344049779
Short name T872
Test name
Test status
Simulation time 156234916 ps
CPU time 1.37 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 196928 kb
Host smart-88c433be-1550-4449-be52-91bfd1924fa9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344049779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.344049779
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1975891391
Short name T855
Test name
Test status
Simulation time 139992205 ps
CPU time 1.02 seconds
Started Jul 03 04:47:36 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 196824 kb
Host smart-54bc4c26-15ee-4f23-8904-a7c379c75a18
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1975891391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1975891391
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3758880548
Short name T941
Test name
Test status
Simulation time 159099000 ps
CPU time 1.12 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 197132 kb
Host smart-2516d8d5-f7ad-4956-a843-6c1c3923095f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758880548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3758880548
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3917474262
Short name T852
Test name
Test status
Simulation time 82710353 ps
CPU time 0.86 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 196600 kb
Host smart-1057775a-64fb-4307-b38b-5e5e1de5713a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3917474262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3917474262
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1493989188
Short name T861
Test name
Test status
Simulation time 79540081 ps
CPU time 1.18 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 196800 kb
Host smart-dd15c891-c6a7-47f3-8df8-ce3d1a0770bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493989188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1493989188
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3952057599
Short name T886
Test name
Test status
Simulation time 105019230 ps
CPU time 0.81 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 195724 kb
Host smart-3ff6d209-aa97-4604-a29a-bcd23243a31f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3952057599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3952057599
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037842125
Short name T947
Test name
Test status
Simulation time 53086555 ps
CPU time 1.48 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:36 PM PDT 24
Peak memory 197060 kb
Host smart-0da8e71d-e5f2-417b-be81-5126aad3dcfe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037842125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3037842125
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1028777448
Short name T904
Test name
Test status
Simulation time 133703844 ps
CPU time 1.18 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 197068 kb
Host smart-44048dde-18b6-44c8-94d5-cdb2d0f8593d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1028777448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1028777448
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1495010129
Short name T928
Test name
Test status
Simulation time 492189782 ps
CPU time 1.56 seconds
Started Jul 03 04:47:38 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 198384 kb
Host smart-56108fa3-164d-48b8-8b3c-dbb2791ededd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495010129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1495010129
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2837865692
Short name T944
Test name
Test status
Simulation time 239663977 ps
CPU time 1.4 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 196988 kb
Host smart-c7893adb-5e70-4e21-a24a-b2ed4c6bbe36
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2837865692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2837865692
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1527131239
Short name T912
Test name
Test status
Simulation time 91189160 ps
CPU time 1.38 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 198424 kb
Host smart-490a69c1-079c-4fed-aa2e-2ba2471f34eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527131239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1527131239
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.849019305
Short name T865
Test name
Test status
Simulation time 21478453 ps
CPU time 0.82 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:36 PM PDT 24
Peak memory 195756 kb
Host smart-a705df31-91ca-498c-8e8a-66fb6b7409ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=849019305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.849019305
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.653735941
Short name T869
Test name
Test status
Simulation time 76488910 ps
CPU time 1.22 seconds
Started Jul 03 04:47:36 PM PDT 24
Finished Jul 03 04:47:38 PM PDT 24
Peak memory 198320 kb
Host smart-6ffcd2c6-4c53-4977-a4c4-22f4c63996d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653735941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.653735941
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3800809270
Short name T900
Test name
Test status
Simulation time 239871925 ps
CPU time 1.02 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:35 PM PDT 24
Peak memory 196012 kb
Host smart-f577648e-7296-4967-bf45-2dda5d076955
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3800809270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3800809270
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3798522038
Short name T870
Test name
Test status
Simulation time 108579209 ps
CPU time 1.57 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 197296 kb
Host smart-86dd616e-9fa2-4aee-b2bc-b48ddd54cdcb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798522038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3798522038
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2618113675
Short name T856
Test name
Test status
Simulation time 39151914 ps
CPU time 0.82 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:38 PM PDT 24
Peak memory 195780 kb
Host smart-7b2339f5-e5b6-4502-b689-e5970764bf63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2618113675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2618113675
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2722764839
Short name T918
Test name
Test status
Simulation time 142475814 ps
CPU time 1.1 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 196040 kb
Host smart-593428d4-9e80-4b0c-9231-1f9e7f1665bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722764839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2722764839
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2942684147
Short name T879
Test name
Test status
Simulation time 77928998 ps
CPU time 0.82 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:36 PM PDT 24
Peak memory 196992 kb
Host smart-992fc630-6a3b-4e72-a619-a872b7e692e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2942684147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2942684147
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2091249700
Short name T946
Test name
Test status
Simulation time 143174715 ps
CPU time 1.35 seconds
Started Jul 03 04:47:36 PM PDT 24
Finished Jul 03 04:47:38 PM PDT 24
Peak memory 196972 kb
Host smart-6c2613f8-73fb-47e4-b1bd-f14164a21bc8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091249700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2091249700
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1081539653
Short name T882
Test name
Test status
Simulation time 56220375 ps
CPU time 1.15 seconds
Started Jul 03 04:47:39 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 197916 kb
Host smart-4ec9af3c-ba73-4e79-ba7b-bf1efc2563fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1081539653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1081539653
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3675346783
Short name T871
Test name
Test status
Simulation time 163320638 ps
CPU time 0.96 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 197424 kb
Host smart-7bc83700-bb8c-4832-810e-0e788de923fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675346783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3675346783
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1405367664
Short name T930
Test name
Test status
Simulation time 112261861 ps
CPU time 1.11 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 198420 kb
Host smart-42af05ab-dc5c-49da-8766-5361cff19212
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1405367664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1405367664
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4107957735
Short name T905
Test name
Test status
Simulation time 93632829 ps
CPU time 0.83 seconds
Started Jul 03 04:47:38 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 195900 kb
Host smart-d8f43291-519a-4323-8e0f-882c77710f8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107957735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4107957735
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2268904992
Short name T907
Test name
Test status
Simulation time 73720173 ps
CPU time 1.21 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 198340 kb
Host smart-9682ab81-f2a8-4e00-8634-287f9475e3ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2268904992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2268904992
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224542176
Short name T924
Test name
Test status
Simulation time 70575633 ps
CPU time 1.29 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 196752 kb
Host smart-bc5f7576-1394-49cd-8015-b426f41b7d10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224542176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4224542176
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1592875393
Short name T854
Test name
Test status
Simulation time 35074949 ps
CPU time 1.12 seconds
Started Jul 03 04:47:47 PM PDT 24
Finished Jul 03 04:47:48 PM PDT 24
Peak memory 196944 kb
Host smart-269ff55e-1a01-472d-8dd9-9cb12a2d0dc4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1592875393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1592875393
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2507621118
Short name T863
Test name
Test status
Simulation time 70562028 ps
CPU time 1.44 seconds
Started Jul 03 04:47:39 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 197316 kb
Host smart-95157895-9c74-44bf-b17f-8dc6c26c0420
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507621118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2507621118
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.998817846
Short name T933
Test name
Test status
Simulation time 212816520 ps
CPU time 1.17 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 197036 kb
Host smart-8224c983-2c70-466d-a0f8-2c46308e3527
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=998817846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.998817846
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1179329231
Short name T903
Test name
Test status
Simulation time 109200197 ps
CPU time 0.89 seconds
Started Jul 03 04:47:39 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 195628 kb
Host smart-1b9546f3-a13a-4fd3-aec2-5cd7c15f74d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179329231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1179329231
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.458751399
Short name T896
Test name
Test status
Simulation time 179944246 ps
CPU time 0.97 seconds
Started Jul 03 04:47:41 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 198340 kb
Host smart-058467e3-081b-4aeb-877b-0ecdb6550e88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=458751399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.458751399
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1392364163
Short name T917
Test name
Test status
Simulation time 41393703 ps
CPU time 1.38 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 197452 kb
Host smart-4b5591ef-2391-4ccd-a4c1-81d83a040ab6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392364163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1392364163
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3469623764
Short name T919
Test name
Test status
Simulation time 86401653 ps
CPU time 1.28 seconds
Started Jul 03 04:47:41 PM PDT 24
Finished Jul 03 04:47:43 PM PDT 24
Peak memory 196940 kb
Host smart-3fa19ccd-aee8-404c-875d-79676521cf22
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3469623764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3469623764
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1985732698
Short name T931
Test name
Test status
Simulation time 70590907 ps
CPU time 1.03 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 196080 kb
Host smart-e13cd7fa-6f7b-4dd8-b675-546186855d6a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985732698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1985732698
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1700535789
Short name T932
Test name
Test status
Simulation time 62671124 ps
CPU time 1.32 seconds
Started Jul 03 04:47:41 PM PDT 24
Finished Jul 03 04:47:43 PM PDT 24
Peak memory 198384 kb
Host smart-54a57483-9ecc-4c31-b91e-afef6a6605c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1700535789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1700535789
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3438976450
Short name T939
Test name
Test status
Simulation time 164113656 ps
CPU time 1.03 seconds
Started Jul 03 04:47:39 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 196076 kb
Host smart-43698043-4f5e-44db-b8db-4be768ed7cb1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438976450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3438976450
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3045355745
Short name T874
Test name
Test status
Simulation time 361268854 ps
CPU time 1.44 seconds
Started Jul 03 04:47:38 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 197156 kb
Host smart-6c09fa13-b17a-4c70-a7fb-dd3ff9930c87
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3045355745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3045355745
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3320130470
Short name T913
Test name
Test status
Simulation time 180769596 ps
CPU time 0.91 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 198180 kb
Host smart-aaff1730-adb2-49c3-bc8e-991e371a76ad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320130470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3320130470
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2978454246
Short name T850
Test name
Test status
Simulation time 42373527 ps
CPU time 1.35 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 197060 kb
Host smart-f9c029cf-ae88-47d6-88ee-afb7222f6160
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2978454246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2978454246
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4252704791
Short name T934
Test name
Test status
Simulation time 65091313 ps
CPU time 0.99 seconds
Started Jul 03 04:47:42 PM PDT 24
Finished Jul 03 04:47:43 PM PDT 24
Peak memory 195936 kb
Host smart-a540d8f0-d184-488c-89d1-0367b1898ac2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252704791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4252704791
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2288706127
Short name T925
Test name
Test status
Simulation time 38080864 ps
CPU time 1.09 seconds
Started Jul 03 04:47:42 PM PDT 24
Finished Jul 03 04:47:44 PM PDT 24
Peak memory 196276 kb
Host smart-74c9e5c6-6353-40d3-bdd0-06f4e62d5536
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2288706127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2288706127
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1737356886
Short name T920
Test name
Test status
Simulation time 65669009 ps
CPU time 1.11 seconds
Started Jul 03 04:47:47 PM PDT 24
Finished Jul 03 04:47:48 PM PDT 24
Peak memory 197000 kb
Host smart-8b983d4f-3b9f-4ce1-80df-77a866d03063
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737356886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1737356886
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3934683991
Short name T935
Test name
Test status
Simulation time 37517841 ps
CPU time 1.09 seconds
Started Jul 03 04:47:39 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 198368 kb
Host smart-e0940b5d-7fa3-493c-9929-2d29fcc78c9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3934683991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3934683991
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.715928086
Short name T878
Test name
Test status
Simulation time 349933030 ps
CPU time 1.53 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 197048 kb
Host smart-9b0eabfb-7686-46f9-b3bc-c25acc800c3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715928086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.715928086
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3869996261
Short name T857
Test name
Test status
Simulation time 270711581 ps
CPU time 1.31 seconds
Started Jul 03 04:47:47 PM PDT 24
Finished Jul 03 04:47:49 PM PDT 24
Peak memory 196940 kb
Host smart-b2b0f013-bf93-4ce7-b1e6-0836dbe9f39e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3869996261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3869996261
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3242720022
Short name T937
Test name
Test status
Simulation time 36756862 ps
CPU time 1.19 seconds
Started Jul 03 04:47:39 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 196944 kb
Host smart-2236ba12-0a5f-4516-91fb-2c2ee8ad1688
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242720022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3242720022
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4240764249
Short name T910
Test name
Test status
Simulation time 32273766 ps
CPU time 0.9 seconds
Started Jul 03 04:47:42 PM PDT 24
Finished Jul 03 04:47:43 PM PDT 24
Peak memory 197064 kb
Host smart-ad118e77-28c9-4024-8e20-b495313c106d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4240764249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4240764249
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.819871227
Short name T888
Test name
Test status
Simulation time 298849737 ps
CPU time 1.2 seconds
Started Jul 03 04:47:41 PM PDT 24
Finished Jul 03 04:47:43 PM PDT 24
Peak memory 196048 kb
Host smart-40fa8ffb-db39-446e-a525-81724526f847
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819871227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.819871227
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2344611867
Short name T866
Test name
Test status
Simulation time 40142325 ps
CPU time 1.01 seconds
Started Jul 03 04:47:42 PM PDT 24
Finished Jul 03 04:47:43 PM PDT 24
Peak memory 196160 kb
Host smart-05e8a702-137c-46e5-a068-0165dd86ffef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2344611867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2344611867
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3856244381
Short name T889
Test name
Test status
Simulation time 888106708 ps
CPU time 1.25 seconds
Started Jul 03 04:47:41 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 196036 kb
Host smart-cab9954f-30a5-493d-904d-6428709cb458
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856244381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3856244381
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2799306178
Short name T875
Test name
Test status
Simulation time 265597889 ps
CPU time 1.46 seconds
Started Jul 03 04:47:43 PM PDT 24
Finished Jul 03 04:47:45 PM PDT 24
Peak memory 198352 kb
Host smart-d018f49b-590a-49fd-877c-67a745e164ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2799306178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2799306178
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.65998736
Short name T858
Test name
Test status
Simulation time 55824371 ps
CPU time 0.98 seconds
Started Jul 03 04:47:45 PM PDT 24
Finished Jul 03 04:47:47 PM PDT 24
Peak memory 195944 kb
Host smart-19b63ac5-7006-48c6-896d-7ffe76cb3123
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65998736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.65998736
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1021708590
Short name T885
Test name
Test status
Simulation time 241178005 ps
CPU time 1.24 seconds
Started Jul 03 04:47:42 PM PDT 24
Finished Jul 03 04:47:44 PM PDT 24
Peak memory 197052 kb
Host smart-60596322-8304-44f5-9456-85ff84d00949
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1021708590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1021708590
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4072313498
Short name T859
Test name
Test status
Simulation time 250054368 ps
CPU time 1.12 seconds
Started Jul 03 04:47:46 PM PDT 24
Finished Jul 03 04:47:48 PM PDT 24
Peak memory 196964 kb
Host smart-873818ef-91aa-48cf-9604-a6eaeb35d2be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072313498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4072313498
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1663657965
Short name T914
Test name
Test status
Simulation time 59985657 ps
CPU time 1.48 seconds
Started Jul 03 04:47:44 PM PDT 24
Finished Jul 03 04:47:46 PM PDT 24
Peak memory 197000 kb
Host smart-a8ed210b-376b-40aa-9517-9f16586bff7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1663657965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1663657965
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1461401325
Short name T906
Test name
Test status
Simulation time 82424911 ps
CPU time 0.94 seconds
Started Jul 03 04:47:43 PM PDT 24
Finished Jul 03 04:47:44 PM PDT 24
Peak memory 196936 kb
Host smart-a8fcebb5-ba0f-4401-b8dc-60c03b31bdd1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461401325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1461401325
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3826387915
Short name T940
Test name
Test status
Simulation time 37952911 ps
CPU time 1.06 seconds
Started Jul 03 04:47:43 PM PDT 24
Finished Jul 03 04:47:44 PM PDT 24
Peak memory 195836 kb
Host smart-55fc0345-0724-4a92-95f3-dfe7b6911b77
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3826387915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3826387915
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4230984205
Short name T883
Test name
Test status
Simulation time 56480308 ps
CPU time 0.88 seconds
Started Jul 03 04:47:46 PM PDT 24
Finished Jul 03 04:47:47 PM PDT 24
Peak memory 195744 kb
Host smart-43fe3d0a-5c09-4a06-b57e-e2fce44106e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230984205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4230984205
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1487807618
Short name T927
Test name
Test status
Simulation time 127362157 ps
CPU time 0.84 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:36 PM PDT 24
Peak memory 195772 kb
Host smart-d09465a0-5c4c-4a63-8441-59ef1cb88343
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1487807618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1487807618
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1408644289
Short name T867
Test name
Test status
Simulation time 54232079 ps
CPU time 1.12 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:36 PM PDT 24
Peak memory 196324 kb
Host smart-f462e7c1-13d7-4e04-a64b-cc6302ac4236
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408644289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1408644289
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2896798913
Short name T923
Test name
Test status
Simulation time 31856908 ps
CPU time 0.81 seconds
Started Jul 03 04:47:44 PM PDT 24
Finished Jul 03 04:47:46 PM PDT 24
Peak memory 196472 kb
Host smart-17f15ecf-0f67-4e9b-b871-593d4bf99837
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2896798913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2896798913
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2209298356
Short name T936
Test name
Test status
Simulation time 150120293 ps
CPU time 0.89 seconds
Started Jul 03 04:47:43 PM PDT 24
Finished Jul 03 04:47:45 PM PDT 24
Peak memory 196504 kb
Host smart-74fb0447-4e2e-4185-a4e7-ae32d1425a21
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209298356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2209298356
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3070311140
Short name T943
Test name
Test status
Simulation time 114190844 ps
CPU time 0.93 seconds
Started Jul 03 04:47:43 PM PDT 24
Finished Jul 03 04:47:45 PM PDT 24
Peak memory 197656 kb
Host smart-1577dc6e-d2fd-46c2-9ce6-c244b2c6db9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3070311140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3070311140
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1350816781
Short name T862
Test name
Test status
Simulation time 165112141 ps
CPU time 0.9 seconds
Started Jul 03 04:47:45 PM PDT 24
Finished Jul 03 04:47:46 PM PDT 24
Peak memory 195996 kb
Host smart-7e3ec95a-7d3b-4d8d-9191-e4a749ec3d33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350816781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1350816781
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4235434885
Short name T877
Test name
Test status
Simulation time 151139953 ps
CPU time 1.42 seconds
Started Jul 03 04:47:43 PM PDT 24
Finished Jul 03 04:47:45 PM PDT 24
Peak memory 198396 kb
Host smart-683eee92-3a99-4e00-8770-c5c0003175c9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4235434885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4235434885
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3460183895
Short name T926
Test name
Test status
Simulation time 37624117 ps
CPU time 1.08 seconds
Started Jul 03 04:47:43 PM PDT 24
Finished Jul 03 04:47:45 PM PDT 24
Peak memory 198348 kb
Host smart-15f0bcc2-6913-4a9f-b252-9fc64c8703bf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460183895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3460183895
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2083128958
Short name T851
Test name
Test status
Simulation time 272938346 ps
CPU time 0.95 seconds
Started Jul 03 04:47:51 PM PDT 24
Finished Jul 03 04:47:52 PM PDT 24
Peak memory 196952 kb
Host smart-217f109b-60d0-4b5b-ae17-7b8d17aaa189
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2083128958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2083128958
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1142689958
Short name T890
Test name
Test status
Simulation time 102720264 ps
CPU time 0.75 seconds
Started Jul 03 04:47:45 PM PDT 24
Finished Jul 03 04:47:46 PM PDT 24
Peak memory 196404 kb
Host smart-af28babc-4d18-4c6d-ab69-8b4732200b6d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142689958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1142689958
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.956978461
Short name T945
Test name
Test status
Simulation time 33319688 ps
CPU time 0.87 seconds
Started Jul 03 04:47:44 PM PDT 24
Finished Jul 03 04:47:46 PM PDT 24
Peak memory 195888 kb
Host smart-1b2a1b25-38c9-4590-a2a8-d730d3b49590
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=956978461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.956978461
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3053987807
Short name T938
Test name
Test status
Simulation time 320253906 ps
CPU time 1.33 seconds
Started Jul 03 04:47:45 PM PDT 24
Finished Jul 03 04:47:47 PM PDT 24
Peak memory 197088 kb
Host smart-ede79b14-7824-4389-b901-96e5da4da1fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053987807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3053987807
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3421765662
Short name T929
Test name
Test status
Simulation time 58864008 ps
CPU time 0.88 seconds
Started Jul 03 04:47:44 PM PDT 24
Finished Jul 03 04:47:45 PM PDT 24
Peak memory 196912 kb
Host smart-f003f99f-f024-4ce4-8559-f37b4ace6ede
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3421765662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3421765662
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2906425421
Short name T921
Test name
Test status
Simulation time 66721276 ps
CPU time 1.02 seconds
Started Jul 03 04:47:43 PM PDT 24
Finished Jul 03 04:47:44 PM PDT 24
Peak memory 196996 kb
Host smart-d48db590-bccf-423c-b3f8-9968b261b280
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906425421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2906425421
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2186970808
Short name T898
Test name
Test status
Simulation time 54458830 ps
CPU time 1.14 seconds
Started Jul 03 04:47:45 PM PDT 24
Finished Jul 03 04:47:46 PM PDT 24
Peak memory 198424 kb
Host smart-d9a9390b-81e0-4b1b-a1f9-f8d510329d58
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2186970808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2186970808
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.153147740
Short name T909
Test name
Test status
Simulation time 34876635 ps
CPU time 0.94 seconds
Started Jul 03 04:47:46 PM PDT 24
Finished Jul 03 04:47:47 PM PDT 24
Peak memory 196032 kb
Host smart-5e52816a-48b4-45d6-b5fe-83aabc3ba834
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153147740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.153147740
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1105964147
Short name T864
Test name
Test status
Simulation time 222080339 ps
CPU time 1.08 seconds
Started Jul 03 04:47:48 PM PDT 24
Finished Jul 03 04:47:49 PM PDT 24
Peak memory 196960 kb
Host smart-7e006046-2cf6-4a3d-a6af-bfbe08f62f6a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1105964147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1105964147
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.463738395
Short name T894
Test name
Test status
Simulation time 209101951 ps
CPU time 1.36 seconds
Started Jul 03 04:47:47 PM PDT 24
Finished Jul 03 04:47:48 PM PDT 24
Peak memory 196988 kb
Host smart-7edbb952-6053-4725-8b9c-e5c3792dd184
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463738395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.463738395
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.793772358
Short name T880
Test name
Test status
Simulation time 55644350 ps
CPU time 0.76 seconds
Started Jul 03 04:47:48 PM PDT 24
Finished Jul 03 04:47:50 PM PDT 24
Peak memory 196516 kb
Host smart-2af0a99f-ea41-4bb3-b528-bd66d86ef5fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=793772358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.793772358
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1589694296
Short name T899
Test name
Test status
Simulation time 119782755 ps
CPU time 1.27 seconds
Started Jul 03 04:47:49 PM PDT 24
Finished Jul 03 04:47:50 PM PDT 24
Peak memory 197224 kb
Host smart-f948c53d-d32d-4914-8103-e00816e4074b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589694296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1589694296
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2667075941
Short name T887
Test name
Test status
Simulation time 255973215 ps
CPU time 1.19 seconds
Started Jul 03 04:47:48 PM PDT 24
Finished Jul 03 04:47:50 PM PDT 24
Peak memory 198440 kb
Host smart-20fd5881-ed98-4a90-bc07-c272b1864fb6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2667075941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2667075941
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1236530601
Short name T892
Test name
Test status
Simulation time 76629044 ps
CPU time 0.85 seconds
Started Jul 03 04:47:48 PM PDT 24
Finished Jul 03 04:47:49 PM PDT 24
Peak memory 195736 kb
Host smart-dccd7e9c-43a7-4adf-b6b7-059a8682aa5e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236530601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1236530601
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1473751263
Short name T849
Test name
Test status
Simulation time 255915047 ps
CPU time 1.1 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 197000 kb
Host smart-718947d7-5c52-48f3-8dc7-31bb3368931f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1473751263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1473751263
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4099663962
Short name T873
Test name
Test status
Simulation time 30229773 ps
CPU time 0.91 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 196856 kb
Host smart-b75eae89-a419-4f83-86ee-74ae2714409b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099663962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4099663962
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2104165014
Short name T881
Test name
Test status
Simulation time 156473775 ps
CPU time 1.35 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 197216 kb
Host smart-0ceb1209-fb5e-4b94-9838-84106f216804
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2104165014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2104165014
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2946645129
Short name T895
Test name
Test status
Simulation time 199488396 ps
CPU time 1.28 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 197024 kb
Host smart-abfbd01a-165f-486e-91f4-069a239a4487
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946645129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2946645129
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3146098679
Short name T942
Test name
Test status
Simulation time 164102411 ps
CPU time 1.03 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 197856 kb
Host smart-644d1ee4-7f71-4fe0-bc16-93369f794a64
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3146098679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3146098679
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2979658100
Short name T902
Test name
Test status
Simulation time 27690216 ps
CPU time 0.95 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 196988 kb
Host smart-e580eeb1-3c83-4c98-a453-d9cb2e16b9fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979658100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2979658100
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1102327845
Short name T911
Test name
Test status
Simulation time 30071772 ps
CPU time 0.89 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:35 PM PDT 24
Peak memory 196796 kb
Host smart-b64e6ec8-84dd-4df5-a3a7-8a5dd7456ebf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1102327845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1102327845
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.905495087
Short name T876
Test name
Test status
Simulation time 89994761 ps
CPU time 1.13 seconds
Started Jul 03 04:47:35 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 197012 kb
Host smart-409d97aa-5f1f-49c9-ad7c-578a286742fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905495087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.905495087
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.293156418
Short name T853
Test name
Test status
Simulation time 158212167 ps
CPU time 1.3 seconds
Started Jul 03 04:47:39 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 196864 kb
Host smart-86c59c0a-b5df-4895-a63a-8cdb1617e4b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=293156418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.293156418
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1216344987
Short name T948
Test name
Test status
Simulation time 51685799 ps
CPU time 1.11 seconds
Started Jul 03 04:47:40 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 196844 kb
Host smart-2616ab02-198e-4aac-bfe8-bf888938ef11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216344987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1216344987
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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