Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2092695 |
1 |
|
|
T31 |
115 |
|
T32 |
36 |
|
T33 |
30 |
| auto[1] |
1842346 |
1 |
|
|
T31 |
142 |
|
T32 |
6 |
|
T33 |
30 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2471882 |
1 |
|
|
T31 |
185 |
|
T32 |
38 |
|
T33 |
49 |
| auto[1] |
1463159 |
1 |
|
|
T31 |
72 |
|
T32 |
4 |
|
T33 |
11 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1357068 |
1 |
|
|
T31 |
80 |
|
T32 |
32 |
|
T33 |
29 |
| auto[0] |
auto[1] |
735627 |
1 |
|
|
T31 |
35 |
|
T32 |
4 |
|
T33 |
1 |
| auto[1] |
auto[0] |
1114814 |
1 |
|
|
T31 |
105 |
|
T32 |
6 |
|
T33 |
20 |
| auto[1] |
auto[1] |
727532 |
1 |
|
|
T31 |
37 |
|
T33 |
10 |
|
T1 |
15 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2095295 |
1 |
|
|
T31 |
132 |
|
T32 |
14 |
|
T33 |
36 |
| auto[1] |
1839746 |
1 |
|
|
T31 |
125 |
|
T32 |
28 |
|
T33 |
24 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2468594 |
1 |
|
|
T31 |
209 |
|
T32 |
40 |
|
T33 |
51 |
| auto[1] |
1466447 |
1 |
|
|
T31 |
48 |
|
T32 |
2 |
|
T33 |
9 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1357077 |
1 |
|
|
T31 |
105 |
|
T32 |
12 |
|
T33 |
35 |
| auto[0] |
auto[1] |
738218 |
1 |
|
|
T31 |
27 |
|
T32 |
2 |
|
T33 |
1 |
| auto[1] |
auto[0] |
1111517 |
1 |
|
|
T31 |
104 |
|
T32 |
28 |
|
T33 |
16 |
| auto[1] |
auto[1] |
728229 |
1 |
|
|
T31 |
21 |
|
T33 |
8 |
|
T1 |
11 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2096245 |
1 |
|
|
T31 |
140 |
|
T32 |
13 |
|
T33 |
27 |
| auto[1] |
1838796 |
1 |
|
|
T31 |
117 |
|
T32 |
29 |
|
T33 |
33 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2473222 |
1 |
|
|
T31 |
189 |
|
T32 |
39 |
|
T33 |
49 |
| auto[1] |
1461819 |
1 |
|
|
T31 |
68 |
|
T32 |
3 |
|
T33 |
11 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1361973 |
1 |
|
|
T31 |
100 |
|
T32 |
12 |
|
T33 |
27 |
| auto[0] |
auto[1] |
734272 |
1 |
|
|
T31 |
40 |
|
T32 |
1 |
|
T1 |
13 |
| auto[1] |
auto[0] |
1111249 |
1 |
|
|
T31 |
89 |
|
T32 |
27 |
|
T33 |
22 |
| auto[1] |
auto[1] |
727547 |
1 |
|
|
T31 |
28 |
|
T32 |
2 |
|
T33 |
11 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2096005 |
1 |
|
|
T31 |
139 |
|
T32 |
40 |
|
T33 |
43 |
| auto[1] |
1839036 |
1 |
|
|
T31 |
118 |
|
T32 |
2 |
|
T33 |
17 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2472283 |
1 |
|
|
T31 |
194 |
|
T32 |
37 |
|
T33 |
44 |
| auto[1] |
1462758 |
1 |
|
|
T31 |
63 |
|
T32 |
5 |
|
T33 |
16 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1359776 |
1 |
|
|
T31 |
110 |
|
T32 |
35 |
|
T33 |
35 |
| auto[0] |
auto[1] |
736229 |
1 |
|
|
T31 |
29 |
|
T32 |
5 |
|
T33 |
8 |
| auto[1] |
auto[0] |
1112507 |
1 |
|
|
T31 |
84 |
|
T32 |
2 |
|
T33 |
9 |
| auto[1] |
auto[1] |
726529 |
1 |
|
|
T31 |
34 |
|
T33 |
8 |
|
T1 |
10 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2096286 |
1 |
|
|
T31 |
150 |
|
T32 |
41 |
|
T33 |
36 |
| auto[1] |
1838755 |
1 |
|
|
T31 |
107 |
|
T32 |
1 |
|
T33 |
24 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2472801 |
1 |
|
|
T31 |
181 |
|
T32 |
39 |
|
T33 |
44 |
| auto[1] |
1462240 |
1 |
|
|
T31 |
76 |
|
T32 |
3 |
|
T33 |
16 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1361079 |
1 |
|
|
T31 |
110 |
|
T32 |
38 |
|
T33 |
36 |
| auto[0] |
auto[1] |
735207 |
1 |
|
|
T31 |
40 |
|
T32 |
3 |
|
T11 |
32 |
| auto[1] |
auto[0] |
1111722 |
1 |
|
|
T31 |
71 |
|
T32 |
1 |
|
T33 |
8 |
| auto[1] |
auto[1] |
727033 |
1 |
|
|
T31 |
36 |
|
T33 |
16 |
|
T1 |
4 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2095019 |
1 |
|
|
T31 |
148 |
|
T32 |
35 |
|
T33 |
46 |
| auto[1] |
1840022 |
1 |
|
|
T31 |
109 |
|
T32 |
7 |
|
T33 |
14 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2472503 |
1 |
|
|
T31 |
180 |
|
T32 |
40 |
|
T33 |
58 |
| auto[1] |
1462538 |
1 |
|
|
T31 |
77 |
|
T32 |
2 |
|
T33 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1361214 |
1 |
|
|
T31 |
101 |
|
T32 |
33 |
|
T33 |
46 |
| auto[0] |
auto[1] |
733805 |
1 |
|
|
T31 |
47 |
|
T32 |
2 |
|
T1 |
6 |
| auto[1] |
auto[0] |
1111289 |
1 |
|
|
T31 |
79 |
|
T32 |
7 |
|
T33 |
12 |
| auto[1] |
auto[1] |
728733 |
1 |
|
|
T31 |
30 |
|
T33 |
2 |
|
T1 |
6 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2097630 |
1 |
|
|
T31 |
138 |
|
T32 |
41 |
|
T33 |
40 |
| auto[1] |
1837411 |
1 |
|
|
T31 |
119 |
|
T32 |
1 |
|
T33 |
20 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2468859 |
1 |
|
|
T31 |
194 |
|
T32 |
36 |
|
T33 |
50 |
| auto[1] |
1466182 |
1 |
|
|
T31 |
63 |
|
T32 |
6 |
|
T33 |
10 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1359801 |
1 |
|
|
T31 |
103 |
|
T32 |
35 |
|
T33 |
37 |
| auto[0] |
auto[1] |
737829 |
1 |
|
|
T31 |
35 |
|
T32 |
6 |
|
T33 |
3 |
| auto[1] |
auto[0] |
1109058 |
1 |
|
|
T31 |
91 |
|
T32 |
1 |
|
T33 |
13 |
| auto[1] |
auto[1] |
728353 |
1 |
|
|
T31 |
28 |
|
T33 |
7 |
|
T1 |
15 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2102486 |
1 |
|
|
T31 |
117 |
|
T32 |
19 |
|
T33 |
42 |
| auto[1] |
1832555 |
1 |
|
|
T31 |
140 |
|
T32 |
23 |
|
T33 |
18 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2468292 |
1 |
|
|
T31 |
190 |
|
T32 |
37 |
|
T33 |
48 |
| auto[1] |
1466749 |
1 |
|
|
T31 |
67 |
|
T32 |
5 |
|
T33 |
12 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1363025 |
1 |
|
|
T31 |
83 |
|
T32 |
16 |
|
T33 |
32 |
| auto[0] |
auto[1] |
739461 |
1 |
|
|
T31 |
34 |
|
T32 |
3 |
|
T33 |
10 |
| auto[1] |
auto[0] |
1105267 |
1 |
|
|
T31 |
107 |
|
T32 |
21 |
|
T33 |
16 |
| auto[1] |
auto[1] |
727288 |
1 |
|
|
T31 |
33 |
|
T32 |
2 |
|
T33 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2099845 |
1 |
|
|
T31 |
125 |
|
T32 |
16 |
|
T33 |
38 |
| auto[1] |
1835196 |
1 |
|
|
T31 |
132 |
|
T32 |
26 |
|
T33 |
22 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2479454 |
1 |
|
|
T31 |
187 |
|
T32 |
35 |
|
T33 |
57 |
| auto[1] |
1455587 |
1 |
|
|
T31 |
70 |
|
T32 |
7 |
|
T33 |
3 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1366358 |
1 |
|
|
T31 |
83 |
|
T32 |
12 |
|
T33 |
38 |
| auto[0] |
auto[1] |
733487 |
1 |
|
|
T31 |
42 |
|
T32 |
4 |
|
T1 |
7 |
| auto[1] |
auto[0] |
1113096 |
1 |
|
|
T31 |
104 |
|
T32 |
23 |
|
T33 |
19 |
| auto[1] |
auto[1] |
722100 |
1 |
|
|
T31 |
28 |
|
T32 |
3 |
|
T33 |
3 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2100563 |
1 |
|
|
T31 |
117 |
|
T32 |
14 |
|
T33 |
45 |
| auto[1] |
1834478 |
1 |
|
|
T31 |
140 |
|
T32 |
28 |
|
T33 |
15 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2479768 |
1 |
|
|
T31 |
198 |
|
T32 |
36 |
|
T33 |
55 |
| auto[1] |
1455273 |
1 |
|
|
T31 |
59 |
|
T32 |
6 |
|
T33 |
5 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1365936 |
1 |
|
|
T31 |
84 |
|
T32 |
10 |
|
T33 |
45 |
| auto[0] |
auto[1] |
734627 |
1 |
|
|
T31 |
33 |
|
T32 |
4 |
|
T1 |
1 |
| auto[1] |
auto[0] |
1113832 |
1 |
|
|
T31 |
114 |
|
T32 |
26 |
|
T33 |
10 |
| auto[1] |
auto[1] |
720646 |
1 |
|
|
T31 |
26 |
|
T32 |
2 |
|
T33 |
5 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2098438 |
1 |
|
|
T31 |
120 |
|
T32 |
14 |
|
T33 |
44 |
| auto[1] |
1836603 |
1 |
|
|
T31 |
137 |
|
T32 |
28 |
|
T33 |
16 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2477333 |
1 |
|
|
T31 |
200 |
|
T32 |
38 |
|
T33 |
52 |
| auto[1] |
1457708 |
1 |
|
|
T31 |
57 |
|
T32 |
4 |
|
T33 |
8 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1365397 |
1 |
|
|
T31 |
92 |
|
T32 |
13 |
|
T33 |
39 |
| auto[0] |
auto[1] |
733041 |
1 |
|
|
T31 |
28 |
|
T32 |
1 |
|
T33 |
5 |
| auto[1] |
auto[0] |
1111936 |
1 |
|
|
T31 |
108 |
|
T32 |
25 |
|
T33 |
13 |
| auto[1] |
auto[1] |
724667 |
1 |
|
|
T31 |
29 |
|
T32 |
3 |
|
T33 |
3 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2096178 |
1 |
|
|
T31 |
128 |
|
T32 |
35 |
|
T33 |
40 |
| auto[1] |
1838863 |
1 |
|
|
T31 |
129 |
|
T32 |
7 |
|
T33 |
20 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2479769 |
1 |
|
|
T31 |
189 |
|
T32 |
39 |
|
T33 |
48 |
| auto[1] |
1455272 |
1 |
|
|
T31 |
68 |
|
T32 |
3 |
|
T33 |
12 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1365367 |
1 |
|
|
T31 |
95 |
|
T32 |
32 |
|
T33 |
33 |
| auto[0] |
auto[1] |
730811 |
1 |
|
|
T31 |
33 |
|
T32 |
3 |
|
T33 |
7 |
| auto[1] |
auto[0] |
1114402 |
1 |
|
|
T31 |
94 |
|
T32 |
7 |
|
T33 |
15 |
| auto[1] |
auto[1] |
724461 |
1 |
|
|
T31 |
35 |
|
T33 |
5 |
|
T1 |
3 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2097122 |
1 |
|
|
T31 |
132 |
|
T32 |
19 |
|
T33 |
48 |
| auto[1] |
1837919 |
1 |
|
|
T31 |
125 |
|
T32 |
23 |
|
T33 |
12 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2470042 |
1 |
|
|
T31 |
174 |
|
T32 |
39 |
|
T33 |
57 |
| auto[1] |
1464999 |
1 |
|
|
T31 |
83 |
|
T32 |
3 |
|
T33 |
3 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1358792 |
1 |
|
|
T31 |
79 |
|
T32 |
16 |
|
T33 |
45 |
| auto[0] |
auto[1] |
738330 |
1 |
|
|
T31 |
53 |
|
T32 |
3 |
|
T33 |
3 |
| auto[1] |
auto[0] |
1111250 |
1 |
|
|
T31 |
95 |
|
T32 |
23 |
|
T33 |
12 |
| auto[1] |
auto[1] |
726669 |
1 |
|
|
T31 |
30 |
|
T11 |
49 |
|
T12 |
169 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2096793 |
1 |
|
|
T31 |
97 |
|
T32 |
38 |
|
T33 |
52 |
| auto[1] |
1838248 |
1 |
|
|
T31 |
160 |
|
T32 |
4 |
|
T33 |
8 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2481470 |
1 |
|
|
T31 |
173 |
|
T32 |
38 |
|
T33 |
56 |
| auto[1] |
1453571 |
1 |
|
|
T31 |
84 |
|
T32 |
4 |
|
T33 |
4 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1366060 |
1 |
|
|
T31 |
66 |
|
T32 |
34 |
|
T33 |
50 |
| auto[0] |
auto[1] |
730733 |
1 |
|
|
T31 |
31 |
|
T32 |
4 |
|
T33 |
2 |
| auto[1] |
auto[0] |
1115410 |
1 |
|
|
T31 |
107 |
|
T32 |
4 |
|
T33 |
6 |
| auto[1] |
auto[1] |
722838 |
1 |
|
|
T31 |
53 |
|
T33 |
2 |
|
T1 |
5 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2095915 |
1 |
|
|
T31 |
125 |
|
T32 |
15 |
|
T33 |
29 |
| auto[1] |
1839126 |
1 |
|
|
T31 |
132 |
|
T32 |
27 |
|
T33 |
31 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2476877 |
1 |
|
|
T31 |
190 |
|
T32 |
38 |
|
T33 |
49 |
| auto[1] |
1458164 |
1 |
|
|
T31 |
67 |
|
T32 |
4 |
|
T33 |
11 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1362437 |
1 |
|
|
T31 |
94 |
|
T32 |
11 |
|
T33 |
24 |
| auto[0] |
auto[1] |
733478 |
1 |
|
|
T31 |
31 |
|
T32 |
4 |
|
T33 |
5 |
| auto[1] |
auto[0] |
1114440 |
1 |
|
|
T31 |
96 |
|
T32 |
27 |
|
T33 |
25 |
| auto[1] |
auto[1] |
724686 |
1 |
|
|
T31 |
36 |
|
T33 |
6 |
|
T1 |
8 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2100748 |
1 |
|
|
T31 |
157 |
|
T32 |
17 |
|
T33 |
32 |
| auto[1] |
1834293 |
1 |
|
|
T31 |
100 |
|
T32 |
25 |
|
T33 |
28 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2481840 |
1 |
|
|
T31 |
185 |
|
T32 |
38 |
|
T33 |
43 |
| auto[1] |
1453201 |
1 |
|
|
T31 |
72 |
|
T32 |
4 |
|
T33 |
17 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1369298 |
1 |
|
|
T31 |
111 |
|
T32 |
14 |
|
T33 |
28 |
| auto[0] |
auto[1] |
731450 |
1 |
|
|
T31 |
46 |
|
T32 |
3 |
|
T33 |
4 |
| auto[1] |
auto[0] |
1112542 |
1 |
|
|
T31 |
74 |
|
T32 |
24 |
|
T33 |
15 |
| auto[1] |
auto[1] |
721751 |
1 |
|
|
T31 |
26 |
|
T32 |
1 |
|
T33 |
13 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2095729 |
1 |
|
|
T31 |
103 |
|
T32 |
27 |
|
T33 |
54 |
| auto[1] |
1839312 |
1 |
|
|
T31 |
154 |
|
T32 |
15 |
|
T33 |
6 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2478032 |
1 |
|
|
T31 |
164 |
|
T32 |
39 |
|
T33 |
47 |
| auto[1] |
1457009 |
1 |
|
|
T31 |
93 |
|
T32 |
3 |
|
T33 |
13 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1361919 |
1 |
|
|
T31 |
70 |
|
T32 |
25 |
|
T33 |
43 |
| auto[0] |
auto[1] |
733810 |
1 |
|
|
T31 |
33 |
|
T32 |
2 |
|
T33 |
11 |
| auto[1] |
auto[0] |
1116113 |
1 |
|
|
T31 |
94 |
|
T32 |
14 |
|
T33 |
4 |
| auto[1] |
auto[1] |
723199 |
1 |
|
|
T31 |
60 |
|
T32 |
1 |
|
T33 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2099996 |
1 |
|
|
T31 |
86 |
|
T32 |
19 |
|
T33 |
36 |
| auto[1] |
1835045 |
1 |
|
|
T31 |
171 |
|
T32 |
23 |
|
T33 |
24 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2479095 |
1 |
|
|
T31 |
201 |
|
T32 |
39 |
|
T33 |
43 |
| auto[1] |
1455946 |
1 |
|
|
T31 |
56 |
|
T32 |
3 |
|
T33 |
17 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1367127 |
1 |
|
|
T31 |
64 |
|
T32 |
17 |
|
T33 |
34 |
| auto[0] |
auto[1] |
732869 |
1 |
|
|
T31 |
22 |
|
T32 |
2 |
|
T33 |
2 |
| auto[1] |
auto[0] |
1111968 |
1 |
|
|
T31 |
137 |
|
T32 |
22 |
|
T33 |
9 |
| auto[1] |
auto[1] |
723077 |
1 |
|
|
T31 |
34 |
|
T32 |
1 |
|
T33 |
15 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2102946 |
1 |
|
|
T31 |
146 |
|
T32 |
31 |
|
T33 |
44 |
| auto[1] |
1832095 |
1 |
|
|
T31 |
111 |
|
T32 |
11 |
|
T33 |
16 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2474979 |
1 |
|
|
T31 |
191 |
|
T32 |
38 |
|
T33 |
46 |
| auto[1] |
1460062 |
1 |
|
|
T31 |
66 |
|
T32 |
4 |
|
T33 |
14 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1366449 |
1 |
|
|
T31 |
110 |
|
T32 |
27 |
|
T33 |
37 |
| auto[0] |
auto[1] |
736497 |
1 |
|
|
T31 |
36 |
|
T32 |
4 |
|
T33 |
7 |
| auto[1] |
auto[0] |
1108530 |
1 |
|
|
T31 |
81 |
|
T32 |
11 |
|
T33 |
9 |
| auto[1] |
auto[1] |
723565 |
1 |
|
|
T31 |
30 |
|
T33 |
7 |
|
T11 |
51 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2094218 |
1 |
|
|
T31 |
137 |
|
T32 |
15 |
|
T33 |
46 |
| auto[1] |
1840823 |
1 |
|
|
T31 |
120 |
|
T32 |
27 |
|
T33 |
14 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2478947 |
1 |
|
|
T31 |
185 |
|
T32 |
37 |
|
T33 |
50 |
| auto[1] |
1456094 |
1 |
|
|
T31 |
72 |
|
T32 |
5 |
|
T33 |
10 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1363728 |
1 |
|
|
T31 |
94 |
|
T32 |
12 |
|
T33 |
42 |
| auto[0] |
auto[1] |
730490 |
1 |
|
|
T31 |
43 |
|
T32 |
3 |
|
T33 |
4 |
| auto[1] |
auto[0] |
1115219 |
1 |
|
|
T31 |
91 |
|
T32 |
25 |
|
T33 |
8 |
| auto[1] |
auto[1] |
725604 |
1 |
|
|
T31 |
29 |
|
T32 |
2 |
|
T33 |
6 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2099910 |
1 |
|
|
T31 |
143 |
|
T32 |
42 |
|
T33 |
35 |
| auto[1] |
1835131 |
1 |
|
|
T31 |
114 |
|
T33 |
25 |
|
T1 |
47 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2481052 |
1 |
|
|
T31 |
194 |
|
T32 |
38 |
|
T33 |
53 |
| auto[1] |
1453989 |
1 |
|
|
T31 |
63 |
|
T32 |
4 |
|
T33 |
7 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1368295 |
1 |
|
|
T31 |
112 |
|
T32 |
38 |
|
T33 |
35 |
| auto[0] |
auto[1] |
731615 |
1 |
|
|
T31 |
31 |
|
T32 |
4 |
|
T1 |
3 |
| auto[1] |
auto[0] |
1112757 |
1 |
|
|
T31 |
82 |
|
T33 |
18 |
|
T1 |
42 |
| auto[1] |
auto[1] |
722374 |
1 |
|
|
T31 |
32 |
|
T33 |
7 |
|
T1 |
5 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2098684 |
1 |
|
|
T31 |
123 |
|
T32 |
22 |
|
T33 |
57 |
| auto[1] |
1836357 |
1 |
|
|
T31 |
134 |
|
T32 |
20 |
|
T33 |
3 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2479570 |
1 |
|
|
T31 |
207 |
|
T32 |
37 |
|
T33 |
55 |
| auto[1] |
1455471 |
1 |
|
|
T31 |
50 |
|
T32 |
5 |
|
T33 |
5 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1365083 |
1 |
|
|
T31 |
102 |
|
T32 |
18 |
|
T33 |
52 |
| auto[0] |
auto[1] |
733601 |
1 |
|
|
T31 |
21 |
|
T32 |
4 |
|
T33 |
5 |
| auto[1] |
auto[0] |
1114487 |
1 |
|
|
T31 |
105 |
|
T32 |
19 |
|
T33 |
3 |
| auto[1] |
auto[1] |
721870 |
1 |
|
|
T31 |
29 |
|
T32 |
1 |
|
T1 |
6 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2095764 |
1 |
|
|
T31 |
104 |
|
T32 |
18 |
|
T33 |
34 |
| auto[1] |
1839277 |
1 |
|
|
T31 |
153 |
|
T32 |
24 |
|
T33 |
26 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2479537 |
1 |
|
|
T31 |
180 |
|
T32 |
40 |
|
T33 |
44 |
| auto[1] |
1455504 |
1 |
|
|
T31 |
77 |
|
T32 |
2 |
|
T33 |
16 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1363588 |
1 |
|
|
T31 |
80 |
|
T32 |
17 |
|
T33 |
26 |
| auto[0] |
auto[1] |
732176 |
1 |
|
|
T31 |
24 |
|
T32 |
1 |
|
T33 |
8 |
| auto[1] |
auto[0] |
1115949 |
1 |
|
|
T31 |
100 |
|
T32 |
23 |
|
T33 |
18 |
| auto[1] |
auto[1] |
723328 |
1 |
|
|
T31 |
53 |
|
T32 |
1 |
|
T33 |
8 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2097063 |
1 |
|
|
T31 |
145 |
|
T32 |
30 |
|
T33 |
42 |
| auto[1] |
1837978 |
1 |
|
|
T31 |
112 |
|
T32 |
12 |
|
T33 |
18 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2471313 |
1 |
|
|
T31 |
177 |
|
T32 |
38 |
|
T33 |
51 |
| auto[1] |
1463728 |
1 |
|
|
T31 |
80 |
|
T32 |
4 |
|
T33 |
9 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1360573 |
1 |
|
|
T31 |
92 |
|
T32 |
26 |
|
T33 |
38 |
| auto[0] |
auto[1] |
736490 |
1 |
|
|
T31 |
53 |
|
T32 |
4 |
|
T33 |
4 |
| auto[1] |
auto[0] |
1110740 |
1 |
|
|
T31 |
85 |
|
T32 |
12 |
|
T33 |
13 |
| auto[1] |
auto[1] |
727238 |
1 |
|
|
T31 |
27 |
|
T33 |
5 |
|
T1 |
7 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2100364 |
1 |
|
|
T31 |
127 |
|
T32 |
14 |
|
T33 |
46 |
| auto[1] |
1834677 |
1 |
|
|
T31 |
130 |
|
T32 |
28 |
|
T33 |
14 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2475411 |
1 |
|
|
T31 |
172 |
|
T32 |
38 |
|
T33 |
55 |
| auto[1] |
1459630 |
1 |
|
|
T31 |
85 |
|
T32 |
4 |
|
T33 |
5 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1365021 |
1 |
|
|
T31 |
87 |
|
T32 |
11 |
|
T33 |
43 |
| auto[0] |
auto[1] |
735343 |
1 |
|
|
T31 |
40 |
|
T32 |
3 |
|
T33 |
3 |
| auto[1] |
auto[0] |
1110390 |
1 |
|
|
T31 |
85 |
|
T32 |
27 |
|
T33 |
12 |
| auto[1] |
auto[1] |
724287 |
1 |
|
|
T31 |
45 |
|
T32 |
1 |
|
T33 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2099310 |
1 |
|
|
T31 |
129 |
|
T32 |
36 |
|
T33 |
46 |
| auto[1] |
1835731 |
1 |
|
|
T31 |
128 |
|
T32 |
6 |
|
T33 |
14 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2479639 |
1 |
|
|
T31 |
184 |
|
T32 |
40 |
|
T33 |
55 |
| auto[1] |
1455402 |
1 |
|
|
T31 |
73 |
|
T32 |
2 |
|
T33 |
5 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1365869 |
1 |
|
|
T31 |
94 |
|
T32 |
34 |
|
T33 |
46 |
| auto[0] |
auto[1] |
733441 |
1 |
|
|
T31 |
35 |
|
T32 |
2 |
|
T1 |
2 |
| auto[1] |
auto[0] |
1113770 |
1 |
|
|
T31 |
90 |
|
T32 |
6 |
|
T33 |
9 |
| auto[1] |
auto[1] |
721961 |
1 |
|
|
T31 |
38 |
|
T33 |
5 |
|
T1 |
13 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2094934 |
1 |
|
|
T31 |
156 |
|
T32 |
14 |
|
T33 |
28 |
| auto[1] |
1840107 |
1 |
|
|
T31 |
101 |
|
T32 |
28 |
|
T33 |
32 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2472895 |
1 |
|
|
T31 |
199 |
|
T32 |
39 |
|
T33 |
46 |
| auto[1] |
1462146 |
1 |
|
|
T31 |
58 |
|
T32 |
3 |
|
T33 |
14 |