Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4311132	1			T31	1		T32	1		T33	34
all_pins[1]	4311132	1			T31	1		T32	1		T33	34
all_pins[2]	4311132	1			T31	1		T32	1		T33	34
all_pins[3]	4311132	1			T31	1		T32	1		T33	34
all_pins[4]	4311132	1			T31	1		T32	1		T33	34
all_pins[5]	4311132	1			T31	1		T32	1		T33	34
all_pins[6]	4311132	1			T31	1		T32	1		T33	34
all_pins[7]	4311132	1			T31	1		T32	1		T33	34
all_pins[8]	4311132	1			T31	1		T32	1		T33	34
all_pins[9]	4311132	1			T31	1		T32	1		T33	34
all_pins[10]	4311132	1			T31	1		T32	1		T33	34
all_pins[11]	4311132	1			T31	1		T32	1		T33	34
all_pins[12]	4311132	1			T31	1		T32	1		T33	34
all_pins[13]	4311132	1			T31	1		T32	1		T33	34
all_pins[14]	4311132	1			T31	1		T32	1		T33	34
all_pins[15]	4311132	1			T31	1		T32	1		T33	34
all_pins[16]	4311132	1			T31	1		T32	1		T33	34
all_pins[17]	4311132	1			T31	1		T32	1		T33	34
all_pins[18]	4311132	1			T31	1		T32	1		T33	34
all_pins[19]	4311132	1			T31	1		T32	1		T33	34
all_pins[20]	4311132	1			T31	1		T32	1		T33	34
all_pins[21]	4311132	1			T31	1		T32	1		T33	34
all_pins[22]	4311132	1			T31	1		T32	1		T33	34
all_pins[23]	4311132	1			T31	1		T32	1		T33	34
all_pins[24]	4311132	1			T31	1		T32	1		T33	34
all_pins[25]	4311132	1			T31	1		T32	1		T33	34
all_pins[26]	4311132	1			T31	1		T32	1		T33	34
all_pins[27]	4311132	1			T31	1		T32	1		T33	34
all_pins[28]	4311132	1			T31	1		T32	1		T33	34
all_pins[29]	4311132	1			T31	1		T32	1		T33	34
all_pins[30]	4311132	1			T31	1		T32	1		T33	34
all_pins[31]	4311132	1			T31	1		T32	1		T33	34

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	85641200	1			T31	32		T32	32		T33	890
values[0x1]	52315024	1			T33	198		T34	2433		T1	286
transitions[0x0=>0x1]	31332561	1			T33	125		T34	1397		T1	215
transitions[0x1=>0x0]	31332411	1			T33	125		T34	1397		T1	215

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2683716	1			T31	1		T32	1		T33	28
all_pins[0]	values[0x1]	1627416	1			T33	6		T34	64		T1	10
all_pins[0]	transitions[0x0=>0x1]	1007130	1			T33	2		T34	48		T1	10
all_pins[0]	transitions[0x1=>0x0]	1014665	1			T33	1		T34	45		T1	20
all_pins[1]	values[0x0]	2681714	1			T31	1		T32	1		T33	30
all_pins[1]	values[0x1]	1629418	1			T33	4		T34	77		T1	16
all_pins[1]	transitions[0x0=>0x1]	976469	1			T33	2		T34	45		T1	13
all_pins[1]	transitions[0x1=>0x0]	974467	1			T33	4		T34	32		T1	7
all_pins[2]	values[0x0]	2675782	1			T31	1		T32	1		T33	27
all_pins[2]	values[0x1]	1635350	1			T33	7		T34	69		T1	8
all_pins[2]	transitions[0x0=>0x1]	978520	1			T33	5		T34	47		T1	4
all_pins[2]	transitions[0x1=>0x0]	972588	1			T33	2		T34	55		T1	12
all_pins[3]	values[0x0]	2677306	1			T31	1		T32	1		T33	30
all_pins[3]	values[0x1]	1633826	1			T33	4		T34	51		T1	10
all_pins[3]	transitions[0x0=>0x1]	976649	1			T33	2		T34	28		T1	5
all_pins[3]	transitions[0x1=>0x0]	978173	1			T33	5		T34	46		T1	3
all_pins[4]	values[0x0]	2676993	1			T31	1		T32	1		T33	28
all_pins[4]	values[0x1]	1634139	1			T33	6		T34	75		T1	14
all_pins[4]	transitions[0x0=>0x1]	979741	1			T33	2		T34	48		T1	8
all_pins[4]	transitions[0x1=>0x0]	979428	1			T34	24		T1	4		T12	122
all_pins[5]	values[0x0]	2673621	1			T31	1		T32	1		T33	33
all_pins[5]	values[0x1]	1637511	1			T33	1		T34	70		T1	5
all_pins[5]	transitions[0x0=>0x1]	978252	1			T33	1		T34	51		T1	2
all_pins[5]	transitions[0x1=>0x0]	974880	1			T33	6		T34	56		T1	11
all_pins[6]	values[0x0]	2668473	1			T31	1		T32	1		T33	27
all_pins[6]	values[0x1]	1642659	1			T33	7		T34	77		T1	10
all_pins[6]	transitions[0x0=>0x1]	982613	1			T33	7		T34	52		T1	9
all_pins[6]	transitions[0x1=>0x0]	977465	1			T33	1		T34	45		T1	4
all_pins[7]	values[0x0]	2677229	1			T31	1		T32	1		T33	27
all_pins[7]	values[0x1]	1633903	1			T33	7		T34	65		T1	5
all_pins[7]	transitions[0x0=>0x1]	972328	1			T33	4		T34	26		T12	164
all_pins[7]	transitions[0x1=>0x0]	981084	1			T33	4		T34	38		T1	5
all_pins[8]	values[0x0]	2676091	1			T31	1		T32	1		T33	32
all_pins[8]	values[0x1]	1635041	1			T33	2		T34	87		T1	8
all_pins[8]	transitions[0x0=>0x1]	980082	1			T33	2		T34	51		T1	3
all_pins[8]	transitions[0x1=>0x0]	978944	1			T33	7		T34	29		T12	123
all_pins[9]	values[0x0]	2675689	1			T31	1		T32	1		T33	26
all_pins[9]	values[0x1]	1635443	1			T33	8		T34	76		T1	5
all_pins[9]	transitions[0x0=>0x1]	979837	1			T33	6		T34	38		T1	3
all_pins[9]	transitions[0x1=>0x0]	979435	1			T34	49		T1	6		T12	108
all_pins[10]	values[0x0]	2678011	1			T31	1		T32	1		T33	26
all_pins[10]	values[0x1]	1633121	1			T33	8		T34	81		T1	3
all_pins[10]	transitions[0x0=>0x1]	976022	1			T34	40		T1	1		T12	123
all_pins[10]	transitions[0x1=>0x0]	978344	1			T34	35		T1	3		T12	166
all_pins[11]	values[0x0]	2672713	1			T31	1		T32	1		T33	27
all_pins[11]	values[0x1]	1638419	1			T33	7		T34	64		T1	3
all_pins[11]	transitions[0x0=>0x1]	980323	1			T33	2		T34	37		T1	3
all_pins[11]	transitions[0x1=>0x0]	975025	1			T33	3		T34	54		T1	3
all_pins[12]	values[0x0]	2680438	1			T31	1		T32	1		T33	25
all_pins[12]	values[0x1]	1630694	1			T33	9		T34	78		T1	5
all_pins[12]	transitions[0x0=>0x1]	975472	1			T33	6		T34	47		T1	5
all_pins[12]	transitions[0x1=>0x0]	983197	1			T33	4		T34	33		T1	3
all_pins[13]	values[0x0]	2678145	1			T31	1		T32	1		T33	22
all_pins[13]	values[0x1]	1632987	1			T33	12		T34	76		T1	4
all_pins[13]	transitions[0x0=>0x1]	979058	1			T33	6		T34	45		T1	4
all_pins[13]	transitions[0x1=>0x0]	976765	1			T33	3		T34	47		T1	5
all_pins[14]	values[0x0]	2671583	1			T31	1		T32	1		T33	32
all_pins[14]	values[0x1]	1639549	1			T33	2		T34	92		T1	3
all_pins[14]	transitions[0x0=>0x1]	983714	1			T34	54		T1	3		T12	153
all_pins[14]	transitions[0x1=>0x0]	977152	1			T33	10		T34	38		T1	4
all_pins[15]	values[0x0]	2674633	1			T31	1		T32	1		T33	25
all_pins[15]	values[0x1]	1636499	1			T33	9		T34	45		T1	17
all_pins[15]	transitions[0x0=>0x1]	977165	1			T33	9		T34	25		T1	17
all_pins[15]	transitions[0x1=>0x0]	980215	1			T33	2		T34	72		T1	3
all_pins[16]	values[0x0]	2674679	1			T31	1		T32	1		T33	23
all_pins[16]	values[0x1]	1636453	1			T33	11		T34	61		T1	5
all_pins[16]	transitions[0x0=>0x1]	981255	1			T33	6		T34	49		T1	1
all_pins[16]	transitions[0x1=>0x0]	981301	1			T33	4		T34	33		T1	13
all_pins[17]	values[0x0]	2678340	1			T31	1		T32	1		T33	26
all_pins[17]	values[0x1]	1632792	1			T33	8		T34	83		T1	9
all_pins[17]	transitions[0x0=>0x1]	974904	1			T33	2		T34	48		T1	7
all_pins[17]	transitions[0x1=>0x0]	978565	1			T33	5		T34	26		T1	3
all_pins[18]	values[0x0]	2676201	1			T31	1		T32	1		T33	29
all_pins[18]	values[0x1]	1634931	1			T33	5		T34	90		T1	9
all_pins[18]	transitions[0x0=>0x1]	975410	1			T33	5		T34	48		T1	7
all_pins[18]	transitions[0x1=>0x0]	973271	1			T33	8		T34	41		T1	7
all_pins[19]	values[0x0]	2677133	1			T31	1		T32	1		T33	30
all_pins[19]	values[0x1]	1633999	1			T33	4		T34	81		T1	9
all_pins[19]	transitions[0x0=>0x1]	976875	1			T33	4		T34	48		T1	7
all_pins[19]	transitions[0x1=>0x0]	977807	1			T33	5		T34	57		T1	7
all_pins[20]	values[0x0]	2673459	1			T31	1		T32	1		T33	34
all_pins[20]	values[0x1]	1637673	1			T34	96		T1	11		T12	223
all_pins[20]	transitions[0x0=>0x1]	980296	1			T34	48		T1	10		T12	144
all_pins[20]	transitions[0x1=>0x0]	976622	1			T33	4		T34	33		T1	8
all_pins[21]	values[0x0]	2674372	1			T31	1		T32	1		T33	28
all_pins[21]	values[0x1]	1636760	1			T33	6		T34	73		T1	17
all_pins[21]	transitions[0x0=>0x1]	977755	1			T33	6		T34	39		T1	8
all_pins[21]	transitions[0x1=>0x0]	978668	1			T34	62		T1	2		T12	143
all_pins[22]	values[0x0]	2669814	1			T31	1		T32	1		T33	32
all_pins[22]	values[0x1]	1641318	1			T33	2		T34	59		T1	4
all_pins[22]	transitions[0x0=>0x1]	980678	1			T33	2		T34	30		T1	2
all_pins[22]	transitions[0x1=>0x0]	976120	1			T33	6		T34	44		T1	15
all_pins[23]	values[0x0]	2680258	1			T31	1		T32	1		T33	30
all_pins[23]	values[0x1]	1630874	1			T33	4		T34	87		T1	7
all_pins[23]	transitions[0x0=>0x1]	973353	1			T33	3		T34	59		T1	7
all_pins[23]	transitions[0x1=>0x0]	983797	1			T33	1		T34	31		T1	4
all_pins[24]	values[0x0]	2678610	1			T31	1		T32	1		T33	28
all_pins[24]	values[0x1]	1632522	1			T33	6		T34	89		T1	13
all_pins[24]	transitions[0x0=>0x1]	977841	1			T33	6		T34	43		T1	11
all_pins[24]	transitions[0x1=>0x0]	976193	1			T33	4		T34	41		T1	5
all_pins[25]	values[0x0]	2672888	1			T31	1		T32	1		T33	25
all_pins[25]	values[0x1]	1638244	1			T33	9		T34	94		T1	10
all_pins[25]	transitions[0x0=>0x1]	982534	1			T33	6		T34	53		T1	7
all_pins[25]	transitions[0x1=>0x0]	976812	1			T33	3		T34	48		T1	10
all_pins[26]	values[0x0]	2677649	1			T31	1		T32	1		T33	25
all_pins[26]	values[0x1]	1633483	1			T33	9		T34	103		T1	5
all_pins[26]	transitions[0x0=>0x1]	974491	1			T33	5		T34	50		T1	4
all_pins[26]	transitions[0x1=>0x0]	979252	1			T33	5		T34	41		T1	9
all_pins[27]	values[0x0]	2679956	1			T31	1		T32	1		T33	23
all_pins[27]	values[0x1]	1631176	1			T33	11		T34	95		T1	19
all_pins[27]	transitions[0x0=>0x1]	978638	1			T33	5		T34	44		T1	18
all_pins[27]	transitions[0x1=>0x0]	980945	1			T33	3		T34	52		T1	4
all_pins[28]	values[0x0]	2673823	1			T31	1		T32	1		T33	25
all_pins[28]	values[0x1]	1637309	1			T33	9		T34	56		T1	9
all_pins[28]	transitions[0x0=>0x1]	981062	1			T33	4		T34	37		T1	5
all_pins[28]	transitions[0x1=>0x0]	974929	1			T33	6		T34	76		T1	15
all_pins[29]	values[0x0]	2678313	1			T31	1		T32	1		T33	29
all_pins[29]	values[0x1]	1632819	1			T33	5		T34	72		T1	8
all_pins[29]	transitions[0x0=>0x1]	977705	1			T33	5		T34	55		T1	7
all_pins[29]	transitions[0x1=>0x0]	982195	1			T33	9		T34	39		T1	8
all_pins[30]	values[0x0]	2677537	1			T31	1		T32	1		T33	29
all_pins[30]	values[0x1]	1633595	1			T33	5		T34	86		T1	5
all_pins[30]	transitions[0x0=>0x1]	975913	1			T33	5		T34	45		T1	5
all_pins[30]	transitions[0x1=>0x0]	975137	1			T33	5		T34	31		T1	8
all_pins[31]	values[0x0]	2676031	1			T31	1		T32	1		T33	29
all_pins[31]	values[0x1]	1635101	1			T33	5		T34	61		T1	20
all_pins[31]	transitions[0x0=>0x1]	980476	1			T33	5		T34	19		T1	19
all_pins[31]	transitions[0x1=>0x0]	978970	1			T33	5		T34	44		T1	4