Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14492162	1			T31	278		T32	54		T33	61
all_values[1]	14492162	1			T31	278		T32	54		T33	61
all_values[2]	14492162	1			T31	278		T32	54		T33	61
all_values[3]	14492162	1			T31	278		T32	54		T33	61
all_values[4]	14492162	1			T31	278		T32	54		T33	61
all_values[5]	14492162	1			T31	278		T32	54		T33	61
all_values[6]	14492162	1			T31	278		T32	54		T33	61
all_values[7]	14492162	1			T31	278		T32	54		T33	61
all_values[8]	14492162	1			T31	278		T32	54		T33	61
all_values[9]	14492162	1			T31	278		T32	54		T33	61
all_values[10]	14492162	1			T31	278		T32	54		T33	61
all_values[11]	14492162	1			T31	278		T32	54		T33	61
all_values[12]	14492162	1			T31	278		T32	54		T33	61
all_values[13]	14492162	1			T31	278		T32	54		T33	61
all_values[14]	14492162	1			T31	278		T32	54		T33	61
all_values[15]	14492162	1			T31	278		T32	54		T33	61
all_values[16]	14492162	1			T31	278		T32	54		T33	61
all_values[17]	14492162	1			T31	278		T32	54		T33	61
all_values[18]	14492162	1			T31	278		T32	54		T33	61
all_values[19]	14492162	1			T31	278		T32	54		T33	61
all_values[20]	14492162	1			T31	278		T32	54		T33	61
all_values[21]	14492162	1			T31	278		T32	54		T33	61
all_values[22]	14492162	1			T31	278		T32	54		T33	61
all_values[23]	14492162	1			T31	278		T32	54		T33	61
all_values[24]	14492162	1			T31	278		T32	54		T33	61
all_values[25]	14492162	1			T31	278		T32	54		T33	61
all_values[26]	14492162	1			T31	278		T32	54		T33	61
all_values[27]	14492162	1			T31	278		T32	54		T33	61
all_values[28]	14492162	1			T31	278		T32	54		T33	61
all_values[29]	14492162	1			T31	278		T32	54		T33	61
all_values[30]	14492162	1			T31	278		T32	54		T33	61
all_values[31]	14492162	1			T31	278		T32	54		T33	61

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

266675617

1

T31

8896

T32

1728

T33

1389

auto[1]

197073567

1

T33

563

T34

5706

T1

947

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107001148

1

T31

8896

T32

1728

T33

1328

auto[1]

356748036

1

T33

624

T34

9455

T1

1446

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

458739823

1

T31

8896

T32

1728

T33

1891

auto[1]

5009361

1

T33

61

T1

149

T12

2252

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2751778	1			T31	278		T32	54		T33	36
all_values[0]	auto[0]	auto[0]	auto[1]	5508656	1			T33	3		T34	139		T1	27
all_values[0]	auto[0]	auto[1]	auto[0]	590879	1			T33	12		T34	36		T1	14
all_values[0]	auto[0]	auto[1]	auto[1]	5484568	1			T33	8		T34	124		T1	13
all_values[0]	auto[1]	auto[0]	auto[1]	78029	1			T33	2		T1	4		T12	34
all_values[0]	auto[1]	auto[1]	auto[1]	78252	1			T1	2		T12	40		T14	34
all_values[1]	auto[0]	auto[0]	auto[0]	2764196	1			T31	278		T32	54		T33	29
all_values[1]	auto[0]	auto[0]	auto[1]	5466709	1			T33	9		T34	186		T1	30
all_values[1]	auto[0]	auto[1]	auto[0]	597431	1			T33	15		T34	8		T1	11
all_values[1]	auto[0]	auto[1]	auto[1]	5507743	1			T33	6		T34	138		T1	22
all_values[1]	auto[1]	auto[0]	auto[1]	77988	1			T33	1		T1	3		T12	40
all_values[1]	auto[1]	auto[1]	auto[1]	78095	1			T33	1		T1	1		T12	26
all_values[2]	auto[0]	auto[0]	auto[0]	2745214	1			T31	278		T32	54		T33	32
all_values[2]	auto[0]	auto[0]	auto[1]	5501369	1			T33	12		T34	136		T1	47
all_values[2]	auto[0]	auto[1]	auto[0]	594967	1			T33	5		T34	36		T1	12
all_values[2]	auto[0]	auto[1]	auto[1]	5493904	1			T33	9		T34	144		T1	11
all_values[2]	auto[1]	auto[0]	auto[1]	78511	1			T33	2		T1	4		T12	43
all_values[2]	auto[1]	auto[1]	auto[1]	78197	1			T33	1		T1	1		T12	20
all_values[3]	auto[0]	auto[0]	auto[0]	2748258	1			T31	278		T32	54		T33	27
all_values[3]	auto[0]	auto[0]	auto[1]	5505331	1			T33	12		T34	158		T1	22
all_values[3]	auto[0]	auto[1]	auto[0]	594933	1			T33	13		T34	51		T1	23
all_values[3]	auto[0]	auto[1]	auto[1]	5487709	1			T33	6		T34	111		T1	15
all_values[3]	auto[1]	auto[0]	auto[1]	78369	1			T33	3		T1	3		T12	37
all_values[3]	auto[1]	auto[1]	auto[1]	77562	1			T12	39		T14	25		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	2749307	1			T31	278		T32	54		T33	34
all_values[4]	auto[0]	auto[0]	auto[1]	5498107	1			T34	157		T1	21		T12	583
all_values[4]	auto[0]	auto[1]	auto[0]	607090	1			T33	18		T34	24		T1	28
all_values[4]	auto[0]	auto[1]	auto[1]	5480510	1			T33	8		T34	146		T1	13
all_values[4]	auto[1]	auto[0]	auto[1]	78358	1			T33	1		T1	2		T12	26
all_values[4]	auto[1]	auto[1]	auto[1]	78790	1			T1	3		T12	55		T14	52
all_values[5]	auto[0]	auto[0]	auto[0]	2758654	1			T31	278		T32	54		T33	44
all_values[5]	auto[0]	auto[0]	auto[1]	5498117	1			T33	3		T34	156		T1	30
all_values[5]	auto[0]	auto[1]	auto[0]	587516	1			T33	13		T34	12		T1	5
all_values[5]	auto[0]	auto[1]	auto[1]	5491009	1			T33	1		T34	146		T1	9
all_values[5]	auto[1]	auto[0]	auto[1]	78764	1			T1	5		T12	42		T14	28
all_values[5]	auto[1]	auto[1]	auto[1]	78102	1			T12	31		T14	48		T16	1
all_values[6]	auto[0]	auto[0]	auto[0]	2750324	1			T31	278		T32	54		T33	33
all_values[6]	auto[0]	auto[0]	auto[1]	5494073	1			T33	9		T34	131		T1	30
all_values[6]	auto[0]	auto[1]	auto[0]	586888	1			T33	11		T34	39		T1	22
all_values[6]	auto[0]	auto[1]	auto[1]	5504101	1			T33	6		T34	147		T1	12
all_values[6]	auto[1]	auto[0]	auto[1]	78497	1			T33	2		T1	5		T12	34
all_values[6]	auto[1]	auto[1]	auto[1]	78279	1			T1	2		T12	40		T14	48
all_values[7]	auto[0]	auto[0]	auto[0]	2748533	1			T31	278		T32	54		T33	30
all_values[7]	auto[0]	auto[0]	auto[1]	5528492	1			T33	14		T34	170		T1	39
all_values[7]	auto[0]	auto[1]	auto[0]	586716	1			T33	6		T34	26		T1	1
all_values[7]	auto[0]	auto[1]	auto[1]	5471825	1			T33	9		T34	127		T1	9
all_values[7]	auto[1]	auto[0]	auto[1]	78494	1			T33	2		T1	4		T12	31
all_values[7]	auto[1]	auto[1]	auto[1]	78102	1			T12	43		T14	24		T16	1
all_values[8]	auto[0]	auto[0]	auto[0]	2749246	1			T31	278		T32	54		T33	30
all_values[8]	auto[0]	auto[0]	auto[1]	5497111	1			T33	3		T34	105		T1	38
all_values[8]	auto[0]	auto[1]	auto[0]	587326	1			T33	23		T34	39		T1	5
all_values[8]	auto[0]	auto[1]	auto[1]	5501922	1			T33	2		T34	174		T1	16
all_values[8]	auto[1]	auto[0]	auto[1]	78629	1			T33	2		T1	6		T12	37
all_values[8]	auto[1]	auto[1]	auto[1]	77928	1			T33	1		T12	32		T14	45
all_values[9]	auto[0]	auto[0]	auto[0]	2750917	1			T31	278		T32	54		T33	36
all_values[9]	auto[0]	auto[0]	auto[1]	5456032	1			T33	12		T34	152		T1	33
all_values[9]	auto[0]	auto[1]	auto[0]	590437	1			T34	12		T1	10		T12	70
all_values[9]	auto[0]	auto[1]	auto[1]	5538147	1			T33	11		T34	156		T1	8
all_values[9]	auto[1]	auto[0]	auto[1]	78401	1			T33	1		T1	5		T12	38
all_values[9]	auto[1]	auto[1]	auto[1]	78228	1			T33	1		T1	1		T12	42
all_values[10]	auto[0]	auto[0]	auto[0]	2754176	1			T31	278		T32	54		T33	32
all_values[10]	auto[0]	auto[0]	auto[1]	5519068	1			T33	9		T34	135		T1	35
all_values[10]	auto[0]	auto[1]	auto[0]	591499	1			T33	7		T34	8		T1	16
all_values[10]	auto[0]	auto[1]	auto[1]	5471501	1			T33	11		T34	162		T1	6
all_values[10]	auto[1]	auto[0]	auto[1]	78079	1			T33	1		T1	4		T12	35
all_values[10]	auto[1]	auto[1]	auto[1]	77839	1			T33	1		T1	1		T12	43
all_values[11]	auto[0]	auto[0]	auto[0]	2752040	1			T31	278		T32	54		T33	38
all_values[11]	auto[0]	auto[0]	auto[1]	5493910	1			T33	10		T34	205		T1	22
all_values[11]	auto[0]	auto[1]	auto[0]	582169	1			T34	9		T1	22		T12	97
all_values[11]	auto[0]	auto[1]	auto[1]	5507458	1			T33	11		T34	107		T1	3
all_values[11]	auto[1]	auto[0]	auto[1]	78635	1			T33	2		T1	6		T12	32
all_values[11]	auto[1]	auto[1]	auto[1]	77950	1			T12	42		T14	33		T16	1
all_values[12]	auto[0]	auto[0]	auto[0]	2747436	1			T31	278		T32	54		T33	39
all_values[12]	auto[0]	auto[0]	auto[1]	5562201	1			T33	3		T34	140		T1	37
all_values[12]	auto[0]	auto[1]	auto[0]	595562	1			T33	7		T34	23		T1	19
all_values[12]	auto[0]	auto[1]	auto[1]	5430349	1			T33	12		T34	164		T1	5
all_values[12]	auto[1]	auto[0]	auto[1]	79265	1			T1	6		T12	21		T14	41
all_values[12]	auto[1]	auto[1]	auto[1]	77349	1			T1	2		T12	45		T14	34
all_values[13]	auto[0]	auto[0]	auto[0]	2740426	1			T31	278		T32	54		T33	28
all_values[13]	auto[0]	auto[0]	auto[1]	5505163	1			T33	8		T34	120		T1	34
all_values[13]	auto[0]	auto[1]	auto[0]	590571	1			T33	9		T34	46		T1	15
all_values[13]	auto[0]	auto[1]	auto[1]	5498829	1			T33	15		T34	159		T1	5
all_values[13]	auto[1]	auto[0]	auto[1]	78604	1			T33	1		T1	5		T12	27
all_values[13]	auto[1]	auto[1]	auto[1]	78569	1			T12	45		T14	44		T16	1
all_values[14]	auto[0]	auto[0]	auto[0]	2752957	1			T31	278		T32	54		T33	34
all_values[14]	auto[0]	auto[0]	auto[1]	5491212	1			T33	9		T34	121		T1	37
all_values[14]	auto[0]	auto[1]	auto[0]	592318	1			T33	12		T34	19		T1	27
all_values[14]	auto[0]	auto[1]	auto[1]	5499270	1			T33	4		T34	177		T1	5
all_values[14]	auto[1]	auto[0]	auto[1]	78660	1			T33	2		T1	4		T12	37
all_values[14]	auto[1]	auto[1]	auto[1]	77745	1			T1	1		T12	39		T14	33
all_values[15]	auto[0]	auto[0]	auto[0]	2746596	1			T31	278		T32	54		T33	30
all_values[15]	auto[0]	auto[0]	auto[1]	5481906	1			T33	11		T34	163		T1	21
all_values[15]	auto[0]	auto[1]	auto[0]	595218	1			T33	7		T34	43		T1	18
all_values[15]	auto[0]	auto[1]	auto[1]	5511532	1			T33	11		T34	109		T1	23
all_values[15]	auto[1]	auto[0]	auto[1]	78763	1			T33	2		T1	2		T12	34
all_values[15]	auto[1]	auto[1]	auto[1]	78147	1			T12	29		T14	25		T16	2
all_values[16]	auto[0]	auto[0]	auto[0]	2757950	1			T31	278		T32	54		T33	25
all_values[16]	auto[0]	auto[0]	auto[1]	5513119	1			T33	6		T34	179		T1	36
all_values[16]	auto[0]	auto[1]	auto[0]	588302	1			T33	12		T34	24		T1	22
all_values[16]	auto[0]	auto[1]	auto[1]	5476324	1			T33	16		T34	123		T1	6
all_values[16]	auto[1]	auto[0]	auto[1]	78533	1			T33	2		T1	4		T12	27
all_values[16]	auto[1]	auto[1]	auto[1]	77934	1			T12	37		T14	41		T18	173
all_values[17]	auto[0]	auto[0]	auto[0]	2753797	1			T31	278		T32	54		T33	30
all_values[17]	auto[0]	auto[0]	auto[1]	5486906	1			T33	7		T34	141		T1	11
all_values[17]	auto[0]	auto[1]	auto[0]	586387	1			T33	12		T34	16		T1	27
all_values[17]	auto[0]	auto[1]	auto[1]	5508675	1			T33	10		T34	156		T1	15
all_values[17]	auto[1]	auto[0]	auto[1]	78369	1			T33	2		T1	3		T12	34
all_values[17]	auto[1]	auto[1]	auto[1]	78028	1			T1	1		T12	50		T14	34
all_values[18]	auto[0]	auto[0]	auto[0]	2747480	1			T31	278		T32	54		T33	34
all_values[18]	auto[0]	auto[0]	auto[1]	5508801	1			T33	13		T34	101		T1	25
all_values[18]	auto[0]	auto[1]	auto[0]	593231	1			T33	5		T34	38		T1	15
all_values[18]	auto[0]	auto[1]	auto[1]	5486063	1			T33	6		T34	184		T1	12
all_values[18]	auto[1]	auto[0]	auto[1]	78663	1			T33	2		T1	3		T12	27
all_values[18]	auto[1]	auto[1]	auto[1]	77924	1			T33	1		T1	1		T12	37
all_values[19]	auto[0]	auto[0]	auto[0]	2746573	1			T31	278		T32	54		T33	29
all_values[19]	auto[0]	auto[0]	auto[1]	5522599	1			T33	14		T34	100		T1	28
all_values[19]	auto[0]	auto[1]	auto[0]	589086	1			T33	10		T34	40		T1	24
all_values[19]	auto[0]	auto[1]	auto[1]	5476737	1			T33	6		T34	172		T1	14
all_values[19]	auto[1]	auto[0]	auto[1]	78856	1			T33	1		T1	3		T12	35
all_values[19]	auto[1]	auto[1]	auto[1]	78311	1			T33	1		T1	3		T12	31
all_values[20]	auto[0]	auto[0]	auto[0]	2757233	1			T31	278		T32	54		T33	37
all_values[20]	auto[0]	auto[0]	auto[1]	5493897	1			T33	15		T34	125		T1	30
all_values[20]	auto[0]	auto[1]	auto[0]	590978	1			T33	6		T34	20		T1	10
all_values[20]	auto[0]	auto[1]	auto[1]	5494006	1			T34	194		T1	11		T12	720
all_values[20]	auto[1]	auto[0]	auto[1]	78086	1			T33	3		T1	6		T12	36
all_values[20]	auto[1]	auto[1]	auto[1]	77962	1			T1	1		T12	33		T14	31
all_values[21]	auto[0]	auto[0]	auto[0]	2754801	1			T31	278		T32	54		T33	25
all_values[21]	auto[0]	auto[0]	auto[1]	5511013	1			T33	15		T34	128		T1	13
all_values[21]	auto[0]	auto[1]	auto[0]	588591	1			T33	11		T34	27		T1	11
all_values[21]	auto[0]	auto[1]	auto[1]	5481230	1			T33	9		T34	172		T1	26
all_values[21]	auto[1]	auto[0]	auto[1]	78670	1			T33	1		T1	1		T12	32
all_values[21]	auto[1]	auto[1]	auto[1]	77857	1			T12	36		T14	42		T16	1
all_values[22]	auto[0]	auto[0]	auto[0]	2740028	1			T31	278		T32	54		T33	31
all_values[22]	auto[0]	auto[0]	auto[1]	5476449	1			T33	13		T34	159		T1	38
all_values[22]	auto[0]	auto[1]	auto[0]	594584	1			T33	12		T34	51		T1	15
all_values[22]	auto[0]	auto[1]	auto[1]	5524399	1			T33	3		T34	118		T1	6
all_values[22]	auto[1]	auto[0]	auto[1]	78436	1			T33	2		T1	1		T12	25
all_values[22]	auto[1]	auto[1]	auto[1]	78266	1			T1	1		T12	36		T14	31
all_values[23]	auto[0]	auto[0]	auto[0]	2759875	1			T31	278		T32	54		T33	30
all_values[23]	auto[0]	auto[0]	auto[1]	5515394	1			T33	9		T34	144		T1	13
all_values[23]	auto[0]	auto[1]	auto[0]	600030	1			T33	13		T34	24		T1	7
all_values[23]	auto[0]	auto[1]	auto[1]	5460545	1			T33	6		T34	172		T1	7
all_values[23]	auto[1]	auto[0]	auto[1]	78407	1			T33	3		T1	3		T12	30
all_values[23]	auto[1]	auto[1]	auto[1]	77911	1			T1	1		T12	29		T14	40
all_values[24]	auto[0]	auto[0]	auto[0]	2757982	1			T31	278		T32	54		T33	37
all_values[24]	auto[0]	auto[0]	auto[1]	5490383	1			T33	12		T34	133		T1	27
all_values[24]	auto[0]	auto[1]	auto[0]	594450	1			T33	5		T34	13		T1	13
all_values[24]	auto[0]	auto[1]	auto[1]	5492954	1			T33	5		T34	181		T1	20
all_values[24]	auto[1]	auto[0]	auto[1]	78789	1			T33	2		T1	3		T12	26
all_values[24]	auto[1]	auto[1]	auto[1]	77604	1			T1	1		T12	30		T14	48
all_values[25]	auto[0]	auto[0]	auto[0]	2751800	1			T31	278		T32	54		T33	28
all_values[25]	auto[0]	auto[0]	auto[1]	5513274	1			T33	14		T34	169		T1	31
all_values[25]	auto[0]	auto[1]	auto[0]	583251	1			T33	9		T34	1		T1	11
all_values[25]	auto[0]	auto[1]	auto[1]	5487309	1			T33	8		T34	172		T1	15
all_values[25]	auto[1]	auto[0]	auto[1]	78004	1			T33	2		T1	4		T12	43
all_values[25]	auto[1]	auto[1]	auto[1]	78524	1			T1	2		T12	34		T14	35
all_values[26]	auto[0]	auto[0]	auto[0]	2764860	1			T31	278		T32	54		T33	27
all_values[26]	auto[0]	auto[0]	auto[1]	5486232	1			T33	10		T34	130		T1	30
all_values[26]	auto[0]	auto[1]	auto[0]	586595	1			T33	12		T34	20		T1	28
all_values[26]	auto[0]	auto[1]	auto[1]	5498436	1			T33	11		T34	186		T1	5
all_values[26]	auto[1]	auto[0]	auto[1]	78396	1			T33	1		T1	3		T12	36
all_values[26]	auto[1]	auto[1]	auto[1]	77643	1			T12	34		T14	27		T16	1
all_values[27]	auto[0]	auto[0]	auto[0]	2753759	1			T31	278		T32	54		T33	33
all_values[27]	auto[0]	auto[0]	auto[1]	5514166	1			T33	5		T34	156		T1	8
all_values[27]	auto[0]	auto[1]	auto[0]	583093	1			T33	6		T34	28		T1	14
all_values[27]	auto[0]	auto[1]	auto[1]	5484261	1			T33	16		T34	157		T1	29
all_values[27]	auto[1]	auto[0]	auto[1]	78836	1			T1	3		T12	40		T14	45
all_values[27]	auto[1]	auto[1]	auto[1]	78047	1			T33	1		T12	34		T14	24
all_values[28]	auto[0]	auto[0]	auto[0]	2757721	1			T31	278		T32	54		T33	28
all_values[28]	auto[0]	auto[0]	auto[1]	5502603	1			T33	18		T34	166		T1	26
all_values[28]	auto[0]	auto[1]	auto[0]	590150	1			T33	3		T34	43		T1	36
all_values[28]	auto[0]	auto[1]	auto[1]	5484745	1			T33	10		T34	116		T1	8
all_values[28]	auto[1]	auto[0]	auto[1]	78440	1			T33	2		T1	1		T12	23
all_values[28]	auto[1]	auto[1]	auto[1]	78503	1			T1	4		T12	40		T14	33
all_values[29]	auto[0]	auto[0]	auto[0]	2764542	1			T31	278		T32	54		T33	41
all_values[29]	auto[0]	auto[0]	auto[1]	5517568	1			T33	3		T34	135		T1	38
all_values[29]	auto[0]	auto[1]	auto[0]	591615	1			T33	12		T34	30		T1	10
all_values[29]	auto[0]	auto[1]	auto[1]	5461788	1			T33	4		T34	140		T1	14
all_values[29]	auto[1]	auto[0]	auto[1]	78370	1			T33	1		T1	4		T12	34
all_values[29]	auto[1]	auto[1]	auto[1]	78279	1			T12	34		T14	32		T18	171
all_values[30]	auto[0]	auto[0]	auto[0]	2754824	1			T31	278		T32	54		T33	34
all_values[30]	auto[0]	auto[0]	auto[1]	5501154	1			T33	14		T34	133		T1	29
all_values[30]	auto[0]	auto[1]	auto[0]	588968	1			T33	4		T34	29		T1	11
all_values[30]	auto[0]	auto[1]	auto[1]	5491076	1			T33	6		T34	172		T1	5
all_values[30]	auto[1]	auto[0]	auto[1]	78523	1			T33	2		T1	4		T12	32
all_values[30]	auto[1]	auto[1]	auto[1]	77617	1			T33	1		T12	40		T14	44
all_values[31]	auto[0]	auto[0]	auto[0]	2756446	1			T31	278		T32	54		T33	26
all_values[31]	auto[0]	auto[0]	auto[1]	5512653	1			T33	15		T34	146		T1	17
all_values[31]	auto[0]	auto[1]	auto[0]	590588	1			T33	11		T34	35		T1	20
all_values[31]	auto[0]	auto[1]	auto[1]	5476082	1			T33	7		T34	130		T1	26
all_values[31]	auto[1]	auto[0]	auto[1]	78796	1			T33	2		T1	4		T12	40
all_values[31]	auto[1]	auto[1]	auto[1]	77597	1			T1	2		T12	38		T14	39

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal