Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[1]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[2]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[3]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[4]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[5]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[6]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[7]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[8]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[9]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[10]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[11]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[12]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[13]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[14]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[15]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[16]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[17]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[18]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[19]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[20]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[21]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[22]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[23]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[24]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[25]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[26]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[27]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[28]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[29]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[30]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[31]	14293497	1			T31	535		T32	96		T33	98

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270679172

1

T31

13435

T32

735

T33

1224

auto[1]

186712732

1

T31

3685

T32

2337

T33

1912

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

366827116

1

T31

12793

T32

2834

T33

2719

auto[1]

90564788

1

T31

4327

T32

238

T33

417

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

340497731

1

T31

8573

T32

1961

T33

2331

auto[1]

116894173

1

T31

8547

T32

1111

T33

805

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5270256	1			T31	157		T32	16		T33	25
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3937793	1			T31	20		T32	62		T33	32
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1421716	1			T31	66		T32	8		T33	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1771612	1			T31	186		T33	8		T1	27
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	479516	1			T31	35		T32	10		T33	16
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1412604	1			T31	71		T33	16		T1	19
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5259970	1			T31	198		T32	4		T33	17
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3948228	1			T31	25		T32	25		T33	48
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1427315	1			T31	52		T32	4		T33	2
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1767343	1			T31	204		T32	12		T33	6
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	476974	1			T31	16		T32	51		T33	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1413667	1			T31	40		T33	11		T1	13
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5270079	1			T31	156		T32	8		T33	31
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3941424	1			T31	16		T32	28		T33	49
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1426935	1			T31	103		T32	6		T33	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1765519	1			T31	179		T32	10		T33	13
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	478666	1			T31	24		T32	44		T33	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1410874	1			T31	57		T11	95		T12	324
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5271958	1			T31	173		T32	14		T33	29
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3943855	1			T31	29		T32	52		T33	40
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1423558	1			T31	103		T32	8		T33	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1765717	1			T31	155		T32	3		T33	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	476397	1			T31	24		T32	19		T33	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1412012	1			T31	51		T33	7		T1	8
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5270538	1			T31	242		T32	9		T33	20
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3943656	1			T31	21		T32	18		T33	28
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1421366	1			T31	60		T32	6		T33	8
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1767420	1			T31	141		T32	6		T33	16
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	479537	1			T31	19		T32	57		T33	15
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1410980	1			T31	52		T33	11		T1	12
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5264300	1			T31	196		T32	6		T33	26
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3949435	1			T31	24		T32	23		T33	49
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1425156	1			T31	93		T32	4		T33	6
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1764100	1			T31	151		T32	15		T33	5
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	476073	1			T31	19		T32	48		T33	6
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1414433	1			T31	52		T33	6		T1	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5264577	1			T31	152		T32	15		T33	17
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3947664	1			T31	24		T32	71		T33	55
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1427837	1			T31	96		T32	8		T33	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1761121	1			T31	181		T1	32		T11	42
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	479196	1			T31	17		T32	2		T33	13
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1413102	1			T31	65		T33	8		T1	11
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5281847	1			T31	229		T32	15		T33	25
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3935823	1			T31	34		T32	60		T33	36
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1423913	1			T31	86		T32	12		T33	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1765874	1			T31	109		T32	2		T33	13
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	478530	1			T31	17		T32	7		T33	11
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1407510	1			T31	60		T33	9		T1	6
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5274263	1			T31	154		T32	16		T33	15
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3940968	1			T31	35		T32	66		T33	53
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1425006	1			T31	41		T32	4		T1	3
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1764839	1			T31	159		T33	1		T1	9
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	475824	1			T31	28		T32	10		T33	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1412597	1			T31	118		T33	15		T1	24
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5265384	1			T31	94		T32	15		T33	16
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3956384	1			T31	20		T32	67		T33	33
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1426671	1			T31	25		T32	2		T33	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1760273	1			T31	291		T32	1		T33	9
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	476827	1			T31	31		T32	11		T33	19
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1407958	1			T31	74		T33	17		T1	7
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5268580	1			T31	195		T32	7		T33	14
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3949001	1			T31	26		T32	23		T33	45
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1419236	1			T31	74		T32	2		T1	17
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1766879	1			T31	169		T32	11		T33	9
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	477342	1			T31	17		T32	49		T33	18
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1412459	1			T31	54		T32	4		T33	12
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5263787	1			T31	201		T32	22		T33	26
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3950290	1			T31	34		T32	62		T33	39
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1422829	1			T31	57		T32	10		T33	11
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1765791	1			T31	157		T1	45		T11	29
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	480423	1			T31	22		T32	2		T33	10
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1410377	1			T31	64		T33	12		T1	12
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5267186	1			T31	203		T32	15		T33	37
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3949302	1			T31	34		T32	74		T33	29
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1421433	1			T31	76		T32	6		T11	61
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1766337	1			T31	141		T33	2		T1	52
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	477969	1			T31	11		T32	1		T33	9
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1411270	1			T31	70		T33	21		T1	5
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5263550	1			T31	195		T32	11		T33	35
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3953655	1			T31	24		T32	70		T33	47
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1418590	1			T31	91		T32	4		T1	8
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1767302	1			T31	139		T32	1		T33	5
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	475683	1			T31	27		T32	10		T33	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1414717	1			T31	59		T33	2		T1	7
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5277758	1			T31	195		T32	13		T33	19
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3936690	1			T31	30		T32	70		T33	47
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1426184	1			T31	68		T32	12		T33	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1761806	1			T31	168		T33	9		T1	27
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	476864	1			T31	20		T32	1		T33	7
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1414195	1			T31	54		T33	12		T1	17
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5266394	1			T31	152		T32	6		T33	47
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3955149	1			T31	29		T32	30		T33	14
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1429262	1			T31	66		T32	6		T33	12
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1756851	1			T31	200		T32	8		T33	10
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	473816	1			T31	24		T32	42		T33	12
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1412025	1			T31	64		T32	4		T33	3
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5273432	1			T31	148		T32	7		T33	31
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3951321	1			T31	24		T32	22		T33	41
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1419262	1			T31	82		T32	8		T1	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1765614	1			T31	198		T32	10		T33	16
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	479991	1			T31	28		T32	43		T33	6
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1403877	1			T31	55		T32	6		T33	4
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5269093	1			T31	163		T32	6		T33	11
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3955226	1			T31	25		T32	19		T33	68
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1421884	1			T31	64		T32	8		T1	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1766329	1			T31	213		T32	12		T33	7
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	480454	1			T31	20		T32	47		T33	6
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1400511	1			T31	50		T32	4		T33	6
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5268612	1			T31	183		T32	7		T33	20
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3954279	1			T31	20		T32	24		T33	54
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1418716	1			T31	54		T32	2		T33	6
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1764941	1			T31	191		T32	9		T33	12
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	478358	1			T31	29		T32	48		T33	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1408591	1			T31	58		T32	6		T33	4
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5276303	1			T31	180		T32	11		T33	35
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3946680	1			T31	28		T32	66		T33	23
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1414422	1			T31	64		T32	6		T33	11
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1766683	1			T31	170		T32	3		T33	15
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	480944	1			T31	25		T32	10		T33	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1408465	1			T31	68		T33	7		T1	5
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5279282	1			T31	125		T32	11		T33	23
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3944641	1			T31	18		T32	71		T33	63
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1414436	1			T31	61		T32	8		T33	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1772378	1			T31	189		T33	2		T1	32
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	477841	1			T31	39		T32	6		T33	6
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1404919	1			T31	103		T33	2		T1	9
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5273218	1			T31	177		T32	5		T33	21
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3943924	1			T31	16		T32	23		T33	32
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1419418	1			T31	61		T32	8		T33	8
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1769037	1			T31	193		T32	10		T33	18
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	479287	1			T31	18		T32	50		T33	13
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1408613	1			T31	70		T33	6		T1	8
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5281118	1			T31	212		T32	8		T33	28
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3950428	1			T31	26		T32	24		T33	31
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1415521	1			T31	87		T32	6		T33	7
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1764543	1			T31	141		T32	8		T33	5
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	478883	1			T31	18		T32	48		T33	12
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1403004	1			T31	51		T32	2		T33	15
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5255927	1			T31	125		T32	10		T33	36
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3960331	1			T31	19		T32	44		T33	42
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1419704	1			T31	65		T32	4		T33	14
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1772954	1			T31	178		T32	8		T33	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	478795	1			T31	34		T32	28		T33	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1405786	1			T31	114		T32	2		T33	2
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5279839	1			T31	124		T32	5		T33	36
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3946759	1			T31	14		T32	33		T33	28
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1418352	1			T31	42		T32	4		T33	2
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1764582	1			T31	242		T32	12		T33	2
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	478549	1			T31	45		T32	40		T33	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1405416	1			T31	68		T32	2		T33	20
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5285064	1			T31	205		T32	15		T33	37
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3941295	1			T31	30		T32	52		T33	34
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1425469	1			T31	70		T32	8		T33	8
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1759580	1			T31	160		T32	5		T33	5
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	475669	1			T31	10		T32	16		T33	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1406420	1			T31	60		T33	8		T11	95
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5271647	1			T31	180		T32	6		T33	14
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3948482	1			T31	20		T32	24		T33	61
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1413699	1			T31	83		T32	6		T33	4
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1769522	1			T31	184		T32	15		T33	5
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	479689	1			T31	11		T32	41		T33	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1410458	1			T31	57		T32	4		T33	8
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5281338	1			T31	201		T32	23		T33	35
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3947377	1			T31	35		T32	65		T33	32
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1415869	1			T31	60		T32	8		T1	6
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1766389	1			T31	156		T33	16		T1	30
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	478505	1			T31	19		T33	7		T1	21
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1404019	1			T31	64		T33	8		T1	7
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5267197	1			T31	205		T32	7		T33	35
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3956110	1			T31	13		T32	34		T33	55
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1419699	1			T31	40		T32	8		T33	5
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1767241	1			T31	190		T32	10		T33	1
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	479495	1			T31	30		T32	35		T33	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1403755	1			T31	57		T32	2		T1	7
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5270538	1			T31	147		T32	5		T33	32
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3949318	1			T31	23		T32	34		T33	25
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1416906	1			T31	45		T32	2		T33	12
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1770382	1			T31	189		T32	13		T33	10
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	480298	1			T31	26		T32	40		T33	10
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1406055	1			T31	105		T32	2		T33	9
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5273247	1			T31	163		T32	6		T33	13
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3949283	1			T31	21		T32	21		T33	63
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1422842	1			T31	80		T32	6		T33	4
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1765129	1			T31	152		T32	15		T33	13
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	475015	1			T31	33		T32	46		T33	3
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1407981	1			T31	86		T32	2		T33	2
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5280578	1			T31	176		T32	13		T33	21
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3943236	1			T31	27		T32	69		T33	60
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1419658	1			T31	68		T32	4		T1	2
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1765360	1			T31	170		T32	1		T33	4
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	481391	1			T31	21		T32	9		T33	7
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1403274	1			T31	73		T33	6		T1	17

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal