Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[1]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[2]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[3]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[4]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[5]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[6]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[7]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[8]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[9]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[10]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[11]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[12]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[13]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[14]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[15]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[16]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[17]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[18]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[19]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[20]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[21]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[22]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[23]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[24]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[25]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[26]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[27]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[28]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[29]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[30]	14293497	1			T31	535		T32	96		T33	98
bins_for_gpio_bits[31]	14293497	1			T31	535		T32	96		T33	98

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270679172

1

T31

13435

T32

735

T33

1224

auto[1]

186712732

1

T31

3685

T32

2337

T33

1912

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270672955

1

T31

13435

T32

735

T33

1225

auto[1]

186718949

1

T31

3685

T32

2337

T33

1911

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8208721	1			T31	396		T32	21		T33	34
bins_for_gpio_bits[0]	auto[0]	auto[1]	254688	1			T31	13		T32	3		T1	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	254863	1			T31	13		T32	3		T11	17
bins_for_gpio_bits[0]	auto[1]	auto[1]	5575225	1			T31	113		T32	69		T33	64
bins_for_gpio_bits[1]	auto[0]	auto[0]	8199796	1			T31	443		T32	19		T33	24
bins_for_gpio_bits[1]	auto[0]	auto[1]	254647	1			T31	11		T32	1		T33	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	254832	1			T31	11		T32	1		T33	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	5584222	1			T31	70		T32	75		T33	72
bins_for_gpio_bits[2]	auto[0]	auto[0]	8207786	1			T31	427		T32	22		T33	48
bins_for_gpio_bits[2]	auto[0]	auto[1]	254583	1			T31	11		T32	2		T11	16
bins_for_gpio_bits[2]	auto[1]	auto[0]	254747	1			T31	11		T32	2		T11	16
bins_for_gpio_bits[2]	auto[1]	auto[1]	5576381	1			T31	86		T32	70		T33	50
bins_for_gpio_bits[3]	auto[0]	auto[0]	8206544	1			T31	421		T32	22		T33	43
bins_for_gpio_bits[3]	auto[0]	auto[1]	254521	1			T31	10		T32	3		T11	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	254689	1			T31	10		T32	3		T11	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	5577743	1			T31	94		T32	68		T33	55
bins_for_gpio_bits[4]	auto[0]	auto[0]	8205154	1			T31	434		T32	19		T33	44
bins_for_gpio_bits[4]	auto[0]	auto[1]	253967	1			T31	9		T32	2		T11	14
bins_for_gpio_bits[4]	auto[1]	auto[0]	254170	1			T31	9		T32	2		T11	14
bins_for_gpio_bits[4]	auto[1]	auto[1]	5580206	1			T31	83		T32	73		T33	54
bins_for_gpio_bits[5]	auto[0]	auto[0]	8198262	1			T31	431		T32	24		T33	37
bins_for_gpio_bits[5]	auto[0]	auto[1]	255140	1			T31	9		T32	1		T11	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	255294	1			T31	9		T32	1		T11	10
bins_for_gpio_bits[5]	auto[1]	auto[1]	5584801	1			T31	86		T32	70		T33	61
bins_for_gpio_bits[6]	auto[0]	auto[0]	8198713	1			T31	417		T32	20		T33	22
bins_for_gpio_bits[6]	auto[0]	auto[1]	254638	1			T31	12		T32	3		T11	12
bins_for_gpio_bits[6]	auto[1]	auto[0]	254822	1			T31	12		T32	3		T11	12
bins_for_gpio_bits[6]	auto[1]	auto[1]	5585324	1			T31	94		T32	70		T33	76
bins_for_gpio_bits[7]	auto[0]	auto[0]	8217169	1			T31	416		T32	26		T33	42
bins_for_gpio_bits[7]	auto[0]	auto[1]	254285	1			T31	8		T32	3		T11	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	254465	1			T31	8		T32	3		T11	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	5567578	1			T31	103		T32	64		T33	56
bins_for_gpio_bits[8]	auto[0]	auto[0]	8209186	1			T31	338		T32	18		T33	16
bins_for_gpio_bits[8]	auto[0]	auto[1]	254670	1			T31	16		T32	2		T1	1
bins_for_gpio_bits[8]	auto[1]	auto[0]	254922	1			T31	16		T32	2		T1	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	5574719	1			T31	165		T32	74		T33	82
bins_for_gpio_bits[9]	auto[0]	auto[0]	8198405	1			T31	394		T32	17		T33	28
bins_for_gpio_bits[9]	auto[0]	auto[1]	253699	1			T31	16		T32	1		T33	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	253923	1			T31	16		T32	1		T33	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	5587470	1			T31	109		T32	77		T33	68
bins_for_gpio_bits[10]	auto[0]	auto[0]	8200559	1			T31	429		T32	19		T33	23
bins_for_gpio_bits[10]	auto[0]	auto[1]	253957	1			T31	9		T32	1		T11	13
bins_for_gpio_bits[10]	auto[1]	auto[0]	254136	1			T31	9		T32	1		T11	13
bins_for_gpio_bits[10]	auto[1]	auto[1]	5584845	1			T31	88		T32	75		T33	75
bins_for_gpio_bits[11]	auto[0]	auto[0]	8197893	1			T31	400		T32	28		T33	36
bins_for_gpio_bits[11]	auto[0]	auto[1]	254341	1			T31	15		T32	4		T33	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	254514	1			T31	15		T32	4		T33	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	5586749	1			T31	105		T32	60		T33	60
bins_for_gpio_bits[12]	auto[0]	auto[0]	8199832	1			T31	406		T32	19		T33	39
bins_for_gpio_bits[12]	auto[0]	auto[1]	254942	1			T31	14		T32	2		T11	10
bins_for_gpio_bits[12]	auto[1]	auto[0]	255124	1			T31	14		T32	2		T11	10
bins_for_gpio_bits[12]	auto[1]	auto[1]	5583599	1			T31	101		T32	73		T33	59
bins_for_gpio_bits[13]	auto[0]	auto[0]	8194664	1			T31	412		T32	14		T33	40
bins_for_gpio_bits[13]	auto[0]	auto[1]	254531	1			T31	13		T32	2		T11	19
bins_for_gpio_bits[13]	auto[1]	auto[0]	254778	1			T31	13		T32	2		T11	19
bins_for_gpio_bits[13]	auto[1]	auto[1]	5589524	1			T31	97		T32	78		T33	58
bins_for_gpio_bits[14]	auto[0]	auto[0]	8210742	1			T31	418		T32	20		T33	32
bins_for_gpio_bits[14]	auto[0]	auto[1]	254762	1			T31	13		T32	5		T11	16
bins_for_gpio_bits[14]	auto[1]	auto[0]	255006	1			T31	13		T32	5		T11	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	5572987	1			T31	91		T32	66		T33	66
bins_for_gpio_bits[15]	auto[0]	auto[0]	8197874	1			T31	407		T32	18		T33	69
bins_for_gpio_bits[15]	auto[0]	auto[1]	254469	1			T31	11		T32	2		T11	18
bins_for_gpio_bits[15]	auto[1]	auto[0]	254633	1			T31	11		T32	2		T11	18
bins_for_gpio_bits[15]	auto[1]	auto[1]	5586521	1			T31	106		T32	74		T33	29
bins_for_gpio_bits[16]	auto[0]	auto[0]	8203875	1			T31	415		T32	22		T33	47
bins_for_gpio_bits[16]	auto[0]	auto[1]	254258	1			T31	13		T32	3		T1	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	254433	1			T31	13		T32	3		T1	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	5580931	1			T31	94		T32	68		T33	51
bins_for_gpio_bits[17]	auto[0]	auto[0]	8203421	1			T31	426		T32	24		T33	18
bins_for_gpio_bits[17]	auto[0]	auto[1]	253716	1			T31	14		T32	2		T11	11
bins_for_gpio_bits[17]	auto[1]	auto[0]	253885	1			T31	14		T32	2		T1	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	5582475	1			T31	81		T32	68		T33	80
bins_for_gpio_bits[18]	auto[0]	auto[0]	8197994	1			T31	418		T32	17		T33	37
bins_for_gpio_bits[18]	auto[0]	auto[1]	254060	1			T31	10		T32	1		T33	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	254275	1			T31	10		T32	1		T33	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	5587168	1			T31	97		T32	77		T33	59
bins_for_gpio_bits[19]	auto[0]	auto[0]	8203270	1			T31	405		T32	17		T33	61
bins_for_gpio_bits[19]	auto[0]	auto[1]	253953	1			T31	9		T32	3		T11	19
bins_for_gpio_bits[19]	auto[1]	auto[0]	254138	1			T31	9		T32	3		T11	19
bins_for_gpio_bits[19]	auto[1]	auto[1]	5582136	1			T31	112		T32	73		T33	37
bins_for_gpio_bits[20]	auto[0]	auto[0]	8211233	1			T31	362		T32	17		T33	27
bins_for_gpio_bits[20]	auto[0]	auto[1]	254662	1			T31	13		T32	2		T11	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	254863	1			T31	13		T32	2		T1	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	5572739	1			T31	147		T32	75		T33	71
bins_for_gpio_bits[21]	auto[0]	auto[0]	8206778	1			T31	417		T32	21		T33	46
bins_for_gpio_bits[21]	auto[0]	auto[1]	254719	1			T31	14		T32	2		T33	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	254895	1			T31	14		T32	2		T33	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	5577105	1			T31	90		T32	71		T33	50
bins_for_gpio_bits[22]	auto[0]	auto[0]	8206982	1			T31	431		T32	19		T33	38
bins_for_gpio_bits[22]	auto[0]	auto[1]	254014	1			T31	9		T32	3		T33	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	254200	1			T31	9		T32	3		T33	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	5578301	1			T31	86		T32	71		T33	56
bins_for_gpio_bits[23]	auto[0]	auto[0]	8193628	1			T31	351		T32	20		T33	52
bins_for_gpio_bits[23]	auto[0]	auto[1]	254747	1			T31	17		T32	2		T1	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	254957	1			T31	17		T32	2		T1	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	5590165	1			T31	150		T32	72		T33	46
bins_for_gpio_bits[24]	auto[0]	auto[0]	8208513	1			T31	392		T32	19		T33	40
bins_for_gpio_bits[24]	auto[0]	auto[1]	254063	1			T31	16		T32	2		T11	14
bins_for_gpio_bits[24]	auto[1]	auto[0]	254260	1			T31	16		T32	2		T11	14
bins_for_gpio_bits[24]	auto[1]	auto[1]	5576661	1			T31	111		T32	73		T33	58
bins_for_gpio_bits[25]	auto[0]	auto[0]	8215582	1			T31	421		T32	24		T33	50
bins_for_gpio_bits[25]	auto[0]	auto[1]	254311	1			T31	14		T32	4		T11	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	254531	1			T31	14		T32	4		T11	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	5569073	1			T31	86		T32	64		T33	48
bins_for_gpio_bits[26]	auto[0]	auto[0]	8199986	1			T31	437		T32	25		T33	23
bins_for_gpio_bits[26]	auto[0]	auto[1]	254686	1			T31	10		T32	2		T1	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	254882	1			T31	10		T32	2		T1	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	5583943	1			T31	78		T32	67		T33	75
bins_for_gpio_bits[27]	auto[0]	auto[0]	8208870	1			T31	403		T32	27		T33	51
bins_for_gpio_bits[27]	auto[0]	auto[1]	254532	1			T31	14		T32	4		T11	15
bins_for_gpio_bits[27]	auto[1]	auto[0]	254726	1			T31	14		T32	4		T11	15
bins_for_gpio_bits[27]	auto[1]	auto[1]	5575369	1			T31	104		T32	61		T33	47
bins_for_gpio_bits[28]	auto[0]	auto[0]	8199739	1			T31	424		T32	22		T33	41
bins_for_gpio_bits[28]	auto[0]	auto[1]	254223	1			T31	11		T32	3		T11	16
bins_for_gpio_bits[28]	auto[1]	auto[0]	254398	1			T31	11		T32	3		T11	16
bins_for_gpio_bits[28]	auto[1]	auto[1]	5585137	1			T31	89		T32	68		T33	57
bins_for_gpio_bits[29]	auto[0]	auto[0]	8202666	1			T31	369		T32	19		T33	53
bins_for_gpio_bits[29]	auto[0]	auto[1]	254918	1			T31	12		T32	1		T33	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	255160	1			T31	12		T32	1		T33	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	5580753	1			T31	142		T32	75		T33	42
bins_for_gpio_bits[30]	auto[0]	auto[0]	8205582	1			T31	384		T32	26		T33	30
bins_for_gpio_bits[30]	auto[0]	auto[1]	255428	1			T31	11		T32	1		T11	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	255636	1			T31	11		T32	1		T11	18
bins_for_gpio_bits[30]	auto[1]	auto[1]	5576851	1			T31	129		T32	68		T33	68
bins_for_gpio_bits[31]	auto[0]	auto[0]	8211055	1			T31	400		T32	16		T33	25
bins_for_gpio_bits[31]	auto[0]	auto[1]	254351	1			T31	14		T32	2		T1	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	254541	1			T31	14		T32	2		T11	16
bins_for_gpio_bits[31]	auto[1]	auto[1]	5573550	1			T31	107		T32	76		T33	73