Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8338463 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
41 |
| auto[1] |
6153699 |
1 |
|
|
T33 |
20 |
|
T34 |
160 |
|
T1 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13701418 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
790744 |
1 |
|
|
T34 |
14 |
|
T12 |
44 |
|
T14 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8358034 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
6134128 |
1 |
|
|
T34 |
195 |
|
T1 |
27 |
|
T12 |
977 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2666520 |
1 |
|
|
T34 |
101 |
|
T1 |
27 |
|
T12 |
469 |
| auto[1] |
auto[0] |
auto[1] |
394825 |
1 |
|
|
T34 |
10 |
|
T12 |
21 |
|
T14 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2676864 |
1 |
|
|
T34 |
80 |
|
T12 |
464 |
|
T14 |
379 |
| auto[1] |
auto[1] |
auto[1] |
395919 |
1 |
|
|
T34 |
4 |
|
T12 |
23 |
|
T14 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8308893 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
39 |
| auto[1] |
6183269 |
1 |
|
|
T33 |
22 |
|
T34 |
146 |
|
T1 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13701921 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
790241 |
1 |
|
|
T34 |
14 |
|
T12 |
38 |
|
T14 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8355334 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
55 |
| auto[1] |
6136828 |
1 |
|
|
T33 |
6 |
|
T34 |
194 |
|
T1 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2667564 |
1 |
|
|
T33 |
6 |
|
T34 |
113 |
|
T1 |
28 |
| auto[1] |
auto[0] |
auto[1] |
393758 |
1 |
|
|
T34 |
6 |
|
T12 |
20 |
|
T14 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2679023 |
1 |
|
|
T34 |
67 |
|
T12 |
458 |
|
T14 |
390 |
| auto[1] |
auto[1] |
auto[1] |
396483 |
1 |
|
|
T34 |
8 |
|
T12 |
18 |
|
T14 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8351323 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
42 |
| auto[1] |
6140839 |
1 |
|
|
T33 |
19 |
|
T34 |
170 |
|
T1 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13698145 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
794017 |
1 |
|
|
T34 |
8 |
|
T1 |
1 |
|
T12 |
30 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8330183 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
55 |
| auto[1] |
6161979 |
1 |
|
|
T33 |
6 |
|
T34 |
137 |
|
T1 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2682011 |
1 |
|
|
T34 |
49 |
|
T1 |
23 |
|
T12 |
321 |
| auto[1] |
auto[0] |
auto[1] |
397686 |
1 |
|
|
T34 |
4 |
|
T1 |
1 |
|
T12 |
18 |
| auto[1] |
auto[1] |
auto[0] |
2685951 |
1 |
|
|
T33 |
6 |
|
T34 |
80 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[1] |
396331 |
1 |
|
|
T34 |
4 |
|
T12 |
12 |
|
T14 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8324585 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
50 |
| auto[1] |
6167577 |
1 |
|
|
T33 |
11 |
|
T34 |
116 |
|
T1 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13696771 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
795391 |
1 |
|
|
T34 |
9 |
|
T1 |
2 |
|
T12 |
29 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8323812 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
46 |
| auto[1] |
6168350 |
1 |
|
|
T33 |
15 |
|
T34 |
117 |
|
T1 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2682702 |
1 |
|
|
T33 |
9 |
|
T34 |
82 |
|
T1 |
32 |
| auto[1] |
auto[0] |
auto[1] |
395663 |
1 |
|
|
T34 |
6 |
|
T1 |
2 |
|
T12 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2690257 |
1 |
|
|
T33 |
6 |
|
T34 |
26 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
399728 |
1 |
|
|
T34 |
3 |
|
T12 |
13 |
|
T14 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8388902 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
42 |
| auto[1] |
6103260 |
1 |
|
|
T33 |
19 |
|
T34 |
187 |
|
T1 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13691696 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
800466 |
1 |
|
|
T34 |
8 |
|
T1 |
1 |
|
T12 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8283328 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
57 |
| auto[1] |
6208834 |
1 |
|
|
T33 |
4 |
|
T34 |
137 |
|
T1 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2744421 |
1 |
|
|
T33 |
3 |
|
T34 |
80 |
|
T1 |
20 |
| auto[1] |
auto[0] |
auto[1] |
406027 |
1 |
|
|
T34 |
6 |
|
T1 |
1 |
|
T12 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2663947 |
1 |
|
|
T33 |
1 |
|
T34 |
49 |
|
T1 |
10 |
| auto[1] |
auto[1] |
auto[1] |
394439 |
1 |
|
|
T34 |
2 |
|
T12 |
31 |
|
T14 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8324193 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
37 |
| auto[1] |
6167969 |
1 |
|
|
T33 |
24 |
|
T34 |
205 |
|
T1 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13693335 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
798827 |
1 |
|
|
T34 |
8 |
|
T12 |
36 |
|
T14 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8308836 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
55 |
| auto[1] |
6183326 |
1 |
|
|
T33 |
6 |
|
T34 |
164 |
|
T1 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2694649 |
1 |
|
|
T34 |
62 |
|
T1 |
16 |
|
T12 |
294 |
| auto[1] |
auto[0] |
auto[1] |
399786 |
1 |
|
|
T34 |
2 |
|
T12 |
16 |
|
T14 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2689850 |
1 |
|
|
T33 |
6 |
|
T34 |
94 |
|
T12 |
370 |
| auto[1] |
auto[1] |
auto[1] |
399041 |
1 |
|
|
T34 |
6 |
|
T12 |
20 |
|
T14 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8322829 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
45 |
| auto[1] |
6169333 |
1 |
|
|
T33 |
16 |
|
T34 |
196 |
|
T1 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13694038 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
798124 |
1 |
|
|
T34 |
15 |
|
T1 |
1 |
|
T12 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8315163 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
51 |
| auto[1] |
6176999 |
1 |
|
|
T33 |
10 |
|
T34 |
222 |
|
T1 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2686841 |
1 |
|
|
T33 |
7 |
|
T34 |
109 |
|
T1 |
10 |
| auto[1] |
auto[0] |
auto[1] |
398063 |
1 |
|
|
T34 |
11 |
|
T1 |
1 |
|
T12 |
22 |
| auto[1] |
auto[1] |
auto[0] |
2692034 |
1 |
|
|
T33 |
3 |
|
T34 |
98 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[1] |
400061 |
1 |
|
|
T34 |
4 |
|
T12 |
18 |
|
T14 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8307265 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
43 |
| auto[1] |
6184897 |
1 |
|
|
T33 |
18 |
|
T34 |
152 |
|
T1 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13693038 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
799124 |
1 |
|
|
T34 |
9 |
|
T12 |
32 |
|
T14 |
37 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8303678 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
48 |
| auto[1] |
6188484 |
1 |
|
|
T33 |
13 |
|
T34 |
139 |
|
T1 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2686615 |
1 |
|
|
T33 |
8 |
|
T34 |
73 |
|
T1 |
26 |
| auto[1] |
auto[0] |
auto[1] |
397570 |
1 |
|
|
T34 |
5 |
|
T12 |
17 |
|
T14 |
23 |
| auto[1] |
auto[1] |
auto[0] |
2702745 |
1 |
|
|
T33 |
5 |
|
T34 |
57 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[1] |
401554 |
1 |
|
|
T34 |
4 |
|
T12 |
15 |
|
T14 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8349602 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
33 |
| auto[1] |
6142560 |
1 |
|
|
T33 |
28 |
|
T34 |
147 |
|
T1 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13695199 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
796963 |
1 |
|
|
T34 |
9 |
|
T1 |
2 |
|
T12 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8309310 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
57 |
| auto[1] |
6182852 |
1 |
|
|
T33 |
4 |
|
T34 |
201 |
|
T1 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2709015 |
1 |
|
|
T34 |
101 |
|
T1 |
26 |
|
T12 |
327 |
| auto[1] |
auto[0] |
auto[1] |
401781 |
1 |
|
|
T34 |
3 |
|
T1 |
1 |
|
T12 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2676874 |
1 |
|
|
T33 |
4 |
|
T34 |
91 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[1] |
395182 |
1 |
|
|
T34 |
6 |
|
T1 |
1 |
|
T12 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8319072 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
39 |
| auto[1] |
6173090 |
1 |
|
|
T33 |
22 |
|
T34 |
172 |
|
T1 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13701117 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
791045 |
1 |
|
|
T34 |
13 |
|
T12 |
35 |
|
T14 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8349790 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
6142372 |
1 |
|
|
T34 |
210 |
|
T1 |
31 |
|
T12 |
759 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2661496 |
1 |
|
|
T34 |
110 |
|
T1 |
21 |
|
T12 |
257 |
| auto[1] |
auto[0] |
auto[1] |
393358 |
1 |
|
|
T34 |
6 |
|
T12 |
19 |
|
T14 |
17 |
| auto[1] |
auto[1] |
auto[0] |
2689831 |
1 |
|
|
T34 |
87 |
|
T1 |
10 |
|
T12 |
467 |
| auto[1] |
auto[1] |
auto[1] |
397687 |
1 |
|
|
T34 |
7 |
|
T12 |
16 |
|
T14 |
24 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8334944 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
49 |
| auto[1] |
6157218 |
1 |
|
|
T33 |
12 |
|
T34 |
222 |
|
T1 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13699969 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
792193 |
1 |
|
|
T34 |
7 |
|
T12 |
22 |
|
T14 |
43 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8351474 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
55 |
| auto[1] |
6140688 |
1 |
|
|
T33 |
6 |
|
T34 |
164 |
|
T1 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2673019 |
1 |
|
|
T33 |
6 |
|
T34 |
59 |
|
T1 |
15 |
| auto[1] |
auto[0] |
auto[1] |
395758 |
1 |
|
|
T34 |
1 |
|
T12 |
14 |
|
T14 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2675476 |
1 |
|
|
T34 |
98 |
|
T1 |
10 |
|
T12 |
395 |
| auto[1] |
auto[1] |
auto[1] |
396435 |
1 |
|
|
T34 |
6 |
|
T12 |
8 |
|
T14 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8348028 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
44 |
| auto[1] |
6144134 |
1 |
|
|
T33 |
17 |
|
T34 |
212 |
|
T1 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13699287 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
792875 |
1 |
|
|
T34 |
19 |
|
T12 |
32 |
|
T14 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8344510 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
51 |
| auto[1] |
6147652 |
1 |
|
|
T33 |
10 |
|
T34 |
218 |
|
T1 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2691031 |
1 |
|
|
T33 |
3 |
|
T34 |
72 |
|
T1 |
4 |
| auto[1] |
auto[0] |
auto[1] |
397565 |
1 |
|
|
T34 |
3 |
|
T12 |
20 |
|
T14 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2663746 |
1 |
|
|
T33 |
7 |
|
T34 |
127 |
|
T1 |
10 |
| auto[1] |
auto[1] |
auto[1] |
395310 |
1 |
|
|
T34 |
16 |
|
T12 |
12 |
|
T14 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8325094 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
46 |
| auto[1] |
6167068 |
1 |
|
|
T33 |
15 |
|
T34 |
180 |
|
T1 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13698501 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
60 |
| auto[1] |
793661 |
1 |
|
|
T33 |
1 |
|
T34 |
11 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8340692 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
52 |
| auto[1] |
6151470 |
1 |
|
|
T33 |
9 |
|
T34 |
156 |
|
T1 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2693246 |
1 |
|
|
T33 |
8 |
|
T34 |
81 |
|
T1 |
15 |
| auto[1] |
auto[0] |
auto[1] |
398728 |
1 |
|
|
T33 |
1 |
|
T34 |
5 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2664563 |
1 |
|
|
T34 |
64 |
|
T1 |
12 |
|
T12 |
260 |
| auto[1] |
auto[1] |
auto[1] |
394933 |
1 |
|
|
T34 |
6 |
|
T12 |
15 |
|
T14 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8329216 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
55 |
| auto[1] |
6162946 |
1 |
|
|
T33 |
6 |
|
T34 |
214 |
|
T1 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13698710 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
60 |
| auto[1] |
793452 |
1 |
|
|
T33 |
1 |
|
T34 |
11 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8350944 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
46 |
| auto[1] |
6141218 |
1 |
|
|
T33 |
15 |
|
T34 |
155 |
|
T1 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2681641 |
1 |
|
|
T33 |
9 |
|
T34 |
75 |
|
T1 |
27 |
| auto[1] |
auto[0] |
auto[1] |
397753 |
1 |
|
|
T33 |
1 |
|
T34 |
3 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2666125 |
1 |
|
|
T33 |
5 |
|
T34 |
69 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[1] |
395699 |
1 |
|
|
T34 |
8 |
|
T1 |
1 |
|
T12 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8344484 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
41 |
| auto[1] |
6147678 |
1 |
|
|
T33 |
20 |
|
T34 |
199 |
|
T1 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13696233 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
60 |
| auto[1] |
795929 |
1 |
|
|
T33 |
1 |
|
T34 |
15 |
|
T12 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8321055 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
42 |
| auto[1] |
6171107 |
1 |
|
|
T33 |
19 |
|
T34 |
191 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2698983 |
1 |
|
|
T33 |
6 |
|
T34 |
88 |
|
T1 |
2 |
| auto[1] |
auto[0] |
auto[1] |
399889 |
1 |
|
|
T33 |
1 |
|
T34 |
9 |
|
T12 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2676195 |
1 |
|
|
T33 |
12 |
|
T34 |
88 |
|
T12 |
262 |
| auto[1] |
auto[1] |
auto[1] |
396040 |
1 |
|
|
T34 |
6 |
|
T12 |
10 |
|
T14 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8294913 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
46 |
| auto[1] |
6197249 |
1 |
|
|
T33 |
15 |
|
T34 |
169 |
|
T1 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13701506 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
790656 |
1 |
|
|
T34 |
6 |
|
T1 |
1 |
|
T12 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8357415 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
42 |
| auto[1] |
6134747 |
1 |
|
|
T33 |
19 |
|
T34 |
105 |
|
T1 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2672006 |
1 |
|
|
T33 |
14 |
|
T34 |
76 |
|
T1 |
17 |
| auto[1] |
auto[0] |
auto[1] |
395456 |
1 |
|
|
T34 |
4 |
|
T1 |
1 |
|
T12 |
17 |
| auto[1] |
auto[1] |
auto[0] |
2672085 |
1 |
|
|
T33 |
5 |
|
T34 |
23 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
395200 |
1 |
|
|
T34 |
2 |
|
T12 |
15 |
|
T14 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8353676 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
42 |
| auto[1] |
6138486 |
1 |
|
|
T33 |
19 |
|
T34 |
196 |
|
T1 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13702437 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
789725 |
1 |
|
|
T34 |
12 |
|
T12 |
37 |
|
T14 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8365261 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
6126901 |
1 |
|
|
T34 |
149 |
|
T1 |
7 |
|
T12 |
878 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2687218 |
1 |
|
|
T34 |
77 |
|
T1 |
4 |
|
T12 |
407 |
| auto[1] |
auto[0] |
auto[1] |
398144 |
1 |
|
|
T34 |
5 |
|
T12 |
11 |
|
T14 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2649958 |
1 |
|
|
T34 |
60 |
|
T1 |
3 |
|
T12 |
434 |
| auto[1] |
auto[1] |
auto[1] |
391581 |
1 |
|
|
T34 |
7 |
|
T12 |
26 |
|
T14 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8327154 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
51 |
| auto[1] |
6165008 |
1 |
|
|
T33 |
10 |
|
T34 |
194 |
|
T1 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13691938 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
800224 |
1 |
|
|
T34 |
13 |
|
T1 |
1 |
|
T12 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8300291 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
6191871 |
1 |
|
|
T34 |
135 |
|
T1 |
18 |
|
T12 |
894 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2706381 |
1 |
|
|
T34 |
66 |
|
T1 |
10 |
|
T12 |
494 |
| auto[1] |
auto[0] |
auto[1] |
401518 |
1 |
|
|
T34 |
8 |
|
T12 |
19 |
|
T14 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2685266 |
1 |
|
|
T34 |
56 |
|
T1 |
7 |
|
T12 |
362 |
| auto[1] |
auto[1] |
auto[1] |
398706 |
1 |
|
|
T34 |
5 |
|
T1 |
1 |
|
T12 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8343078 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
44 |
| auto[1] |
6149084 |
1 |
|
|
T33 |
17 |
|
T34 |
173 |
|
T1 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13693652 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
798510 |
1 |
|
|
T34 |
12 |
|
T12 |
41 |
|
T14 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8303437 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
42 |
| auto[1] |
6188725 |
1 |
|
|
T33 |
19 |
|
T34 |
169 |
|
T1 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2692239 |
1 |
|
|
T33 |
7 |
|
T34 |
66 |
|
T1 |
17 |
| auto[1] |
auto[0] |
auto[1] |
399248 |
1 |
|
|
T34 |
5 |
|
T12 |
28 |
|
T14 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2697976 |
1 |
|
|
T33 |
12 |
|
T34 |
91 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[1] |
399262 |
1 |
|
|
T34 |
7 |
|
T12 |
13 |
|
T14 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8329488 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
38 |
| auto[1] |
6162674 |
1 |
|
|
T33 |
23 |
|
T34 |
206 |
|
T1 |
33 |