Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8308893 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
39 |
| auto[1] |
6183269 |
1 |
|
|
T33 |
22 |
|
T34 |
146 |
|
T1 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11937504 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
58 |
| auto[1] |
2554658 |
1 |
|
|
T33 |
3 |
|
T34 |
153 |
|
T1 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8365391 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
44 |
| auto[1] |
6126771 |
1 |
|
|
T33 |
17 |
|
T34 |
260 |
|
T1 |
41 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1770500 |
1 |
|
|
T33 |
6 |
|
T34 |
69 |
|
T1 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1270492 |
1 |
|
|
T33 |
1 |
|
T34 |
74 |
|
T1 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1801613 |
1 |
|
|
T33 |
8 |
|
T34 |
38 |
|
T1 |
13 |
| auto[1] |
auto[1] |
auto[1] |
1284166 |
1 |
|
|
T33 |
2 |
|
T34 |
79 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |