Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8351323 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
42 |
| auto[1] |
6140839 |
1 |
|
|
T33 |
19 |
|
T34 |
170 |
|
T1 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11924740 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
55 |
| auto[1] |
2567422 |
1 |
|
|
T33 |
6 |
|
T34 |
114 |
|
T1 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8322068 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
51 |
| auto[1] |
6170094 |
1 |
|
|
T33 |
10 |
|
T34 |
216 |
|
T1 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1809302 |
1 |
|
|
T33 |
3 |
|
T34 |
45 |
|
T1 |
17 |
| auto[1] |
auto[0] |
auto[1] |
1290916 |
1 |
|
|
T33 |
1 |
|
T34 |
49 |
|
T1 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1793370 |
1 |
|
|
T33 |
1 |
|
T34 |
57 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1276506 |
1 |
|
|
T33 |
5 |
|
T34 |
65 |
|
T1 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |