Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8324585 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
50 |
| auto[1] |
6167577 |
1 |
|
|
T33 |
11 |
|
T34 |
116 |
|
T1 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11928398 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
50 |
| auto[1] |
2563764 |
1 |
|
|
T33 |
11 |
|
T34 |
73 |
|
T1 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8347045 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
50 |
| auto[1] |
6145117 |
1 |
|
|
T33 |
11 |
|
T34 |
141 |
|
T1 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1786721 |
1 |
|
|
T34 |
51 |
|
T1 |
16 |
|
T12 |
318 |
| auto[1] |
auto[0] |
auto[1] |
1279501 |
1 |
|
|
T33 |
3 |
|
T34 |
43 |
|
T1 |
13 |
| auto[1] |
auto[1] |
auto[0] |
1794632 |
1 |
|
|
T34 |
17 |
|
T1 |
6 |
|
T12 |
402 |
| auto[1] |
auto[1] |
auto[1] |
1284263 |
1 |
|
|
T33 |
8 |
|
T34 |
30 |
|
T12 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |