Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8388902 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
42 |
| auto[1] |
6103260 |
1 |
|
|
T33 |
19 |
|
T34 |
187 |
|
T1 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11925836 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
54 |
| auto[1] |
2566326 |
1 |
|
|
T33 |
7 |
|
T34 |
82 |
|
T1 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8318906 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
46 |
| auto[1] |
6173256 |
1 |
|
|
T33 |
15 |
|
T34 |
151 |
|
T1 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1832472 |
1 |
|
|
T33 |
2 |
|
T34 |
30 |
|
T1 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1297970 |
1 |
|
|
T33 |
1 |
|
T34 |
43 |
|
T1 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1774458 |
1 |
|
|
T33 |
6 |
|
T34 |
39 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1268356 |
1 |
|
|
T33 |
6 |
|
T34 |
39 |
|
T1 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |