Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13698264 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
793898 |
1 |
|
|
T34 |
12 |
|
T12 |
45 |
|
T14 |
37 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8334051 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
52 |
| auto[1] |
6158111 |
1 |
|
|
T33 |
9 |
|
T34 |
194 |
|
T1 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2693851 |
1 |
|
|
T33 |
5 |
|
T34 |
74 |
|
T1 |
13 |
| auto[1] |
auto[0] |
auto[1] |
398936 |
1 |
|
|
T34 |
4 |
|
T12 |
18 |
|
T14 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2670362 |
1 |
|
|
T33 |
4 |
|
T34 |
108 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[1] |
394962 |
1 |
|
|
T34 |
8 |
|
T12 |
27 |
|
T14 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |