Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8324193 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
37 |
| auto[1] |
6167969 |
1 |
|
|
T33 |
24 |
|
T34 |
205 |
|
T1 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11928177 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
2563985 |
1 |
|
|
T34 |
116 |
|
T1 |
5 |
|
T12 |
235 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8346616 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
6145546 |
1 |
|
|
T34 |
230 |
|
T1 |
18 |
|
T12 |
904 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1789959 |
1 |
|
|
T34 |
44 |
|
T1 |
13 |
|
T12 |
303 |
| auto[1] |
auto[0] |
auto[1] |
1286372 |
1 |
|
|
T34 |
47 |
|
T1 |
5 |
|
T12 |
117 |
| auto[1] |
auto[1] |
auto[0] |
1791602 |
1 |
|
|
T34 |
70 |
|
T12 |
366 |
|
T14 |
120 |
| auto[1] |
auto[1] |
auto[1] |
1277613 |
1 |
|
|
T34 |
69 |
|
T12 |
118 |
|
T14 |
423 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |