Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8307265 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
43 |
| auto[1] |
6184897 |
1 |
|
|
T33 |
18 |
|
T34 |
152 |
|
T1 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11930548 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
2561614 |
1 |
|
|
T34 |
47 |
|
T12 |
216 |
|
T14 |
768 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8337117 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
43 |
| auto[1] |
6155045 |
1 |
|
|
T33 |
18 |
|
T34 |
187 |
|
T1 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1793009 |
1 |
|
|
T33 |
8 |
|
T34 |
74 |
|
T1 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1282455 |
1 |
|
|
T34 |
28 |
|
T12 |
119 |
|
T14 |
479 |
| auto[1] |
auto[1] |
auto[0] |
1800422 |
1 |
|
|
T33 |
10 |
|
T34 |
66 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1279159 |
1 |
|
|
T34 |
19 |
|
T12 |
97 |
|
T14 |
289 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |