Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8349602 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
33 |
| auto[1] |
6142560 |
1 |
|
|
T33 |
28 |
|
T34 |
147 |
|
T1 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11924397 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
53 |
| auto[1] |
2567765 |
1 |
|
|
T33 |
8 |
|
T34 |
54 |
|
T1 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8359426 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
46 |
| auto[1] |
6132736 |
1 |
|
|
T33 |
15 |
|
T34 |
135 |
|
T1 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1785132 |
1 |
|
|
T34 |
40 |
|
T1 |
8 |
|
T12 |
247 |
| auto[1] |
auto[0] |
auto[1] |
1285399 |
1 |
|
|
T33 |
2 |
|
T34 |
28 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1779839 |
1 |
|
|
T33 |
7 |
|
T34 |
41 |
|
T12 |
402 |
| auto[1] |
auto[1] |
auto[1] |
1282366 |
1 |
|
|
T33 |
6 |
|
T34 |
26 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |