Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8334944 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
49 |
| auto[1] |
6157218 |
1 |
|
|
T33 |
12 |
|
T34 |
222 |
|
T1 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11928333 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
60 |
| auto[1] |
2563829 |
1 |
|
|
T33 |
1 |
|
T34 |
49 |
|
T1 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8318058 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
54 |
| auto[1] |
6174104 |
1 |
|
|
T33 |
7 |
|
T34 |
184 |
|
T1 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1802005 |
1 |
|
|
T33 |
3 |
|
T34 |
41 |
|
T1 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1281186 |
1 |
|
|
T34 |
24 |
|
T1 |
10 |
|
T12 |
86 |
| auto[1] |
auto[1] |
auto[0] |
1808270 |
1 |
|
|
T33 |
3 |
|
T34 |
94 |
|
T12 |
344 |
| auto[1] |
auto[1] |
auto[1] |
1282643 |
1 |
|
|
T33 |
1 |
|
T34 |
25 |
|
T1 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |