Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8348028 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
44 |
| auto[1] |
6144134 |
1 |
|
|
T33 |
17 |
|
T34 |
212 |
|
T1 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11924572 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
2567590 |
1 |
|
|
T34 |
70 |
|
T1 |
5 |
|
T12 |
193 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8335474 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
53 |
| auto[1] |
6156688 |
1 |
|
|
T33 |
8 |
|
T34 |
178 |
|
T1 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1817437 |
1 |
|
|
T33 |
1 |
|
T34 |
42 |
|
T1 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1294856 |
1 |
|
|
T34 |
32 |
|
T1 |
3 |
|
T12 |
109 |
| auto[1] |
auto[1] |
auto[0] |
1771661 |
1 |
|
|
T33 |
7 |
|
T34 |
66 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1272734 |
1 |
|
|
T34 |
38 |
|
T1 |
2 |
|
T12 |
84 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |