Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8325094 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
46 |
| auto[1] |
6167068 |
1 |
|
|
T33 |
15 |
|
T34 |
180 |
|
T1 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11916066 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
53 |
| auto[1] |
2576096 |
1 |
|
|
T33 |
8 |
|
T34 |
42 |
|
T1 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8317778 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
44 |
| auto[1] |
6174384 |
1 |
|
|
T33 |
17 |
|
T34 |
158 |
|
T1 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1795061 |
1 |
|
|
T33 |
2 |
|
T34 |
64 |
|
T1 |
15 |
| auto[1] |
auto[0] |
auto[1] |
1284694 |
1 |
|
|
T33 |
5 |
|
T34 |
20 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1803227 |
1 |
|
|
T33 |
7 |
|
T34 |
52 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1291402 |
1 |
|
|
T33 |
3 |
|
T34 |
22 |
|
T1 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |