Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8329216 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
55 |
| auto[1] |
6162946 |
1 |
|
|
T33 |
6 |
|
T34 |
214 |
|
T1 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11937299 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
56 |
| auto[1] |
2554863 |
1 |
|
|
T33 |
5 |
|
T34 |
88 |
|
T1 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8356243 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
55 |
| auto[1] |
6135919 |
1 |
|
|
T33 |
6 |
|
T34 |
186 |
|
T1 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1791041 |
1 |
|
|
T33 |
1 |
|
T34 |
40 |
|
T1 |
15 |
| auto[1] |
auto[0] |
auto[1] |
1279366 |
1 |
|
|
T33 |
5 |
|
T34 |
29 |
|
T1 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1790015 |
1 |
|
|
T34 |
58 |
|
T1 |
2 |
|
T12 |
276 |
| auto[1] |
auto[1] |
auto[1] |
1275497 |
1 |
|
|
T34 |
59 |
|
T12 |
59 |
|
T14 |
251 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |