Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8294913 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
46 |
| auto[1] |
6197249 |
1 |
|
|
T33 |
15 |
|
T34 |
169 |
|
T1 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11929176 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
51 |
| auto[1] |
2562986 |
1 |
|
|
T33 |
10 |
|
T34 |
81 |
|
T1 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8334966 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
50 |
| auto[1] |
6157196 |
1 |
|
|
T33 |
11 |
|
T34 |
157 |
|
T1 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1787850 |
1 |
|
|
T34 |
34 |
|
T1 |
12 |
|
T12 |
279 |
| auto[1] |
auto[0] |
auto[1] |
1276950 |
1 |
|
|
T33 |
8 |
|
T34 |
41 |
|
T1 |
19 |
| auto[1] |
auto[1] |
auto[0] |
1806360 |
1 |
|
|
T33 |
1 |
|
T34 |
42 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1286036 |
1 |
|
|
T33 |
2 |
|
T34 |
40 |
|
T1 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |