Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8338764 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
48 |
| auto[1] |
6153398 |
1 |
|
|
T33 |
13 |
|
T34 |
159 |
|
T1 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13698734 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
793428 |
1 |
|
|
T34 |
9 |
|
T1 |
1 |
|
T12 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8338051 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
52 |
| auto[1] |
6154111 |
1 |
|
|
T33 |
9 |
|
T34 |
140 |
|
T1 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2683340 |
1 |
|
|
T33 |
4 |
|
T34 |
70 |
|
T1 |
14 |
| auto[1] |
auto[0] |
auto[1] |
397738 |
1 |
|
|
T34 |
4 |
|
T12 |
10 |
|
T14 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2677343 |
1 |
|
|
T33 |
5 |
|
T34 |
61 |
|
T1 |
12 |
| auto[1] |
auto[1] |
auto[1] |
395690 |
1 |
|
|
T34 |
5 |
|
T1 |
1 |
|
T12 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |