Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8334501 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
50 |
| auto[1] |
6157661 |
1 |
|
|
T33 |
11 |
|
T34 |
201 |
|
T1 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13700745 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
791417 |
1 |
|
|
T34 |
14 |
|
T1 |
1 |
|
T12 |
46 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8351917 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
57 |
| auto[1] |
6140245 |
1 |
|
|
T33 |
4 |
|
T34 |
184 |
|
T1 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2683921 |
1 |
|
|
T33 |
3 |
|
T34 |
83 |
|
T1 |
22 |
| auto[1] |
auto[0] |
auto[1] |
396451 |
1 |
|
|
T34 |
7 |
|
T1 |
1 |
|
T12 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2664907 |
1 |
|
|
T33 |
1 |
|
T34 |
87 |
|
T12 |
508 |
| auto[1] |
auto[1] |
auto[1] |
394966 |
1 |
|
|
T34 |
7 |
|
T12 |
26 |
|
T14 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |