Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8325772 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
35 |
| auto[1] |
6166390 |
1 |
|
|
T33 |
26 |
|
T34 |
170 |
|
T1 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13695603 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
61 |
| auto[1] |
796559 |
1 |
|
|
T34 |
8 |
|
T12 |
40 |
|
T14 |
47 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8318345 |
1 |
|
|
T31 |
278 |
|
T32 |
54 |
|
T33 |
48 |
| auto[1] |
6173817 |
1 |
|
|
T33 |
13 |
|
T34 |
125 |
|
T1 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2698161 |
1 |
|
|
T33 |
1 |
|
T34 |
73 |
|
T1 |
17 |
| auto[1] |
auto[0] |
auto[1] |
400773 |
1 |
|
|
T34 |
4 |
|
T12 |
18 |
|
T14 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2679097 |
1 |
|
|
T33 |
12 |
|
T34 |
44 |
|
T12 |
471 |
| auto[1] |
auto[1] |
auto[1] |
395786 |
1 |
|
|
T34 |
4 |
|
T12 |
22 |
|
T14 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |