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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 944
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T96 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.758623153 Jul 04 04:51:27 PM PDT 24 Jul 04 04:51:28 PM PDT 24 42731794 ps
T110 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2347057644 Jul 04 04:50:56 PM PDT 24 Jul 04 04:50:56 PM PDT 24 56378183 ps
T764 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3552495960 Jul 04 04:51:13 PM PDT 24 Jul 04 04:51:15 PM PDT 24 28562984 ps
T97 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2040766194 Jul 04 04:50:57 PM PDT 24 Jul 04 04:50:58 PM PDT 24 30466830 ps
T765 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3398544499 Jul 04 04:51:25 PM PDT 24 Jul 04 04:51:27 PM PDT 24 141385888 ps
T766 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3806393030 Jul 04 04:50:57 PM PDT 24 Jul 04 04:50:57 PM PDT 24 104915635 ps
T767 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3417446601 Jul 04 04:51:29 PM PDT 24 Jul 04 04:51:30 PM PDT 24 11379682 ps
T768 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1046570413 Jul 04 04:50:59 PM PDT 24 Jul 04 04:51:00 PM PDT 24 14008401 ps
T48 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.745019444 Jul 04 04:50:42 PM PDT 24 Jul 04 04:50:43 PM PDT 24 242404495 ps
T769 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2105479528 Jul 04 04:51:30 PM PDT 24 Jul 04 04:51:31 PM PDT 24 43190715 ps
T98 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1568579290 Jul 04 04:50:53 PM PDT 24 Jul 04 04:50:54 PM PDT 24 18385599 ps
T99 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2393793747 Jul 04 04:51:07 PM PDT 24 Jul 04 04:51:08 PM PDT 24 50131212 ps
T770 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.926806514 Jul 04 04:51:05 PM PDT 24 Jul 04 04:51:06 PM PDT 24 25954973 ps
T111 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3799741754 Jul 04 04:50:47 PM PDT 24 Jul 04 04:50:48 PM PDT 24 78775031 ps
T771 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3824981495 Jul 04 04:51:21 PM PDT 24 Jul 04 04:51:22 PM PDT 24 53282421 ps
T772 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.312359550 Jul 04 04:51:28 PM PDT 24 Jul 04 04:51:29 PM PDT 24 150702715 ps
T773 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.115294467 Jul 04 04:50:56 PM PDT 24 Jul 04 04:50:57 PM PDT 24 61037315 ps
T774 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.925624712 Jul 04 04:51:20 PM PDT 24 Jul 04 04:51:22 PM PDT 24 83482251 ps
T55 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1214770626 Jul 04 04:51:12 PM PDT 24 Jul 04 04:51:13 PM PDT 24 444196323 ps
T775 /workspace/coverage/cover_reg_top/36.gpio_intr_test.27685576 Jul 04 04:51:29 PM PDT 24 Jul 04 04:51:30 PM PDT 24 18528718 ps
T776 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2072967387 Jul 04 04:51:23 PM PDT 24 Jul 04 04:51:24 PM PDT 24 38909064 ps
T777 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3125465224 Jul 04 04:50:57 PM PDT 24 Jul 04 04:50:59 PM PDT 24 335951406 ps
T115 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2659647960 Jul 04 04:51:06 PM PDT 24 Jul 04 04:51:07 PM PDT 24 191899330 ps
T778 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3985958613 Jul 04 04:51:07 PM PDT 24 Jul 04 04:51:07 PM PDT 24 11538373 ps
T779 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2713559219 Jul 04 04:50:53 PM PDT 24 Jul 04 04:50:54 PM PDT 24 41327642 ps
T780 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3675324756 Jul 04 04:51:28 PM PDT 24 Jul 04 04:51:29 PM PDT 24 42684850 ps
T781 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2435412820 Jul 04 04:51:28 PM PDT 24 Jul 04 04:51:29 PM PDT 24 45196121 ps
T782 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2715823673 Jul 04 04:51:29 PM PDT 24 Jul 04 04:51:30 PM PDT 24 39436042 ps
T783 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1041090695 Jul 04 04:50:59 PM PDT 24 Jul 04 04:51:00 PM PDT 24 285321990 ps
T784 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.850338612 Jul 04 04:51:09 PM PDT 24 Jul 04 04:51:10 PM PDT 24 30593101 ps
T785 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3427101557 Jul 04 04:51:23 PM PDT 24 Jul 04 04:51:24 PM PDT 24 15118055 ps
T786 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1361933443 Jul 04 04:51:12 PM PDT 24 Jul 04 04:51:14 PM PDT 24 70706809 ps
T787 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2791425638 Jul 04 04:51:26 PM PDT 24 Jul 04 04:51:27 PM PDT 24 19676920 ps
T788 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2944556341 Jul 04 04:50:49 PM PDT 24 Jul 04 04:50:52 PM PDT 24 395198146 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_intr_test.416411463 Jul 04 04:50:48 PM PDT 24 Jul 04 04:50:49 PM PDT 24 24471941 ps
T790 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2018891330 Jul 04 04:50:44 PM PDT 24 Jul 04 04:50:45 PM PDT 24 25894367 ps
T791 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3775691761 Jul 04 04:50:47 PM PDT 24 Jul 04 04:50:47 PM PDT 24 42452088 ps
T792 /workspace/coverage/cover_reg_top/22.gpio_intr_test.4260970223 Jul 04 04:51:27 PM PDT 24 Jul 04 04:51:28 PM PDT 24 12795445 ps
T793 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2963521048 Jul 04 04:51:31 PM PDT 24 Jul 04 04:51:32 PM PDT 24 67114261 ps
T794 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1367988219 Jul 04 04:51:30 PM PDT 24 Jul 04 04:51:31 PM PDT 24 16607486 ps
T795 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1179636140 Jul 04 04:51:05 PM PDT 24 Jul 04 04:51:08 PM PDT 24 100421275 ps
T796 /workspace/coverage/cover_reg_top/45.gpio_intr_test.4225658731 Jul 04 04:51:30 PM PDT 24 Jul 04 04:51:31 PM PDT 24 43663529 ps
T797 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2972844896 Jul 04 04:51:06 PM PDT 24 Jul 04 04:51:07 PM PDT 24 40201374 ps
T798 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1076661626 Jul 04 04:51:22 PM PDT 24 Jul 04 04:51:22 PM PDT 24 20349992 ps
T799 /workspace/coverage/cover_reg_top/4.gpio_intr_test.598458957 Jul 04 04:50:56 PM PDT 24 Jul 04 04:50:57 PM PDT 24 12421076 ps
T800 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2203061169 Jul 04 04:51:21 PM PDT 24 Jul 04 04:51:22 PM PDT 24 92834138 ps
T801 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1236811792 Jul 04 04:50:56 PM PDT 24 Jul 04 04:50:57 PM PDT 24 29114930 ps
T802 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3530561273 Jul 04 04:50:56 PM PDT 24 Jul 04 04:50:56 PM PDT 24 12086615 ps
T803 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4041874567 Jul 04 04:51:13 PM PDT 24 Jul 04 04:51:16 PM PDT 24 45668376 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2033233761 Jul 04 04:50:47 PM PDT 24 Jul 04 04:50:49 PM PDT 24 164490588 ps
T100 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.601181167 Jul 04 04:51:22 PM PDT 24 Jul 04 04:51:23 PM PDT 24 19572096 ps
T805 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4178753771 Jul 04 04:50:48 PM PDT 24 Jul 04 04:50:49 PM PDT 24 10711044 ps
T806 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3635697922 Jul 04 04:51:18 PM PDT 24 Jul 04 04:51:19 PM PDT 24 35159310 ps
T807 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1124912267 Jul 04 04:51:02 PM PDT 24 Jul 04 04:51:04 PM PDT 24 57142025 ps
T808 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2634786183 Jul 04 04:51:30 PM PDT 24 Jul 04 04:51:31 PM PDT 24 28580334 ps
T809 /workspace/coverage/cover_reg_top/31.gpio_intr_test.54186487 Jul 04 04:51:29 PM PDT 24 Jul 04 04:51:30 PM PDT 24 39076101 ps
T810 /workspace/coverage/cover_reg_top/18.gpio_intr_test.577073994 Jul 04 04:51:20 PM PDT 24 Jul 04 04:51:21 PM PDT 24 12101664 ps
T811 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3460224371 Jul 04 04:51:09 PM PDT 24 Jul 04 04:51:12 PM PDT 24 153064856 ps
T812 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2399484642 Jul 04 04:51:13 PM PDT 24 Jul 04 04:51:14 PM PDT 24 30923848 ps
T813 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.246288540 Jul 04 04:51:28 PM PDT 24 Jul 04 04:51:29 PM PDT 24 44618609 ps
T814 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1789923643 Jul 04 04:51:27 PM PDT 24 Jul 04 04:51:28 PM PDT 24 56269558 ps
T815 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2540149498 Jul 04 04:50:51 PM PDT 24 Jul 04 04:50:52 PM PDT 24 67908608 ps
T816 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1683651092 Jul 04 04:51:29 PM PDT 24 Jul 04 04:51:30 PM PDT 24 25702218 ps
T817 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.50535719 Jul 04 04:51:07 PM PDT 24 Jul 04 04:51:08 PM PDT 24 117648037 ps
T818 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.831881042 Jul 04 04:50:46 PM PDT 24 Jul 04 04:50:47 PM PDT 24 23311705 ps
T819 /workspace/coverage/cover_reg_top/21.gpio_intr_test.272713022 Jul 04 04:51:30 PM PDT 24 Jul 04 04:51:31 PM PDT 24 12993803 ps
T101 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4094778156 Jul 04 04:51:15 PM PDT 24 Jul 04 04:51:16 PM PDT 24 15390174 ps
T102 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3867319957 Jul 04 04:50:48 PM PDT 24 Jul 04 04:50:51 PM PDT 24 87871391 ps
T50 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.373508914 Jul 04 04:51:07 PM PDT 24 Jul 04 04:51:08 PM PDT 24 1336952090 ps
T820 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3464478688 Jul 04 04:50:58 PM PDT 24 Jul 04 04:50:58 PM PDT 24 57140268 ps
T821 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3028627045 Jul 04 04:51:09 PM PDT 24 Jul 04 04:51:09 PM PDT 24 35373004 ps
T822 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1991275053 Jul 04 04:51:32 PM PDT 24 Jul 04 04:51:32 PM PDT 24 34503951 ps
T823 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.62187546 Jul 04 04:50:58 PM PDT 24 Jul 04 04:50:59 PM PDT 24 17066003 ps
T824 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.90810364 Jul 04 04:51:18 PM PDT 24 Jul 04 04:51:20 PM PDT 24 84172388 ps
T825 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.143897731 Jul 04 04:51:05 PM PDT 24 Jul 04 04:51:06 PM PDT 24 13984621 ps
T826 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3387285081 Jul 04 04:51:31 PM PDT 24 Jul 04 04:51:32 PM PDT 24 72333125 ps
T827 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1892426927 Jul 04 04:50:42 PM PDT 24 Jul 04 04:50:43 PM PDT 24 30832747 ps
T828 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4099566526 Jul 04 04:51:25 PM PDT 24 Jul 04 04:51:26 PM PDT 24 130778597 ps
T829 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4034691220 Jul 04 04:51:03 PM PDT 24 Jul 04 04:51:05 PM PDT 24 118613309 ps
T830 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.308963079 Jul 04 04:51:06 PM PDT 24 Jul 04 04:51:07 PM PDT 24 198469539 ps
T831 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4291232709 Jul 04 04:50:49 PM PDT 24 Jul 04 04:50:50 PM PDT 24 62279462 ps
T832 /workspace/coverage/cover_reg_top/44.gpio_intr_test.2113021550 Jul 04 04:51:28 PM PDT 24 Jul 04 04:51:29 PM PDT 24 41758390 ps
T833 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3012448746 Jul 04 04:50:56 PM PDT 24 Jul 04 04:50:57 PM PDT 24 176491769 ps
T834 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1714489311 Jul 04 04:51:28 PM PDT 24 Jul 04 04:51:29 PM PDT 24 16444591 ps
T835 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.4268120610 Jul 04 04:51:06 PM PDT 24 Jul 04 04:51:07 PM PDT 24 18369112 ps
T836 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1795525230 Jul 04 04:50:56 PM PDT 24 Jul 04 04:50:57 PM PDT 24 12903765 ps
T837 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.633423522 Jul 04 04:50:51 PM PDT 24 Jul 04 04:50:52 PM PDT 24 49109492 ps
T838 /workspace/coverage/cover_reg_top/12.gpio_intr_test.95950183 Jul 04 04:51:14 PM PDT 24 Jul 04 04:51:15 PM PDT 24 23234511 ps
T839 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4198230683 Jul 04 04:51:14 PM PDT 24 Jul 04 04:51:14 PM PDT 24 19293594 ps
T840 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1836016099 Jul 04 04:51:14 PM PDT 24 Jul 04 04:51:15 PM PDT 24 89281881 ps
T841 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2599634199 Jul 04 04:50:48 PM PDT 24 Jul 04 04:50:49 PM PDT 24 19250819 ps
T842 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2399056189 Jul 04 04:51:18 PM PDT 24 Jul 04 04:51:19 PM PDT 24 142459361 ps
T843 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1577356969 Jul 04 04:51:22 PM PDT 24 Jul 04 04:51:24 PM PDT 24 85323886 ps
T844 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1249179004 Jul 04 04:51:19 PM PDT 24 Jul 04 04:51:20 PM PDT 24 30376962 ps
T845 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2543212977 Jul 04 04:51:36 PM PDT 24 Jul 04 04:51:38 PM PDT 24 66627345 ps
T846 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1614262529 Jul 04 04:52:00 PM PDT 24 Jul 04 04:52:01 PM PDT 24 29457704 ps
T847 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1703055346 Jul 04 04:51:41 PM PDT 24 Jul 04 04:51:43 PM PDT 24 282316775 ps
T848 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3427229262 Jul 04 04:51:53 PM PDT 24 Jul 04 04:51:55 PM PDT 24 354247230 ps
T849 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1127294763 Jul 04 04:51:44 PM PDT 24 Jul 04 04:51:45 PM PDT 24 27637363 ps
T850 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2567296250 Jul 04 04:51:36 PM PDT 24 Jul 04 04:51:37 PM PDT 24 613224268 ps
T851 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3339674390 Jul 04 04:51:37 PM PDT 24 Jul 04 04:51:39 PM PDT 24 81877718 ps
T852 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.503989201 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:36 PM PDT 24 196518117 ps
T853 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.8337324 Jul 04 04:51:29 PM PDT 24 Jul 04 04:51:30 PM PDT 24 123576924 ps
T854 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1930988987 Jul 04 04:51:42 PM PDT 24 Jul 04 04:51:43 PM PDT 24 29284378 ps
T855 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1522689768 Jul 04 04:51:53 PM PDT 24 Jul 04 04:51:55 PM PDT 24 298060075 ps
T856 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.315905182 Jul 04 04:51:52 PM PDT 24 Jul 04 04:51:54 PM PDT 24 679675393 ps
T857 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.604892910 Jul 04 04:51:42 PM PDT 24 Jul 04 04:51:43 PM PDT 24 51751659 ps
T858 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.925748685 Jul 04 04:51:53 PM PDT 24 Jul 04 04:51:55 PM PDT 24 49384445 ps
T859 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.539169511 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:37 PM PDT 24 169844539 ps
T860 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.214983818 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:36 PM PDT 24 82675166 ps
T861 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3923456103 Jul 04 04:51:46 PM PDT 24 Jul 04 04:51:48 PM PDT 24 400447140 ps
T862 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3237106365 Jul 04 04:51:40 PM PDT 24 Jul 04 04:51:41 PM PDT 24 110203209 ps
T863 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2074170670 Jul 04 04:51:42 PM PDT 24 Jul 04 04:51:44 PM PDT 24 51945837 ps
T864 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1608176116 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:40 PM PDT 24 149729090 ps
T865 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.958949044 Jul 04 04:51:36 PM PDT 24 Jul 04 04:51:37 PM PDT 24 78217439 ps
T866 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4157385773 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:36 PM PDT 24 66596810 ps
T867 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1969074547 Jul 04 04:51:42 PM PDT 24 Jul 04 04:51:44 PM PDT 24 184385299 ps
T868 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1481768657 Jul 04 04:52:00 PM PDT 24 Jul 04 04:52:02 PM PDT 24 38243746 ps
T869 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.140257452 Jul 04 04:51:54 PM PDT 24 Jul 04 04:51:56 PM PDT 24 232605807 ps
T870 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4122033450 Jul 04 04:51:44 PM PDT 24 Jul 04 04:51:46 PM PDT 24 186016354 ps
T871 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.125501463 Jul 04 04:51:37 PM PDT 24 Jul 04 04:51:38 PM PDT 24 300320305 ps
T872 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2290091966 Jul 04 04:51:54 PM PDT 24 Jul 04 04:51:56 PM PDT 24 291730842 ps
T873 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4132568808 Jul 04 04:51:37 PM PDT 24 Jul 04 04:51:39 PM PDT 24 361574150 ps
T874 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1460622327 Jul 04 04:51:33 PM PDT 24 Jul 04 04:51:35 PM PDT 24 92154232 ps
T875 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1013990626 Jul 04 04:51:51 PM PDT 24 Jul 04 04:51:53 PM PDT 24 199318555 ps
T876 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2829262221 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:40 PM PDT 24 147373405 ps
T877 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.852298830 Jul 04 04:51:34 PM PDT 24 Jul 04 04:51:35 PM PDT 24 55639180 ps
T878 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.204035329 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:40 PM PDT 24 222719226 ps
T879 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2149138813 Jul 04 04:51:53 PM PDT 24 Jul 04 04:51:55 PM PDT 24 145751990 ps
T880 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2597730436 Jul 04 04:52:00 PM PDT 24 Jul 04 04:52:01 PM PDT 24 92707353 ps
T881 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1072831912 Jul 04 04:51:43 PM PDT 24 Jul 04 04:51:44 PM PDT 24 43638106 ps
T882 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.688016103 Jul 04 04:51:43 PM PDT 24 Jul 04 04:51:44 PM PDT 24 332765176 ps
T883 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2467718664 Jul 04 04:51:55 PM PDT 24 Jul 04 04:51:56 PM PDT 24 78366844 ps
T884 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.431995577 Jul 04 04:51:53 PM PDT 24 Jul 04 04:51:54 PM PDT 24 161114619 ps
T885 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1616248978 Jul 04 04:51:37 PM PDT 24 Jul 04 04:51:39 PM PDT 24 76202505 ps
T886 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.402641378 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:40 PM PDT 24 125136649 ps
T887 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.123071224 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:39 PM PDT 24 261173957 ps
T888 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4285179741 Jul 04 04:51:43 PM PDT 24 Jul 04 04:51:45 PM PDT 24 80231334 ps
T889 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1599404382 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:37 PM PDT 24 121685216 ps
T890 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1492621298 Jul 04 04:51:51 PM PDT 24 Jul 04 04:51:52 PM PDT 24 21810306 ps
T891 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2012729282 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:40 PM PDT 24 194973088 ps
T892 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3185816512 Jul 04 04:51:40 PM PDT 24 Jul 04 04:51:42 PM PDT 24 360308196 ps
T893 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2829003830 Jul 04 04:51:36 PM PDT 24 Jul 04 04:51:37 PM PDT 24 201151156 ps
T894 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4251451335 Jul 04 04:51:43 PM PDT 24 Jul 04 04:51:45 PM PDT 24 234596415 ps
T895 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2147986227 Jul 04 04:51:29 PM PDT 24 Jul 04 04:51:30 PM PDT 24 99425171 ps
T896 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4259810122 Jul 04 04:51:52 PM PDT 24 Jul 04 04:51:54 PM PDT 24 139854716 ps
T897 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.624674690 Jul 04 04:51:42 PM PDT 24 Jul 04 04:51:43 PM PDT 24 74258458 ps
T898 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3064768742 Jul 04 04:51:45 PM PDT 24 Jul 04 04:51:46 PM PDT 24 42080129 ps
T899 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2945160338 Jul 04 04:51:37 PM PDT 24 Jul 04 04:51:39 PM PDT 24 51538603 ps
T900 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4006211633 Jul 04 04:51:44 PM PDT 24 Jul 04 04:51:46 PM PDT 24 44450483 ps
T901 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750861018 Jul 04 04:51:50 PM PDT 24 Jul 04 04:51:52 PM PDT 24 52289627 ps
T902 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2521211239 Jul 04 04:51:34 PM PDT 24 Jul 04 04:51:35 PM PDT 24 90335988 ps
T903 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.9450694 Jul 04 04:51:43 PM PDT 24 Jul 04 04:51:44 PM PDT 24 202791322 ps
T904 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4042126282 Jul 04 04:51:43 PM PDT 24 Jul 04 04:51:44 PM PDT 24 54758302 ps
T905 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.785262112 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:37 PM PDT 24 219692816 ps
T906 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3419318958 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:39 PM PDT 24 108082159 ps
T907 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.334518418 Jul 04 04:51:41 PM PDT 24 Jul 04 04:51:42 PM PDT 24 105448376 ps
T908 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3367922143 Jul 04 04:51:43 PM PDT 24 Jul 04 04:51:44 PM PDT 24 54662182 ps
T909 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1922421620 Jul 04 04:51:52 PM PDT 24 Jul 04 04:51:53 PM PDT 24 127102930 ps
T910 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.309060436 Jul 04 04:51:51 PM PDT 24 Jul 04 04:51:53 PM PDT 24 267283097 ps
T911 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4256491762 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:40 PM PDT 24 65808397 ps
T912 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2282860283 Jul 04 04:51:39 PM PDT 24 Jul 04 04:51:40 PM PDT 24 37546627 ps
T913 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.971029590 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:40 PM PDT 24 31080261 ps
T914 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.470988284 Jul 04 04:51:44 PM PDT 24 Jul 04 04:51:46 PM PDT 24 86121137 ps
T915 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3454913302 Jul 04 04:51:37 PM PDT 24 Jul 04 04:51:39 PM PDT 24 285410545 ps
T916 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2710323531 Jul 04 04:51:52 PM PDT 24 Jul 04 04:51:55 PM PDT 24 320783726 ps
T917 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2285611872 Jul 04 04:51:37 PM PDT 24 Jul 04 04:51:38 PM PDT 24 48988090 ps
T918 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4202273147 Jul 04 04:51:37 PM PDT 24 Jul 04 04:51:38 PM PDT 24 23207539 ps
T919 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2770450765 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:40 PM PDT 24 141644315 ps
T920 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2914151072 Jul 04 04:51:30 PM PDT 24 Jul 04 04:51:31 PM PDT 24 65268660 ps
T921 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3491504268 Jul 04 04:51:30 PM PDT 24 Jul 04 04:51:31 PM PDT 24 68993309 ps
T922 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3503996981 Jul 04 04:51:55 PM PDT 24 Jul 04 04:51:56 PM PDT 24 53044270 ps
T923 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1719995500 Jul 04 04:51:54 PM PDT 24 Jul 04 04:51:55 PM PDT 24 134626790 ps
T924 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2764976317 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:37 PM PDT 24 150452812 ps
T925 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2524580574 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:37 PM PDT 24 61911148 ps
T926 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2688962265 Jul 04 04:51:34 PM PDT 24 Jul 04 04:51:36 PM PDT 24 170182558 ps
T927 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.827643321 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:36 PM PDT 24 103767253 ps
T928 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1687613936 Jul 04 04:51:54 PM PDT 24 Jul 04 04:51:55 PM PDT 24 62881796 ps
T929 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3590881856 Jul 04 04:51:40 PM PDT 24 Jul 04 04:51:41 PM PDT 24 135429962 ps
T930 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2614715390 Jul 04 04:51:44 PM PDT 24 Jul 04 04:51:45 PM PDT 24 274074187 ps
T931 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2733170107 Jul 04 04:51:35 PM PDT 24 Jul 04 04:51:36 PM PDT 24 71485582 ps
T932 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387245848 Jul 04 04:51:54 PM PDT 24 Jul 04 04:51:56 PM PDT 24 293109503 ps
T933 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.562501713 Jul 04 04:51:55 PM PDT 24 Jul 04 04:51:57 PM PDT 24 71004984 ps
T934 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2820717242 Jul 04 04:51:51 PM PDT 24 Jul 04 04:51:53 PM PDT 24 619290994 ps
T935 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.190817097 Jul 04 04:51:36 PM PDT 24 Jul 04 04:51:37 PM PDT 24 217927399 ps
T936 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.256975298 Jul 04 04:51:51 PM PDT 24 Jul 04 04:51:53 PM PDT 24 37797712 ps
T937 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1085953793 Jul 04 04:51:54 PM PDT 24 Jul 04 04:51:56 PM PDT 24 194907407 ps
T938 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3215300031 Jul 04 04:51:36 PM PDT 24 Jul 04 04:51:37 PM PDT 24 48731527 ps
T939 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1334379549 Jul 04 04:51:43 PM PDT 24 Jul 04 04:51:44 PM PDT 24 141216328 ps
T940 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.403553416 Jul 04 04:51:53 PM PDT 24 Jul 04 04:51:55 PM PDT 24 53215794 ps
T941 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.786798831 Jul 04 04:51:39 PM PDT 24 Jul 04 04:51:40 PM PDT 24 233418888 ps
T942 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.979861569 Jul 04 04:51:55 PM PDT 24 Jul 04 04:51:56 PM PDT 24 129488031 ps
T943 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3134084905 Jul 04 04:51:38 PM PDT 24 Jul 04 04:51:39 PM PDT 24 35665247 ps
T944 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2180422857 Jul 04 04:51:53 PM PDT 24 Jul 04 04:51:55 PM PDT 24 40887611 ps

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3839716514
Short name T14
Test name
Test status
Simulation time 402505899 ps
CPU time 4.78 seconds
Started Jul 04 05:03:06 PM PDT 24
Finished Jul 04 05:03:11 PM PDT 24
Peak memory 198572 kb
Host smart-0ce8f8d0-0f0d-4a6b-b036-452d322a824f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839716514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3839716514
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3166406885
Short name T117
Test name
Test status
Simulation time 832091124 ps
CPU time 3.37 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:03:06 PM PDT 24
Peak memory 198592 kb
Host smart-ea6e1be4-ec83-45a6-ac5f-b7651716103e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166406885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3166406885
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2820185811
Short name T71
Test name
Test status
Simulation time 113262818190 ps
CPU time 656.19 seconds
Started Jul 04 05:01:54 PM PDT 24
Finished Jul 04 05:12:51 PM PDT 24
Peak memory 198772 kb
Host smart-7304ec6d-2145-4eca-80de-a89cce7e73fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2820185811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2820185811
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3399725511
Short name T41
Test name
Test status
Simulation time 149313802 ps
CPU time 0.76 seconds
Started Jul 04 05:01:18 PM PDT 24
Finished Jul 04 05:01:19 PM PDT 24
Peak memory 214152 kb
Host smart-c054e98b-b352-4a79-a735-bcb27f7b6156
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399725511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3399725511
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.622740043
Short name T88
Test name
Test status
Simulation time 43686286 ps
CPU time 0.61 seconds
Started Jul 04 04:51:21 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 195340 kb
Host smart-a5355135-602e-49cc-bd6f-3646d99069c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622740043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.622740043
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4007476880
Short name T6
Test name
Test status
Simulation time 4667088943 ps
CPU time 58.15 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:02:46 PM PDT 24
Peak memory 198696 kb
Host smart-4bd70a64-3fad-449b-bc74-6d992c6eb719
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007476880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4007476880
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.4271142654
Short name T44
Test name
Test status
Simulation time 13894231 ps
CPU time 0.59 seconds
Started Jul 04 05:02:41 PM PDT 24
Finished Jul 04 05:02:42 PM PDT 24
Peak memory 195556 kb
Host smart-ec2ae4c5-af1e-4b96-bc02-51c79a9964b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271142654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4271142654
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3512802475
Short name T39
Test name
Test status
Simulation time 79521418 ps
CPU time 1.17 seconds
Started Jul 04 04:50:51 PM PDT 24
Finished Jul 04 04:50:52 PM PDT 24
Peak memory 198680 kb
Host smart-73cbcc2b-ba23-4a6c-8915-12a02f69640e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512802475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3512802475
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/16.gpio_stress_all.434140615
Short name T126
Test name
Test status
Simulation time 14183980207 ps
CPU time 199 seconds
Started Jul 04 05:01:55 PM PDT 24
Finished Jul 04 05:05:14 PM PDT 24
Peak memory 198636 kb
Host smart-3c44e726-2917-4056-8ca7-8374dcaffcc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434140615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.434140615
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3799741754
Short name T111
Test name
Test status
Simulation time 78775031 ps
CPU time 0.69 seconds
Started Jul 04 04:50:47 PM PDT 24
Finished Jul 04 04:50:48 PM PDT 24
Peak memory 196436 kb
Host smart-2e7deaf9-d9aa-4714-81d2-a25624f5191c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799741754 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3799741754
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3495774250
Short name T54
Test name
Test status
Simulation time 819850501 ps
CPU time 1.51 seconds
Started Jul 04 04:51:21 PM PDT 24
Finished Jul 04 04:51:23 PM PDT 24
Peak memory 198600 kb
Host smart-769207eb-0eca-4049-8efc-b731a2502f24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495774250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3495774250
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2659647960
Short name T115
Test name
Test status
Simulation time 191899330 ps
CPU time 0.97 seconds
Started Jul 04 04:51:06 PM PDT 24
Finished Jul 04 04:51:07 PM PDT 24
Peak memory 197820 kb
Host smart-6161e370-b3d0-4f28-9ab5-5bb2b4226ed8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659647960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2659647960
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2018891330
Short name T790
Test name
Test status
Simulation time 25894367 ps
CPU time 0.75 seconds
Started Jul 04 04:50:44 PM PDT 24
Finished Jul 04 04:50:45 PM PDT 24
Peak memory 196024 kb
Host smart-57d6b80f-7bb0-436d-b1ca-599d35210a15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018891330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2018891330
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1922640798
Short name T762
Test name
Test status
Simulation time 131525162 ps
CPU time 1.34 seconds
Started Jul 04 04:50:41 PM PDT 24
Finished Jul 04 04:50:43 PM PDT 24
Peak memory 197368 kb
Host smart-77f7caeb-086a-41eb-8cd0-90babfdb21bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922640798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1922640798
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1159042359
Short name T87
Test name
Test status
Simulation time 21390476 ps
CPU time 0.69 seconds
Started Jul 04 04:50:43 PM PDT 24
Finished Jul 04 04:50:43 PM PDT 24
Peak memory 195568 kb
Host smart-bbfe8352-a677-40f0-acd4-6bd0433481b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159042359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1159042359
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2792404333
Short name T750
Test name
Test status
Simulation time 36435848 ps
CPU time 1.11 seconds
Started Jul 04 04:50:41 PM PDT 24
Finished Jul 04 04:50:42 PM PDT 24
Peak memory 198672 kb
Host smart-bd2cca51-9b16-4186-9bf6-596951121de0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792404333 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2792404333
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.831881042
Short name T818
Test name
Test status
Simulation time 23311705 ps
CPU time 0.57 seconds
Started Jul 04 04:50:46 PM PDT 24
Finished Jul 04 04:50:47 PM PDT 24
Peak memory 195164 kb
Host smart-9aa36899-f030-44cd-b8e5-76090e967e91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831881042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.831881042
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3775691761
Short name T791
Test name
Test status
Simulation time 42452088 ps
CPU time 0.57 seconds
Started Jul 04 04:50:47 PM PDT 24
Finished Jul 04 04:50:47 PM PDT 24
Peak memory 194212 kb
Host smart-192e22a5-4f5b-4f97-b6bd-21e265233a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775691761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3775691761
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1892426927
Short name T827
Test name
Test status
Simulation time 30832747 ps
CPU time 0.83 seconds
Started Jul 04 04:50:42 PM PDT 24
Finished Jul 04 04:50:43 PM PDT 24
Peak memory 196916 kb
Host smart-b2eb6362-c5ca-45e5-b2dc-3adf8ad33ef8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892426927 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1892426927
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2033233761
Short name T804
Test name
Test status
Simulation time 164490588 ps
CPU time 2.05 seconds
Started Jul 04 04:50:47 PM PDT 24
Finished Jul 04 04:50:49 PM PDT 24
Peak memory 198592 kb
Host smart-840ffc91-b917-49fc-a1df-bbc9f5031d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033233761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2033233761
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.745019444
Short name T48
Test name
Test status
Simulation time 242404495 ps
CPU time 1.12 seconds
Started Jul 04 04:50:42 PM PDT 24
Finished Jul 04 04:50:43 PM PDT 24
Peak memory 198580 kb
Host smart-401b21b2-432d-4520-8dad-be5c760f8567
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745019444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.745019444
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.633423522
Short name T837
Test name
Test status
Simulation time 49109492 ps
CPU time 0.75 seconds
Started Jul 04 04:50:51 PM PDT 24
Finished Jul 04 04:50:52 PM PDT 24
Peak memory 197084 kb
Host smart-9749d758-247e-449d-9a26-ba4b4384459f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633423522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.633423522
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2944556341
Short name T788
Test name
Test status
Simulation time 395198146 ps
CPU time 3.57 seconds
Started Jul 04 04:50:49 PM PDT 24
Finished Jul 04 04:50:52 PM PDT 24
Peak memory 197336 kb
Host smart-ef7fe3e6-cf31-4fa7-a791-9038a97a4607
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944556341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2944556341
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2713559219
Short name T779
Test name
Test status
Simulation time 41327642 ps
CPU time 0.57 seconds
Started Jul 04 04:50:53 PM PDT 24
Finished Jul 04 04:50:54 PM PDT 24
Peak memory 195596 kb
Host smart-89543d8a-7514-4564-a278-10f92c0e95f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713559219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2713559219
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4291232709
Short name T831
Test name
Test status
Simulation time 62279462 ps
CPU time 0.87 seconds
Started Jul 04 04:50:49 PM PDT 24
Finished Jul 04 04:50:50 PM PDT 24
Peak memory 198492 kb
Host smart-abab97cb-76f1-426a-a477-cdc22fe2cec1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291232709 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4291232709
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2257818022
Short name T86
Test name
Test status
Simulation time 31575684 ps
CPU time 0.58 seconds
Started Jul 04 04:50:50 PM PDT 24
Finished Jul 04 04:50:51 PM PDT 24
Peak memory 193900 kb
Host smart-e82330b1-3b2d-4a48-9df0-18c8bf180200
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257818022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2257818022
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2945793402
Short name T748
Test name
Test status
Simulation time 112300055 ps
CPU time 0.61 seconds
Started Jul 04 04:50:49 PM PDT 24
Finished Jul 04 04:50:50 PM PDT 24
Peak memory 194924 kb
Host smart-d50a19da-6845-4fdf-be52-f54a2ce224ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945793402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2945793402
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2606176490
Short name T734
Test name
Test status
Simulation time 1343838551 ps
CPU time 3.47 seconds
Started Jul 04 04:50:50 PM PDT 24
Finished Jul 04 04:50:54 PM PDT 24
Peak memory 198600 kb
Host smart-beac7729-252a-4d38-9e43-c8973e7454d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606176490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2606176490
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.850338612
Short name T784
Test name
Test status
Simulation time 30593101 ps
CPU time 0.94 seconds
Started Jul 04 04:51:09 PM PDT 24
Finished Jul 04 04:51:10 PM PDT 24
Peak memory 198424 kb
Host smart-18d6d310-4b8a-4ad5-a16a-b2de4c345247
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850338612 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.850338612
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2393793747
Short name T99
Test name
Test status
Simulation time 50131212 ps
CPU time 0.58 seconds
Started Jul 04 04:51:07 PM PDT 24
Finished Jul 04 04:51:08 PM PDT 24
Peak memory 194524 kb
Host smart-c4c68684-ae1a-4bb6-b693-762dd9bddf7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393793747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2393793747
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.848061102
Short name T759
Test name
Test status
Simulation time 39709329 ps
CPU time 0.57 seconds
Started Jul 04 04:51:06 PM PDT 24
Finished Jul 04 04:51:07 PM PDT 24
Peak memory 194196 kb
Host smart-62d0da63-7054-435b-93c1-fcb8ffc62ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848061102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.848061102
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.50535719
Short name T817
Test name
Test status
Simulation time 117648037 ps
CPU time 0.8 seconds
Started Jul 04 04:51:07 PM PDT 24
Finished Jul 04 04:51:08 PM PDT 24
Peak memory 196460 kb
Host smart-f51025fa-7d56-4b67-9517-201d8b9cb043
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50535719 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.gpio_same_csr_outstanding.50535719
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1398879049
Short name T761
Test name
Test status
Simulation time 548769241 ps
CPU time 2.86 seconds
Started Jul 04 04:51:07 PM PDT 24
Finished Jul 04 04:51:10 PM PDT 24
Peak memory 198572 kb
Host smart-bd1e62e9-f995-471b-9d3b-c8ae088449cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398879049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1398879049
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.308963079
Short name T830
Test name
Test status
Simulation time 198469539 ps
CPU time 1.03 seconds
Started Jul 04 04:51:06 PM PDT 24
Finished Jul 04 04:51:07 PM PDT 24
Peak memory 198496 kb
Host smart-64ba461d-ebb5-49d2-89df-f6a4e6de358e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308963079 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.308963079
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1583239644
Short name T90
Test name
Test status
Simulation time 46428845 ps
CPU time 0.6 seconds
Started Jul 04 04:51:07 PM PDT 24
Finished Jul 04 04:51:08 PM PDT 24
Peak memory 193900 kb
Host smart-2d94bb02-85e9-4bcd-bf8b-008da66ed519
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583239644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1583239644
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1836016099
Short name T840
Test name
Test status
Simulation time 89281881 ps
CPU time 0.58 seconds
Started Jul 04 04:51:14 PM PDT 24
Finished Jul 04 04:51:15 PM PDT 24
Peak memory 194796 kb
Host smart-5a060c93-32f8-4915-9a23-915819ea27a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836016099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1836016099
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3087674603
Short name T107
Test name
Test status
Simulation time 41053817 ps
CPU time 0.89 seconds
Started Jul 04 04:51:07 PM PDT 24
Finished Jul 04 04:51:08 PM PDT 24
Peak memory 196988 kb
Host smart-a34fc30f-d431-4479-a856-a0d5f9fd92bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087674603 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3087674603
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2273626636
Short name T726
Test name
Test status
Simulation time 19559686 ps
CPU time 1 seconds
Started Jul 04 04:51:13 PM PDT 24
Finished Jul 04 04:51:14 PM PDT 24
Peak memory 198412 kb
Host smart-081b11c8-6ce0-4f9c-a614-a23d5a96494e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273626636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2273626636
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3345277255
Short name T38
Test name
Test status
Simulation time 944532135 ps
CPU time 1.56 seconds
Started Jul 04 04:51:05 PM PDT 24
Finished Jul 04 04:51:06 PM PDT 24
Peak memory 198632 kb
Host smart-8bdc8ed5-ee91-4680-a9fb-d6de38e07dc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345277255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3345277255
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3552495960
Short name T764
Test name
Test status
Simulation time 28562984 ps
CPU time 1.36 seconds
Started Jul 04 04:51:13 PM PDT 24
Finished Jul 04 04:51:15 PM PDT 24
Peak memory 198628 kb
Host smart-6a610654-0413-485a-880c-6ef9c24fba2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552495960 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3552495960
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.820574709
Short name T113
Test name
Test status
Simulation time 144854531 ps
CPU time 0.63 seconds
Started Jul 04 04:51:18 PM PDT 24
Finished Jul 04 04:51:19 PM PDT 24
Peak memory 195468 kb
Host smart-57f7dfba-033f-4471-9898-d9823f033673
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820574709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.820574709
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.95950183
Short name T838
Test name
Test status
Simulation time 23234511 ps
CPU time 0.63 seconds
Started Jul 04 04:51:14 PM PDT 24
Finished Jul 04 04:51:15 PM PDT 24
Peak memory 194880 kb
Host smart-caf6d6f2-bc0f-4cb8-9b8e-47b301105c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95950183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.95950183
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2399056189
Short name T842
Test name
Test status
Simulation time 142459361 ps
CPU time 0.69 seconds
Started Jul 04 04:51:18 PM PDT 24
Finished Jul 04 04:51:19 PM PDT 24
Peak memory 195580 kb
Host smart-f506885b-0e1c-4692-86dc-0864342f0d68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399056189 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2399056189
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.90810364
Short name T824
Test name
Test status
Simulation time 84172388 ps
CPU time 1.96 seconds
Started Jul 04 04:51:18 PM PDT 24
Finished Jul 04 04:51:20 PM PDT 24
Peak memory 198620 kb
Host smart-087c9c98-e7f9-4536-af90-c7072f663ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90810364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.90810364
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1214770626
Short name T55
Test name
Test status
Simulation time 444196323 ps
CPU time 1.33 seconds
Started Jul 04 04:51:12 PM PDT 24
Finished Jul 04 04:51:13 PM PDT 24
Peak memory 198604 kb
Host smart-0e9ece14-5c77-4e7d-be6f-f1d8979f6bf2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214770626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1214770626
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1361933443
Short name T786
Test name
Test status
Simulation time 70706809 ps
CPU time 1.64 seconds
Started Jul 04 04:51:12 PM PDT 24
Finished Jul 04 04:51:14 PM PDT 24
Peak memory 198664 kb
Host smart-390b9efd-ae16-4554-8b6a-a011675a7afa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361933443 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1361933443
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4094778156
Short name T101
Test name
Test status
Simulation time 15390174 ps
CPU time 0.61 seconds
Started Jul 04 04:51:15 PM PDT 24
Finished Jul 04 04:51:16 PM PDT 24
Peak memory 195016 kb
Host smart-3985ce48-0a82-4f1b-a1d2-fc5bb955e424
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094778156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4094778156
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3635697922
Short name T806
Test name
Test status
Simulation time 35159310 ps
CPU time 0.63 seconds
Started Jul 04 04:51:18 PM PDT 24
Finished Jul 04 04:51:19 PM PDT 24
Peak memory 194336 kb
Host smart-70a4c70d-5d21-433f-a304-54b8b8c0a2a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635697922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3635697922
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2399484642
Short name T812
Test name
Test status
Simulation time 30923848 ps
CPU time 0.85 seconds
Started Jul 04 04:51:13 PM PDT 24
Finished Jul 04 04:51:14 PM PDT 24
Peak memory 196740 kb
Host smart-6a380da0-5fdb-4551-a6ed-4ec45fc4ce8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399484642 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2399484642
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4041874567
Short name T803
Test name
Test status
Simulation time 45668376 ps
CPU time 2.4 seconds
Started Jul 04 04:51:13 PM PDT 24
Finished Jul 04 04:51:16 PM PDT 24
Peak memory 198636 kb
Host smart-53c6c302-bf7b-4d36-b802-e822cf53bf8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041874567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.4041874567
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1138442821
Short name T40
Test name
Test status
Simulation time 474927173 ps
CPU time 1.17 seconds
Started Jul 04 04:51:13 PM PDT 24
Finished Jul 04 04:51:14 PM PDT 24
Peak memory 198624 kb
Host smart-3246cf2b-b0c4-47e6-ab89-02d9f6ebdad3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138442821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1138442821
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3824981495
Short name T771
Test name
Test status
Simulation time 53282421 ps
CPU time 0.66 seconds
Started Jul 04 04:51:21 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 196904 kb
Host smart-6622d63a-5e03-4a65-872e-6de26702a702
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824981495 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3824981495
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4198230683
Short name T839
Test name
Test status
Simulation time 19293594 ps
CPU time 0.62 seconds
Started Jul 04 04:51:14 PM PDT 24
Finished Jul 04 04:51:14 PM PDT 24
Peak memory 195900 kb
Host smart-9f1ac3af-d749-4b28-8098-0fbe44f79039
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198230683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4198230683
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1076661626
Short name T798
Test name
Test status
Simulation time 20349992 ps
CPU time 0.58 seconds
Started Jul 04 04:51:22 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 194108 kb
Host smart-83024c94-62d0-40a7-87fa-19b31d24f9e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076661626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1076661626
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1249179004
Short name T844
Test name
Test status
Simulation time 30376962 ps
CPU time 0.8 seconds
Started Jul 04 04:51:19 PM PDT 24
Finished Jul 04 04:51:20 PM PDT 24
Peak memory 197012 kb
Host smart-961a3376-3db9-4b80-ac93-37dec49791a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249179004 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1249179004
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4163822907
Short name T727
Test name
Test status
Simulation time 86046595 ps
CPU time 1.92 seconds
Started Jul 04 04:51:20 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 198600 kb
Host smart-be390c1f-18e8-4396-9e22-7b1f50b9cbee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163822907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4163822907
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4054832242
Short name T51
Test name
Test status
Simulation time 435896341 ps
CPU time 1.44 seconds
Started Jul 04 04:51:21 PM PDT 24
Finished Jul 04 04:51:23 PM PDT 24
Peak memory 198572 kb
Host smart-b56754c2-47ae-4e9c-ac22-1b4749dd36c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054832242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4054832242
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3398544499
Short name T765
Test name
Test status
Simulation time 141385888 ps
CPU time 0.98 seconds
Started Jul 04 04:51:25 PM PDT 24
Finished Jul 04 04:51:27 PM PDT 24
Peak memory 198540 kb
Host smart-797d2a0f-10eb-4738-a53e-808d924f1d4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398544499 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3398544499
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.758623153
Short name T96
Test name
Test status
Simulation time 42731794 ps
CPU time 0.64 seconds
Started Jul 04 04:51:27 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 195308 kb
Host smart-85694eb8-04db-4b36-a28d-5f68e9d0935a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758623153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.758623153
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.865534486
Short name T752
Test name
Test status
Simulation time 13546725 ps
CPU time 0.61 seconds
Started Jul 04 04:51:21 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 194312 kb
Host smart-9268ff80-741e-48d8-b62e-59231be45c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865534486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.865534486
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3427101557
Short name T785
Test name
Test status
Simulation time 15118055 ps
CPU time 0.68 seconds
Started Jul 04 04:51:23 PM PDT 24
Finished Jul 04 04:51:24 PM PDT 24
Peak memory 195056 kb
Host smart-b5374019-e9ce-4835-9b65-c5bbe9b9139d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427101557 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3427101557
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1584876367
Short name T724
Test name
Test status
Simulation time 54516372 ps
CPU time 1.38 seconds
Started Jul 04 04:51:20 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 198604 kb
Host smart-a70220e0-225a-4b9b-af16-18a9c67fe01f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584876367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1584876367
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2627651481
Short name T114
Test name
Test status
Simulation time 100064591 ps
CPU time 1.43 seconds
Started Jul 04 04:51:20 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 198592 kb
Host smart-6774d507-edf6-4838-b67c-e4498db7900b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627651481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2627651481
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2791425638
Short name T787
Test name
Test status
Simulation time 19676920 ps
CPU time 0.69 seconds
Started Jul 04 04:51:26 PM PDT 24
Finished Jul 04 04:51:27 PM PDT 24
Peak memory 198036 kb
Host smart-bcd4d408-fc2c-4703-a023-76952c954fba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791425638 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2791425638
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3417446601
Short name T767
Test name
Test status
Simulation time 11379682 ps
CPU time 0.63 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 194220 kb
Host smart-ff892212-ebca-4a4c-8d91-aa9fefbde04d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417446601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3417446601
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1683651092
Short name T816
Test name
Test status
Simulation time 25702218 ps
CPU time 0.74 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 196508 kb
Host smart-fd7dc1cf-5855-4ec5-8372-b2319f0da513
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683651092 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1683651092
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.372206068
Short name T730
Test name
Test status
Simulation time 701442009 ps
CPU time 3.01 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:32 PM PDT 24
Peak memory 198596 kb
Host smart-8b8a7ec4-db81-43f4-a865-550f08ac85cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372206068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.372206068
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4099566526
Short name T828
Test name
Test status
Simulation time 130778597 ps
CPU time 0.89 seconds
Started Jul 04 04:51:25 PM PDT 24
Finished Jul 04 04:51:26 PM PDT 24
Peak memory 197752 kb
Host smart-73d3b161-908c-4a05-b842-1dea13f7af19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099566526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4099566526
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2203061169
Short name T800
Test name
Test status
Simulation time 92834138 ps
CPU time 0.86 seconds
Started Jul 04 04:51:21 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 198596 kb
Host smart-b92b2e8e-ae5f-43c9-8bf8-b6ca988e1fec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203061169 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2203061169
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.601181167
Short name T100
Test name
Test status
Simulation time 19572096 ps
CPU time 0.59 seconds
Started Jul 04 04:51:22 PM PDT 24
Finished Jul 04 04:51:23 PM PDT 24
Peak memory 195280 kb
Host smart-7767b0cc-3317-4b2c-b777-9903580f1541
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601181167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.601181167
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2072967387
Short name T776
Test name
Test status
Simulation time 38909064 ps
CPU time 0.61 seconds
Started Jul 04 04:51:23 PM PDT 24
Finished Jul 04 04:51:24 PM PDT 24
Peak memory 194216 kb
Host smart-efc724ef-f2fd-4125-94c5-ba79937f545c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072967387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2072967387
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.281804956
Short name T108
Test name
Test status
Simulation time 25890383 ps
CPU time 0.79 seconds
Started Jul 04 04:51:21 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 196752 kb
Host smart-987a8dfe-6863-42f5-a6e6-b98733d4c04d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281804956 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.281804956
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.925624712
Short name T774
Test name
Test status
Simulation time 83482251 ps
CPU time 1.14 seconds
Started Jul 04 04:51:20 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 198616 kb
Host smart-f2f91724-16fc-455b-b14e-ef96872091ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925624712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.925624712
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.4077893102
Short name T723
Test name
Test status
Simulation time 37868915 ps
CPU time 0.71 seconds
Started Jul 04 04:51:21 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 198112 kb
Host smart-c5bf9def-1061-4621-906b-6799acbb4ae4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077893102 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.4077893102
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4133379406
Short name T95
Test name
Test status
Simulation time 32633727 ps
CPU time 0.67 seconds
Started Jul 04 04:51:20 PM PDT 24
Finished Jul 04 04:51:21 PM PDT 24
Peak memory 195412 kb
Host smart-f3681eea-9af1-4d1d-97ee-760c9fed2e2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133379406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.4133379406
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.577073994
Short name T810
Test name
Test status
Simulation time 12101664 ps
CPU time 0.59 seconds
Started Jul 04 04:51:20 PM PDT 24
Finished Jul 04 04:51:21 PM PDT 24
Peak memory 194184 kb
Host smart-8f28d005-5ad2-4d72-ba97-28da59e47077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577073994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.577073994
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4187868051
Short name T105
Test name
Test status
Simulation time 40423169 ps
CPU time 0.62 seconds
Started Jul 04 04:51:25 PM PDT 24
Finished Jul 04 04:51:26 PM PDT 24
Peak memory 195308 kb
Host smart-73ff355e-f1bc-4085-aca9-4fed07dadbaf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187868051 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.4187868051
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1577356969
Short name T843
Test name
Test status
Simulation time 85323886 ps
CPU time 1.81 seconds
Started Jul 04 04:51:22 PM PDT 24
Finished Jul 04 04:51:24 PM PDT 24
Peak memory 198600 kb
Host smart-e927eca9-43ec-48df-8e13-6ed1efe1ce6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577356969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1577356969
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1294394631
Short name T47
Test name
Test status
Simulation time 111907642 ps
CPU time 1.47 seconds
Started Jul 04 04:51:27 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 198624 kb
Host smart-ccbd2446-ae5b-41c3-a077-e0dc2dca1216
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294394631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1294394631
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.246288540
Short name T813
Test name
Test status
Simulation time 44618609 ps
CPU time 0.76 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 198472 kb
Host smart-faa59426-918f-48ad-a3f4-5f3c78f3a6b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246288540 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.246288540
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1888363885
Short name T91
Test name
Test status
Simulation time 18084568 ps
CPU time 0.61 seconds
Started Jul 04 04:51:27 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 195332 kb
Host smart-07b462b1-cd29-4217-91d4-e8ebf23b2be8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888363885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1888363885
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.141119053
Short name T753
Test name
Test status
Simulation time 14491001 ps
CPU time 0.6 seconds
Started Jul 04 04:51:27 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 194244 kb
Host smart-bbee261a-b35f-44f6-82fb-3e0bb5b6c57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141119053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.141119053
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2791453140
Short name T106
Test name
Test status
Simulation time 32190991 ps
CPU time 0.77 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 196792 kb
Host smart-e78e1ef0-ee35-410d-8aca-0b16d4d18c67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791453140 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2791453140
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2666753691
Short name T731
Test name
Test status
Simulation time 147559275 ps
CPU time 1.17 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 198428 kb
Host smart-cf1fd70e-cb02-43f0-b9d7-3bae4a6798ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666753691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2666753691
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.312359550
Short name T772
Test name
Test status
Simulation time 150702715 ps
CPU time 0.86 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 198360 kb
Host smart-2573ab53-14b5-4b1b-80bf-2699334737ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312359550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.312359550
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3088976757
Short name T92
Test name
Test status
Simulation time 12727815 ps
CPU time 0.68 seconds
Started Jul 04 04:50:52 PM PDT 24
Finished Jul 04 04:50:52 PM PDT 24
Peak memory 194988 kb
Host smart-d9131629-8efa-402c-8acd-d8b3e27ec5eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088976757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3088976757
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3867319957
Short name T102
Test name
Test status
Simulation time 87871391 ps
CPU time 3.01 seconds
Started Jul 04 04:50:48 PM PDT 24
Finished Jul 04 04:50:51 PM PDT 24
Peak memory 197704 kb
Host smart-18ba895c-77b7-49b3-8c47-e8ce4f1d3a68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867319957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3867319957
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2878417433
Short name T756
Test name
Test status
Simulation time 26572313 ps
CPU time 0.6 seconds
Started Jul 04 04:50:49 PM PDT 24
Finished Jul 04 04:50:50 PM PDT 24
Peak memory 195500 kb
Host smart-f99f56ae-887b-4bfe-bf89-82ed7f21756f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878417433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2878417433
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2503010060
Short name T738
Test name
Test status
Simulation time 55968810 ps
CPU time 0.91 seconds
Started Jul 04 04:50:49 PM PDT 24
Finished Jul 04 04:50:50 PM PDT 24
Peak memory 198484 kb
Host smart-21d081ff-a20f-4230-b2f5-256a110f33dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503010060 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2503010060
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1060315522
Short name T112
Test name
Test status
Simulation time 14576977 ps
CPU time 0.68 seconds
Started Jul 04 04:50:50 PM PDT 24
Finished Jul 04 04:50:51 PM PDT 24
Peak memory 195412 kb
Host smart-218261b8-09c9-46d3-8b2b-20e0d291fe5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060315522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1060315522
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.416411463
Short name T789
Test name
Test status
Simulation time 24471941 ps
CPU time 0.64 seconds
Started Jul 04 04:50:48 PM PDT 24
Finished Jul 04 04:50:49 PM PDT 24
Peak memory 194344 kb
Host smart-0bac1fae-1956-4045-9924-2ccd3ec4ff19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416411463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.416411463
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2540149498
Short name T815
Test name
Test status
Simulation time 67908608 ps
CPU time 0.9 seconds
Started Jul 04 04:50:51 PM PDT 24
Finished Jul 04 04:50:52 PM PDT 24
Peak memory 197488 kb
Host smart-b4c5c268-de38-47dc-88ab-711da7589586
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540149498 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2540149498
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3081517167
Short name T749
Test name
Test status
Simulation time 37922301 ps
CPU time 2 seconds
Started Jul 04 04:50:50 PM PDT 24
Finished Jul 04 04:50:52 PM PDT 24
Peak memory 198632 kb
Host smart-1f4ff1e1-2edd-4df8-9a82-8994b7d554cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081517167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3081517167
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3293301903
Short name T53
Test name
Test status
Simulation time 94863339 ps
CPU time 1.26 seconds
Started Jul 04 04:50:51 PM PDT 24
Finished Jul 04 04:50:52 PM PDT 24
Peak memory 198724 kb
Host smart-6226134c-f0fc-4dc2-94a0-62a099a7cf9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293301903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3293301903
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3312591524
Short name T755
Test name
Test status
Simulation time 13891423 ps
CPU time 0.57 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 194944 kb
Host smart-10ae1607-2065-4fd4-844d-acc72baa85af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312591524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3312591524
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.272713022
Short name T819
Test name
Test status
Simulation time 12993803 ps
CPU time 0.62 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 194244 kb
Host smart-ecdf1a78-a995-4193-b488-3f1cfbdbc456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272713022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.272713022
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4260970223
Short name T792
Test name
Test status
Simulation time 12795445 ps
CPU time 0.58 seconds
Started Jul 04 04:51:27 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 194200 kb
Host smart-5ddb1ae7-da8d-4f5c-9714-1001d26cb85f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260970223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4260970223
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.373294767
Short name T743
Test name
Test status
Simulation time 43979320 ps
CPU time 0.58 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 194872 kb
Host smart-062eec5e-8b06-4812-9d3f-b761424c263c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373294767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.373294767
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2105479528
Short name T769
Test name
Test status
Simulation time 43190715 ps
CPU time 0.6 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 195024 kb
Host smart-5c9e6d93-e574-447c-8937-cd52dd582125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105479528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2105479528
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2715823673
Short name T782
Test name
Test status
Simulation time 39436042 ps
CPU time 0.63 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 194264 kb
Host smart-7999facc-2f15-4d93-a3b9-335e41f3113a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715823673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2715823673
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1367988219
Short name T794
Test name
Test status
Simulation time 16607486 ps
CPU time 0.61 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 194396 kb
Host smart-815da511-fe8d-492b-b985-11b954991932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367988219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1367988219
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.110439750
Short name T725
Test name
Test status
Simulation time 47548741 ps
CPU time 0.6 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 194228 kb
Host smart-de3ce698-c0e5-45c4-8d2b-a8c0bf6095e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110439750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.110439750
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1789923643
Short name T814
Test name
Test status
Simulation time 56269558 ps
CPU time 0.62 seconds
Started Jul 04 04:51:27 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 194228 kb
Host smart-bc55244a-b7d8-462f-9bee-8ed5cc70c740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789923643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1789923643
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2634786183
Short name T808
Test name
Test status
Simulation time 28580334 ps
CPU time 0.59 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 194920 kb
Host smart-1f2743e2-8801-499a-ae76-c10ae3ff0dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634786183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2634786183
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1568579290
Short name T98
Test name
Test status
Simulation time 18385599 ps
CPU time 0.68 seconds
Started Jul 04 04:50:53 PM PDT 24
Finished Jul 04 04:50:54 PM PDT 24
Peak memory 195596 kb
Host smart-41e68f9e-2e1f-4d44-ad71-ecf094e4c12b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568579290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1568579290
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3549732901
Short name T745
Test name
Test status
Simulation time 457331196 ps
CPU time 1.6 seconds
Started Jul 04 04:51:01 PM PDT 24
Finished Jul 04 04:51:03 PM PDT 24
Peak memory 198524 kb
Host smart-201671b5-6c4d-4914-85a1-454d77fe66e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549732901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3549732901
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2599634199
Short name T841
Test name
Test status
Simulation time 19250819 ps
CPU time 0.59 seconds
Started Jul 04 04:50:48 PM PDT 24
Finished Jul 04 04:50:49 PM PDT 24
Peak memory 195228 kb
Host smart-4c384252-6bc0-4e2c-b8a9-bb14a4b3c557
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599634199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2599634199
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3248584975
Short name T760
Test name
Test status
Simulation time 108986458 ps
CPU time 0.7 seconds
Started Jul 04 04:50:53 PM PDT 24
Finished Jul 04 04:50:54 PM PDT 24
Peak memory 197628 kb
Host smart-30d97a40-6f55-4124-b63b-1a720f013a5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248584975 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3248584975
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4178753771
Short name T805
Test name
Test status
Simulation time 10711044 ps
CPU time 0.59 seconds
Started Jul 04 04:50:48 PM PDT 24
Finished Jul 04 04:50:49 PM PDT 24
Peak memory 195172 kb
Host smart-437792f5-0f38-4070-933d-a788f3a871ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178753771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.4178753771
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2680919669
Short name T744
Test name
Test status
Simulation time 44961143 ps
CPU time 0.6 seconds
Started Jul 04 04:50:49 PM PDT 24
Finished Jul 04 04:50:49 PM PDT 24
Peak memory 194356 kb
Host smart-2a504b2a-882f-4221-8bbf-a9fccc4efe35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680919669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2680919669
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.176870793
Short name T104
Test name
Test status
Simulation time 24656211 ps
CPU time 0.71 seconds
Started Jul 04 04:50:49 PM PDT 24
Finished Jul 04 04:50:49 PM PDT 24
Peak memory 195516 kb
Host smart-49f204e7-ac70-46dc-bdbb-c47a4a906677
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176870793 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.176870793
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.4204015380
Short name T754
Test name
Test status
Simulation time 54763821 ps
CPU time 1.42 seconds
Started Jul 04 04:50:48 PM PDT 24
Finished Jul 04 04:50:50 PM PDT 24
Peak memory 198596 kb
Host smart-544fd226-564d-4ae0-8e2d-3379e6a0c340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204015380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.4204015380
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.827949987
Short name T751
Test name
Test status
Simulation time 81581141 ps
CPU time 0.88 seconds
Started Jul 04 04:50:48 PM PDT 24
Finished Jul 04 04:50:49 PM PDT 24
Peak memory 198336 kb
Host smart-fab6ead8-1d04-4ea2-9493-646f09d4a011
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827949987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.827949987
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.612210661
Short name T735
Test name
Test status
Simulation time 12514208 ps
CPU time 0.59 seconds
Started Jul 04 04:51:27 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 194848 kb
Host smart-b3903894-5d82-4117-a27e-eaddc778470c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612210661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.612210661
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.54186487
Short name T809
Test name
Test status
Simulation time 39076101 ps
CPU time 0.6 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 194272 kb
Host smart-e0d51133-84f7-4a85-87d3-ecdff0fdd3a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54186487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.54186487
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3973562312
Short name T729
Test name
Test status
Simulation time 44569606 ps
CPU time 0.6 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 194312 kb
Host smart-77f73a29-fd7e-4e92-acc6-7ed7bb8e38d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973562312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3973562312
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1517150272
Short name T758
Test name
Test status
Simulation time 25045444 ps
CPU time 0.6 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 194192 kb
Host smart-69513af8-f5f8-4570-a6c5-dfaae4994e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517150272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1517150272
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1345577411
Short name T739
Test name
Test status
Simulation time 32194990 ps
CPU time 0.57 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 194196 kb
Host smart-18a6f042-bb41-4d98-a365-4ff3b08143df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345577411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1345577411
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3675324756
Short name T780
Test name
Test status
Simulation time 42684850 ps
CPU time 0.63 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 194320 kb
Host smart-2e74ba6b-f980-471d-8bc3-2c264ec8199a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675324756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3675324756
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.27685576
Short name T775
Test name
Test status
Simulation time 18528718 ps
CPU time 0.56 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 194220 kb
Host smart-8429e991-a720-4473-b023-a6ac83baa5f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27685576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.27685576
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1714489311
Short name T834
Test name
Test status
Simulation time 16444591 ps
CPU time 0.63 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 194840 kb
Host smart-6b845604-f50e-40d6-979e-c58129fd4ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714489311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1714489311
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2187252298
Short name T763
Test name
Test status
Simulation time 43690603 ps
CPU time 0.58 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 194880 kb
Host smart-bae8707b-1d1a-475a-a35c-ee3337c424b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187252298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2187252298
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2061318147
Short name T736
Test name
Test status
Simulation time 50338026 ps
CPU time 0.61 seconds
Started Jul 04 04:51:27 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 194300 kb
Host smart-f9d62f8e-892f-46d2-8275-8cf318eeea99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061318147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2061318147
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3870930716
Short name T94
Test name
Test status
Simulation time 31346845 ps
CPU time 0.86 seconds
Started Jul 04 04:50:57 PM PDT 24
Finished Jul 04 04:50:58 PM PDT 24
Peak memory 196368 kb
Host smart-f01d05fc-20fa-43b8-9f00-8b9bd39d773b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870930716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3870930716
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.668590863
Short name T89
Test name
Test status
Simulation time 1081129686 ps
CPU time 3.27 seconds
Started Jul 04 04:50:57 PM PDT 24
Finished Jul 04 04:51:00 PM PDT 24
Peak memory 198584 kb
Host smart-b8981d49-ea47-4f91-a391-2ea06724cebc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668590863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.668590863
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.986773940
Short name T740
Test name
Test status
Simulation time 14024878 ps
CPU time 0.6 seconds
Started Jul 04 04:50:58 PM PDT 24
Finished Jul 04 04:50:59 PM PDT 24
Peak memory 194984 kb
Host smart-e6d30d03-fa53-4966-8b2f-2e404e95480b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986773940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.986773940
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3433990959
Short name T732
Test name
Test status
Simulation time 41976910 ps
CPU time 1.24 seconds
Started Jul 04 04:50:57 PM PDT 24
Finished Jul 04 04:50:58 PM PDT 24
Peak memory 198588 kb
Host smart-f3859bf0-16f3-4a41-992d-5b244d2c899a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433990959 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3433990959
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2040766194
Short name T97
Test name
Test status
Simulation time 30466830 ps
CPU time 0.61 seconds
Started Jul 04 04:50:57 PM PDT 24
Finished Jul 04 04:50:58 PM PDT 24
Peak memory 195308 kb
Host smart-878577ae-93d2-4f8f-ab52-b3677c6c4999
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040766194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2040766194
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.598458957
Short name T799
Test name
Test status
Simulation time 12421076 ps
CPU time 0.62 seconds
Started Jul 04 04:50:56 PM PDT 24
Finished Jul 04 04:50:57 PM PDT 24
Peak memory 194212 kb
Host smart-c13cf0cf-f491-48b9-bfc2-283fffbaa5d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598458957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.598458957
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3142710582
Short name T85
Test name
Test status
Simulation time 463024045 ps
CPU time 0.88 seconds
Started Jul 04 04:50:56 PM PDT 24
Finished Jul 04 04:50:58 PM PDT 24
Peak memory 197928 kb
Host smart-38698921-1b92-4293-bc1b-526eebd92d0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142710582 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3142710582
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3125465224
Short name T777
Test name
Test status
Simulation time 335951406 ps
CPU time 1.67 seconds
Started Jul 04 04:50:57 PM PDT 24
Finished Jul 04 04:50:59 PM PDT 24
Peak memory 198656 kb
Host smart-96b69c2e-0595-419a-b315-031afd40f586
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125465224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3125465224
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1041090695
Short name T783
Test name
Test status
Simulation time 285321990 ps
CPU time 1.13 seconds
Started Jul 04 04:50:59 PM PDT 24
Finished Jul 04 04:51:00 PM PDT 24
Peak memory 198556 kb
Host smart-1f081426-d38c-4ddc-8d63-b987d8b95771
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041090695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1041090695
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2435412820
Short name T781
Test name
Test status
Simulation time 45196121 ps
CPU time 0.61 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 194912 kb
Host smart-62f5ed22-dc3b-4672-be31-442e2f47575f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435412820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2435412820
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2492485416
Short name T757
Test name
Test status
Simulation time 23139372 ps
CPU time 0.63 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 194264 kb
Host smart-6a924e90-6699-4031-976c-33b0ed0cb8bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492485416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2492485416
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3387285081
Short name T826
Test name
Test status
Simulation time 72333125 ps
CPU time 0.61 seconds
Started Jul 04 04:51:31 PM PDT 24
Finished Jul 04 04:51:32 PM PDT 24
Peak memory 194336 kb
Host smart-d375e028-a821-4983-9335-12a374175e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387285081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3387285081
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4087297759
Short name T733
Test name
Test status
Simulation time 47488073 ps
CPU time 0.58 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 194296 kb
Host smart-96197f71-b2ed-40d4-a647-bd4bc28fdf54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087297759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4087297759
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2113021550
Short name T832
Test name
Test status
Simulation time 41758390 ps
CPU time 0.6 seconds
Started Jul 04 04:51:28 PM PDT 24
Finished Jul 04 04:51:29 PM PDT 24
Peak memory 194148 kb
Host smart-e07ea03d-682d-4c83-9569-69bdc13ba10b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113021550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2113021550
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.4225658731
Short name T796
Test name
Test status
Simulation time 43663529 ps
CPU time 0.62 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 194316 kb
Host smart-9084ed94-d096-48f8-a17d-aae246d439a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225658731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.4225658731
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2963521048
Short name T793
Test name
Test status
Simulation time 67114261 ps
CPU time 0.58 seconds
Started Jul 04 04:51:31 PM PDT 24
Finished Jul 04 04:51:32 PM PDT 24
Peak memory 194220 kb
Host smart-44fd336b-d0d3-453e-b84a-b4f4fa060421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963521048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2963521048
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1991275053
Short name T822
Test name
Test status
Simulation time 34503951 ps
CPU time 0.56 seconds
Started Jul 04 04:51:32 PM PDT 24
Finished Jul 04 04:51:32 PM PDT 24
Peak memory 194244 kb
Host smart-5eecd1d7-4a6c-4138-93df-666597e4d383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991275053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1991275053
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3623533415
Short name T737
Test name
Test status
Simulation time 15884558 ps
CPU time 0.55 seconds
Started Jul 04 04:51:27 PM PDT 24
Finished Jul 04 04:51:27 PM PDT 24
Peak memory 194164 kb
Host smart-eeb6436f-e8fb-4a43-a292-79abe42412db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623533415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3623533415
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.986722267
Short name T746
Test name
Test status
Simulation time 48422386 ps
CPU time 0.65 seconds
Started Jul 04 04:51:31 PM PDT 24
Finished Jul 04 04:51:32 PM PDT 24
Peak memory 194332 kb
Host smart-761b6342-7bf6-485a-8093-d99133ebf616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986722267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.986722267
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3806393030
Short name T766
Test name
Test status
Simulation time 104915635 ps
CPU time 0.71 seconds
Started Jul 04 04:50:57 PM PDT 24
Finished Jul 04 04:50:57 PM PDT 24
Peak memory 198096 kb
Host smart-4e604c94-d32d-4c46-837c-70d08b59b408
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806393030 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3806393030
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1046570413
Short name T768
Test name
Test status
Simulation time 14008401 ps
CPU time 0.67 seconds
Started Jul 04 04:50:59 PM PDT 24
Finished Jul 04 04:51:00 PM PDT 24
Peak memory 195476 kb
Host smart-3615a329-7c57-47c5-8276-1ac701154011
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046570413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1046570413
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1795525230
Short name T836
Test name
Test status
Simulation time 12903765 ps
CPU time 0.6 seconds
Started Jul 04 04:50:56 PM PDT 24
Finished Jul 04 04:50:57 PM PDT 24
Peak memory 194180 kb
Host smart-ad5d7774-a41a-4a9e-a962-25b4dbe392a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795525230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1795525230
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1236811792
Short name T801
Test name
Test status
Simulation time 29114930 ps
CPU time 0.63 seconds
Started Jul 04 04:50:56 PM PDT 24
Finished Jul 04 04:50:57 PM PDT 24
Peak memory 194796 kb
Host smart-dc1dba6e-25c4-4fed-b2fe-388472ad6504
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236811792 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1236811792
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4052759490
Short name T742
Test name
Test status
Simulation time 468255317 ps
CPU time 2.2 seconds
Started Jul 04 04:50:57 PM PDT 24
Finished Jul 04 04:50:59 PM PDT 24
Peak memory 198564 kb
Host smart-3fc8151c-aedd-46b1-9a8c-92f328eb9d09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052759490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.4052759490
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4191101822
Short name T52
Test name
Test status
Simulation time 358032908 ps
CPU time 0.94 seconds
Started Jul 04 04:50:58 PM PDT 24
Finished Jul 04 04:50:59 PM PDT 24
Peak memory 197664 kb
Host smart-d2faafed-a2df-46c2-bfe3-b3180c3de1b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191101822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.4191101822
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.62187546
Short name T823
Test name
Test status
Simulation time 17066003 ps
CPU time 0.7 seconds
Started Jul 04 04:50:58 PM PDT 24
Finished Jul 04 04:50:59 PM PDT 24
Peak memory 197912 kb
Host smart-208209ca-3015-4220-9e73-2978f591e50c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62187546 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.62187546
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.115294467
Short name T773
Test name
Test status
Simulation time 61037315 ps
CPU time 0.64 seconds
Started Jul 04 04:50:56 PM PDT 24
Finished Jul 04 04:50:57 PM PDT 24
Peak memory 195288 kb
Host smart-c4ed55ae-4483-42b1-82a0-c2394befca52
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115294467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.115294467
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3464478688
Short name T820
Test name
Test status
Simulation time 57140268 ps
CPU time 0.58 seconds
Started Jul 04 04:50:58 PM PDT 24
Finished Jul 04 04:50:58 PM PDT 24
Peak memory 194216 kb
Host smart-9a3efb62-aadd-4ac4-b64c-440035399b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464478688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3464478688
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.755417279
Short name T109
Test name
Test status
Simulation time 13329059 ps
CPU time 0.66 seconds
Started Jul 04 04:50:56 PM PDT 24
Finished Jul 04 04:50:57 PM PDT 24
Peak memory 195156 kb
Host smart-530d6eca-9c5e-4787-acdb-81997aab9bb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755417279 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.755417279
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2893518358
Short name T741
Test name
Test status
Simulation time 260824647 ps
CPU time 1.41 seconds
Started Jul 04 04:50:55 PM PDT 24
Finished Jul 04 04:50:57 PM PDT 24
Peak memory 198628 kb
Host smart-9261f38b-9270-4080-81da-c1f7302d7ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893518358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2893518358
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3012448746
Short name T833
Test name
Test status
Simulation time 176491769 ps
CPU time 0.84 seconds
Started Jul 04 04:50:56 PM PDT 24
Finished Jul 04 04:50:57 PM PDT 24
Peak memory 197488 kb
Host smart-f008d627-6675-41df-ada2-3d0f61917dfa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012448746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3012448746
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1124912267
Short name T807
Test name
Test status
Simulation time 57142025 ps
CPU time 1.49 seconds
Started Jul 04 04:51:02 PM PDT 24
Finished Jul 04 04:51:04 PM PDT 24
Peak memory 198640 kb
Host smart-64602176-52fb-4b7b-8aad-bd09bcb6c3ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124912267 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1124912267
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3530561273
Short name T802
Test name
Test status
Simulation time 12086615 ps
CPU time 0.59 seconds
Started Jul 04 04:50:56 PM PDT 24
Finished Jul 04 04:50:56 PM PDT 24
Peak memory 194568 kb
Host smart-7d3a3580-614d-4aff-83f2-f7e91bd37072
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530561273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3530561273
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.416249215
Short name T728
Test name
Test status
Simulation time 16771175 ps
CPU time 0.62 seconds
Started Jul 04 04:51:08 PM PDT 24
Finished Jul 04 04:51:08 PM PDT 24
Peak memory 194252 kb
Host smart-6ba03c41-4908-47ac-93ea-fb1177740ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416249215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.416249215
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2347057644
Short name T110
Test name
Test status
Simulation time 56378183 ps
CPU time 0.63 seconds
Started Jul 04 04:50:56 PM PDT 24
Finished Jul 04 04:50:56 PM PDT 24
Peak memory 195188 kb
Host smart-6fbbaedd-7ca4-4fa3-8ca6-2a194131fe8c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347057644 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2347057644
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3643539805
Short name T747
Test name
Test status
Simulation time 648088733 ps
CPU time 2.27 seconds
Started Jul 04 04:51:06 PM PDT 24
Finished Jul 04 04:51:08 PM PDT 24
Peak memory 198600 kb
Host smart-ed3532ad-cf70-4d42-8267-d69b89ba3f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643539805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3643539805
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4034691220
Short name T829
Test name
Test status
Simulation time 118613309 ps
CPU time 1.5 seconds
Started Jul 04 04:51:03 PM PDT 24
Finished Jul 04 04:51:05 PM PDT 24
Peak memory 198580 kb
Host smart-97d8ae64-432b-4426-b0c6-998b71d61539
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034691220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4034691220
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.4268120610
Short name T835
Test name
Test status
Simulation time 18369112 ps
CPU time 0.71 seconds
Started Jul 04 04:51:06 PM PDT 24
Finished Jul 04 04:51:07 PM PDT 24
Peak memory 198424 kb
Host smart-ff6dd74d-bfd6-4964-92e9-e9ba30a9144c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268120610 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.4268120610
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3985958613
Short name T778
Test name
Test status
Simulation time 11538373 ps
CPU time 0.64 seconds
Started Jul 04 04:51:07 PM PDT 24
Finished Jul 04 04:51:07 PM PDT 24
Peak memory 195344 kb
Host smart-bce23d7b-fab7-4d1e-834c-907f1610b0b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985958613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3985958613
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3028627045
Short name T821
Test name
Test status
Simulation time 35373004 ps
CPU time 0.57 seconds
Started Jul 04 04:51:09 PM PDT 24
Finished Jul 04 04:51:09 PM PDT 24
Peak memory 194228 kb
Host smart-172837df-706b-47ca-91b8-5d096d95c3ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028627045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3028627045
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1659939661
Short name T103
Test name
Test status
Simulation time 56872527 ps
CPU time 0.63 seconds
Started Jul 04 04:51:08 PM PDT 24
Finished Jul 04 04:51:09 PM PDT 24
Peak memory 195120 kb
Host smart-ca94258b-cf70-459e-bfba-63849e34b01c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659939661 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1659939661
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3460224371
Short name T811
Test name
Test status
Simulation time 153064856 ps
CPU time 2.93 seconds
Started Jul 04 04:51:09 PM PDT 24
Finished Jul 04 04:51:12 PM PDT 24
Peak memory 198600 kb
Host smart-0fbac487-f239-45cd-83b2-d1243653ce88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460224371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3460224371
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.373508914
Short name T50
Test name
Test status
Simulation time 1336952090 ps
CPU time 1.5 seconds
Started Jul 04 04:51:07 PM PDT 24
Finished Jul 04 04:51:08 PM PDT 24
Peak memory 198632 kb
Host smart-19b13320-bc1f-4d2d-9707-0a8075124abf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373508914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.373508914
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.926806514
Short name T770
Test name
Test status
Simulation time 25954973 ps
CPU time 0.77 seconds
Started Jul 04 04:51:05 PM PDT 24
Finished Jul 04 04:51:06 PM PDT 24
Peak memory 198388 kb
Host smart-0f076395-3e9e-4e47-a814-efdca8d11114
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926806514 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.926806514
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1622320884
Short name T93
Test name
Test status
Simulation time 34047748 ps
CPU time 0.64 seconds
Started Jul 04 04:51:05 PM PDT 24
Finished Jul 04 04:51:06 PM PDT 24
Peak memory 195504 kb
Host smart-09c45357-6ecb-4e42-a2ec-72b7e35cda6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622320884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1622320884
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2972844896
Short name T797
Test name
Test status
Simulation time 40201374 ps
CPU time 0.61 seconds
Started Jul 04 04:51:06 PM PDT 24
Finished Jul 04 04:51:07 PM PDT 24
Peak memory 194232 kb
Host smart-dfee7ac8-3ed4-4052-a2ac-d1520f329754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972844896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2972844896
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.143897731
Short name T825
Test name
Test status
Simulation time 13984621 ps
CPU time 0.63 seconds
Started Jul 04 04:51:05 PM PDT 24
Finished Jul 04 04:51:06 PM PDT 24
Peak memory 195176 kb
Host smart-3bdccb04-3ee7-4887-bb6d-3fc78f5068a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143897731 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.143897731
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1179636140
Short name T795
Test name
Test status
Simulation time 100421275 ps
CPU time 2.47 seconds
Started Jul 04 04:51:05 PM PDT 24
Finished Jul 04 04:51:08 PM PDT 24
Peak memory 198600 kb
Host smart-5184cf13-bb90-4d0e-b1ad-eca0e64c8468
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179636140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1179636140
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1181899263
Short name T49
Test name
Test status
Simulation time 92006117 ps
CPU time 0.88 seconds
Started Jul 04 04:51:08 PM PDT 24
Finished Jul 04 04:51:09 PM PDT 24
Peak memory 197744 kb
Host smart-7f9e91d9-8a25-4780-a2d9-d1db65ff493e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181899263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1181899263
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.853544228
Short name T588
Test name
Test status
Simulation time 13345355 ps
CPU time 0.58 seconds
Started Jul 04 05:01:09 PM PDT 24
Finished Jul 04 05:01:10 PM PDT 24
Peak memory 195552 kb
Host smart-ff80f7fb-c13a-4bd9-985c-1aefeb4550c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853544228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.853544228
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1139880243
Short name T695
Test name
Test status
Simulation time 34624647 ps
CPU time 0.74 seconds
Started Jul 04 05:01:09 PM PDT 24
Finished Jul 04 05:01:10 PM PDT 24
Peak memory 194732 kb
Host smart-3be4eafe-91a3-4106-8997-e62a93fda6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139880243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1139880243
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.328085576
Short name T303
Test name
Test status
Simulation time 388506668 ps
CPU time 19.39 seconds
Started Jul 04 05:01:08 PM PDT 24
Finished Jul 04 05:01:28 PM PDT 24
Peak memory 197524 kb
Host smart-96e8390a-6d96-4de4-ab2c-0da0066bc54a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328085576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.328085576
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3953400105
Short name T576
Test name
Test status
Simulation time 477236371 ps
CPU time 1.07 seconds
Started Jul 04 05:01:08 PM PDT 24
Finished Jul 04 05:01:09 PM PDT 24
Peak memory 198524 kb
Host smart-eba41b48-fec9-4ba2-bb99-9ad851fbb641
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953400105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3953400105
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3192957576
Short name T426
Test name
Test status
Simulation time 184867790 ps
CPU time 1.38 seconds
Started Jul 04 05:01:09 PM PDT 24
Finished Jul 04 05:01:10 PM PDT 24
Peak memory 197620 kb
Host smart-c7ac0fca-959c-4f7a-b611-339f23d5a731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192957576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3192957576
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.810730614
Short name T229
Test name
Test status
Simulation time 438557978 ps
CPU time 1.99 seconds
Started Jul 04 05:01:06 PM PDT 24
Finished Jul 04 05:01:08 PM PDT 24
Peak memory 198548 kb
Host smart-66767271-c8f9-4c9f-abeb-53e35bd381f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810730614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.810730614
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1068646724
Short name T399
Test name
Test status
Simulation time 170021857 ps
CPU time 3.39 seconds
Started Jul 04 05:01:06 PM PDT 24
Finished Jul 04 05:01:09 PM PDT 24
Peak memory 198584 kb
Host smart-232c9fa7-7aef-444a-bb65-fd9553d22278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068646724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1068646724
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1368741023
Short name T547
Test name
Test status
Simulation time 45385198 ps
CPU time 1.2 seconds
Started Jul 04 05:01:07 PM PDT 24
Finished Jul 04 05:01:09 PM PDT 24
Peak memory 196436 kb
Host smart-a46d52b3-4d5b-406f-a6d8-5d508f64b985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368741023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1368741023
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3852460259
Short name T395
Test name
Test status
Simulation time 21211651 ps
CPU time 0.69 seconds
Started Jul 04 05:01:06 PM PDT 24
Finished Jul 04 05:01:07 PM PDT 24
Peak memory 194936 kb
Host smart-1a15c10c-745d-4a47-bc2d-04b83a2a36ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852460259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3852460259
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2853560424
Short name T252
Test name
Test status
Simulation time 193801695 ps
CPU time 3.35 seconds
Started Jul 04 05:01:10 PM PDT 24
Finished Jul 04 05:01:14 PM PDT 24
Peak memory 198528 kb
Host smart-abf7b59a-f5eb-41ba-8421-1b5c19982cba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853560424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2853560424
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2477180945
Short name T57
Test name
Test status
Simulation time 285417550 ps
CPU time 0.86 seconds
Started Jul 04 05:01:07 PM PDT 24
Finished Jul 04 05:01:08 PM PDT 24
Peak memory 214204 kb
Host smart-6003f6c7-0cf1-4f5f-81be-4cb1a296d9cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477180945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2477180945
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.808825351
Short name T216
Test name
Test status
Simulation time 37744620 ps
CPU time 0.97 seconds
Started Jul 04 05:01:10 PM PDT 24
Finished Jul 04 05:01:11 PM PDT 24
Peak memory 196400 kb
Host smart-7f51b7c7-18e1-4116-ab60-393c85b4bdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808825351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.808825351
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.4063017137
Short name T669
Test name
Test status
Simulation time 156379908 ps
CPU time 1.08 seconds
Started Jul 04 05:01:06 PM PDT 24
Finished Jul 04 05:01:07 PM PDT 24
Peak memory 196300 kb
Host smart-960da791-6fe0-4a68-b153-f16e6cf6a9f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063017137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.4063017137
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.810096035
Short name T24
Test name
Test status
Simulation time 4987626968 ps
CPU time 23.3 seconds
Started Jul 04 05:01:10 PM PDT 24
Finished Jul 04 05:01:33 PM PDT 24
Peak memory 198620 kb
Host smart-bf30c2a9-2581-48c0-95d8-b4b6669237fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810096035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.810096035
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.431541196
Short name T571
Test name
Test status
Simulation time 17852008 ps
CPU time 0.57 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:17 PM PDT 24
Peak memory 194740 kb
Host smart-a327fe25-a1d2-4354-8932-48ea4b0ca88e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431541196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.431541196
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1840561386
Short name T369
Test name
Test status
Simulation time 112265698 ps
CPU time 0.84 seconds
Started Jul 04 05:01:18 PM PDT 24
Finished Jul 04 05:01:19 PM PDT 24
Peak memory 196136 kb
Host smart-fbda86cf-8ba9-43b4-b21e-a12e28fe6ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840561386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1840561386
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4187722194
Short name T459
Test name
Test status
Simulation time 426931720 ps
CPU time 11.36 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:27 PM PDT 24
Peak memory 197520 kb
Host smart-80b24c11-437f-4820-8c97-596c8b19363f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187722194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4187722194
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3728709446
Short name T442
Test name
Test status
Simulation time 49391782 ps
CPU time 0.78 seconds
Started Jul 04 05:01:14 PM PDT 24
Finished Jul 04 05:01:15 PM PDT 24
Peak memory 196324 kb
Host smart-5ab0f924-b86f-45b5-bd84-42d99f19bb4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728709446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3728709446
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1592301864
Short name T479
Test name
Test status
Simulation time 61386663 ps
CPU time 1.06 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:17 PM PDT 24
Peak memory 196516 kb
Host smart-6db7daa1-dad9-458b-a1ac-756f61f9252b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592301864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1592301864
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.4199580396
Short name T283
Test name
Test status
Simulation time 34564047 ps
CPU time 1.48 seconds
Started Jul 04 05:01:14 PM PDT 24
Finished Jul 04 05:01:16 PM PDT 24
Peak memory 197340 kb
Host smart-53a1fcb2-8863-47c5-a774-394b7427eaf5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199580396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.4199580396
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3460322774
Short name T515
Test name
Test status
Simulation time 178129959 ps
CPU time 2.15 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:19 PM PDT 24
Peak memory 196808 kb
Host smart-77e39f92-eede-4bcf-97af-3a40b4d6c6cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460322774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3460322774
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.300949895
Short name T646
Test name
Test status
Simulation time 216285338 ps
CPU time 1.24 seconds
Started Jul 04 05:01:07 PM PDT 24
Finished Jul 04 05:01:09 PM PDT 24
Peak memory 196432 kb
Host smart-bfc4d73b-0bc1-4e2a-b222-3691166006d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300949895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.300949895
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2814241602
Short name T570
Test name
Test status
Simulation time 45735317 ps
CPU time 0.79 seconds
Started Jul 04 05:01:06 PM PDT 24
Finished Jul 04 05:01:07 PM PDT 24
Peak memory 196128 kb
Host smart-36e646c3-a558-43cc-b861-f6da98c07a40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814241602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2814241602
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2540027101
Short name T138
Test name
Test status
Simulation time 603790399 ps
CPU time 4.87 seconds
Started Jul 04 05:01:15 PM PDT 24
Finished Jul 04 05:01:20 PM PDT 24
Peak memory 198544 kb
Host smart-38a8c092-1e9d-4ed6-80bb-13aa4c36a80f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540027101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2540027101
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.3544718086
Short name T180
Test name
Test status
Simulation time 182447645 ps
CPU time 1.34 seconds
Started Jul 04 05:01:08 PM PDT 24
Finished Jul 04 05:01:10 PM PDT 24
Peak memory 197544 kb
Host smart-983d7041-b4eb-4380-b932-44ba9e02708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544718086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3544718086
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1748918212
Short name T328
Test name
Test status
Simulation time 37148623 ps
CPU time 1.01 seconds
Started Jul 04 05:01:10 PM PDT 24
Finished Jul 04 05:01:11 PM PDT 24
Peak memory 196628 kb
Host smart-4a149ab1-33ef-45bf-b0e3-aa54ec868a71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748918212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1748918212
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2833322995
Short name T272
Test name
Test status
Simulation time 6528849244 ps
CPU time 98.39 seconds
Started Jul 04 05:01:15 PM PDT 24
Finished Jul 04 05:02:54 PM PDT 24
Peak memory 198748 kb
Host smart-3719b401-6af8-41f0-8244-864bc3610c7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833322995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2833322995
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3361109859
Short name T212
Test name
Test status
Simulation time 12675403 ps
CPU time 0.57 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:37 PM PDT 24
Peak memory 195548 kb
Host smart-5e8c1cbd-042f-4c97-a6b7-f9c974e17b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361109859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3361109859
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1387871430
Short name T618
Test name
Test status
Simulation time 40789925 ps
CPU time 0.85 seconds
Started Jul 04 05:01:38 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 195764 kb
Host smart-0735088c-ad9c-4bbc-a6ff-362a4fd4bd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387871430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1387871430
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1113486229
Short name T432
Test name
Test status
Simulation time 1694897438 ps
CPU time 12.85 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:51 PM PDT 24
Peak memory 197640 kb
Host smart-8204264b-6474-49f0-bbf0-d08e7ca3f816
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113486229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1113486229
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2623363103
Short name T416
Test name
Test status
Simulation time 23849158 ps
CPU time 0.68 seconds
Started Jul 04 05:01:38 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 195920 kb
Host smart-846e5247-350f-4f07-893a-58bba5ae69a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623363103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2623363103
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4060189703
Short name T495
Test name
Test status
Simulation time 45760680 ps
CPU time 1.24 seconds
Started Jul 04 05:01:38 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 197328 kb
Host smart-40058449-1f26-4385-ae7b-fc05628a1b65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060189703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4060189703
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3410524833
Short name T720
Test name
Test status
Simulation time 86284388 ps
CPU time 3.24 seconds
Started Jul 04 05:01:36 PM PDT 24
Finished Jul 04 05:01:40 PM PDT 24
Peak memory 198608 kb
Host smart-54d6de8f-0309-437f-9577-06ea2e95e8ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410524833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3410524833
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2200892253
Short name T28
Test name
Test status
Simulation time 143471965 ps
CPU time 2.79 seconds
Started Jul 04 05:01:38 PM PDT 24
Finished Jul 04 05:01:41 PM PDT 24
Peak memory 197576 kb
Host smart-b6dbce59-f586-4707-abc1-3290e80ca00b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200892253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2200892253
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1362933254
Short name T350
Test name
Test status
Simulation time 115173307 ps
CPU time 0.88 seconds
Started Jul 04 05:01:39 PM PDT 24
Finished Jul 04 05:01:40 PM PDT 24
Peak memory 197052 kb
Host smart-ae98720b-a11e-467b-9407-cc59131e4d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362933254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1362933254
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2872317960
Short name T174
Test name
Test status
Simulation time 16389311 ps
CPU time 0.68 seconds
Started Jul 04 05:01:36 PM PDT 24
Finished Jul 04 05:01:37 PM PDT 24
Peak memory 195276 kb
Host smart-409bf3f4-b81d-4b2a-9f2c-62735f287003
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872317960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2872317960
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.114787700
Short name T261
Test name
Test status
Simulation time 101225609 ps
CPU time 4.26 seconds
Started Jul 04 05:01:36 PM PDT 24
Finished Jul 04 05:01:40 PM PDT 24
Peak memory 198504 kb
Host smart-7d638e1c-2921-4553-84c0-a75ed54d3a2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114787700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.114787700
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3811094575
Short name T640
Test name
Test status
Simulation time 85115714 ps
CPU time 0.9 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:38 PM PDT 24
Peak memory 195912 kb
Host smart-06097586-cf15-4720-99e0-d44c0279a9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811094575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3811094575
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3080780759
Short name T383
Test name
Test status
Simulation time 41105357 ps
CPU time 1.18 seconds
Started Jul 04 05:01:39 PM PDT 24
Finished Jul 04 05:01:41 PM PDT 24
Peak memory 197000 kb
Host smart-4ddc3135-d19f-464c-83ca-7b2bdd0eed7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080780759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3080780759
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.724549104
Short name T649
Test name
Test status
Simulation time 12398139186 ps
CPU time 179.95 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:04:38 PM PDT 24
Peak memory 198612 kb
Host smart-4b693c52-23b7-44e2-ac40-07f4b2f29fb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724549104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.724549104
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.4185025289
Short name T345
Test name
Test status
Simulation time 94724018392 ps
CPU time 623.34 seconds
Started Jul 04 05:01:38 PM PDT 24
Finished Jul 04 05:12:02 PM PDT 24
Peak memory 198832 kb
Host smart-bc0e3d0a-9be2-4bb3-a297-2b093d6c2f4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4185025289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.4185025289
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2189801623
Short name T450
Test name
Test status
Simulation time 47301113 ps
CPU time 0.55 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:01:48 PM PDT 24
Peak memory 194544 kb
Host smart-a7eb1c55-1525-484e-8686-f047b741acff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189801623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2189801623
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3198409104
Short name T153
Test name
Test status
Simulation time 155767033 ps
CPU time 0.89 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 197740 kb
Host smart-8c8de595-8554-4a90-9565-84befe2cc936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198409104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3198409104
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1399700236
Short name T670
Test name
Test status
Simulation time 476804681 ps
CPU time 24.07 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:02:10 PM PDT 24
Peak memory 197424 kb
Host smart-03ed4179-01bc-4d2d-bbd5-833acd5bef68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399700236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1399700236
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.4017702588
Short name T21
Test name
Test status
Simulation time 75628716 ps
CPU time 1 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 198364 kb
Host smart-e41f121d-9e78-4f7b-9d77-3349c85f40ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017702588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.4017702588
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3923854490
Short name T271
Test name
Test status
Simulation time 119618468 ps
CPU time 1.08 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:48 PM PDT 24
Peak memory 196396 kb
Host smart-e4636d5f-8954-4505-9a3f-5b9b50a9b0c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923854490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3923854490
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4151882304
Short name T592
Test name
Test status
Simulation time 85899272 ps
CPU time 3.64 seconds
Started Jul 04 05:01:45 PM PDT 24
Finished Jul 04 05:01:49 PM PDT 24
Peak memory 198636 kb
Host smart-bb462a43-8cd0-449f-8b10-193d5b09ec2e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151882304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4151882304
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3645067026
Short name T434
Test name
Test status
Simulation time 158598046 ps
CPU time 1.02 seconds
Started Jul 04 05:01:45 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 196188 kb
Host smart-54b80895-58a5-41c5-8d4e-647ff0da935e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645067026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3645067026
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1274756100
Short name T688
Test name
Test status
Simulation time 157706986 ps
CPU time 1.13 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 196596 kb
Host smart-af3315d5-b5dc-4b8c-9738-90495a3cf611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274756100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1274756100
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1864520978
Short name T80
Test name
Test status
Simulation time 98229870 ps
CPU time 1.17 seconds
Started Jul 04 05:01:41 PM PDT 24
Finished Jul 04 05:01:42 PM PDT 24
Peak memory 196584 kb
Host smart-f16b6f4a-46c8-450b-999e-69e1aa1c344e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864520978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1864520978
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1889696843
Short name T324
Test name
Test status
Simulation time 144081256 ps
CPU time 3.39 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:01:51 PM PDT 24
Peak memory 198544 kb
Host smart-9ae812bb-3e4d-4a3a-a19e-c77fd17a0a01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889696843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1889696843
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1077416747
Short name T353
Test name
Test status
Simulation time 241620885 ps
CPU time 1.06 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 196232 kb
Host smart-74fae601-02e7-48dd-b0fa-59f4057803ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077416747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1077416747
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3594557581
Short name T540
Test name
Test status
Simulation time 44730028 ps
CPU time 0.96 seconds
Started Jul 04 05:01:38 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 196996 kb
Host smart-f872ac27-ee0b-4d7a-8530-955f4b571d07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594557581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3594557581
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1861357459
Short name T338
Test name
Test status
Simulation time 69419220042 ps
CPU time 181.64 seconds
Started Jul 04 05:01:45 PM PDT 24
Finished Jul 04 05:04:47 PM PDT 24
Peak memory 198632 kb
Host smart-fc13de70-b44c-479a-9c63-37fb0da7cbc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861357459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1861357459
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.4181741935
Short name T505
Test name
Test status
Simulation time 42156734 ps
CPU time 0.6 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 194528 kb
Host smart-f070f4fd-b4c7-4d34-9b64-5cfa0a70a5aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181741935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.4181741935
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.890408384
Short name T602
Test name
Test status
Simulation time 19306014 ps
CPU time 0.78 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 195924 kb
Host smart-fca26d46-71d4-4ac9-a05b-5269350a1d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890408384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.890408384
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2686955832
Short name T421
Test name
Test status
Simulation time 1571139745 ps
CPU time 11.31 seconds
Started Jul 04 05:01:45 PM PDT 24
Finished Jul 04 05:01:57 PM PDT 24
Peak memory 197560 kb
Host smart-007fcf10-f59c-4020-a1b6-c9db84af3a28
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686955832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2686955832
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2881313136
Short name T146
Test name
Test status
Simulation time 21665782 ps
CPU time 0.62 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:01:48 PM PDT 24
Peak memory 194984 kb
Host smart-e4cc525b-f139-43d0-ac6b-14d34084a5c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881313136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2881313136
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.36859354
Short name T538
Test name
Test status
Simulation time 158496824 ps
CPU time 1.21 seconds
Started Jul 04 05:01:45 PM PDT 24
Finished Jul 04 05:01:46 PM PDT 24
Peak memory 196608 kb
Host smart-e9273204-41de-4184-9a6f-da6d93c7f420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.36859354
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2151675954
Short name T250
Test name
Test status
Simulation time 23282086 ps
CPU time 1.08 seconds
Started Jul 04 05:01:48 PM PDT 24
Finished Jul 04 05:01:49 PM PDT 24
Peak memory 196712 kb
Host smart-e4ddd5a8-59fc-4dd1-bcc4-1df53872d98c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151675954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2151675954
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2151507218
Short name T320
Test name
Test status
Simulation time 30394043 ps
CPU time 0.91 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:01:49 PM PDT 24
Peak memory 194880 kb
Host smart-b514ea2c-f218-4a94-8343-55e37035d551
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151507218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2151507218
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.59958927
Short name T436
Test name
Test status
Simulation time 137387847 ps
CPU time 0.99 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:01:48 PM PDT 24
Peak memory 197372 kb
Host smart-dec41404-1128-44a9-a23d-4ac4b4af82e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59958927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.59958927
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3727385055
Short name T696
Test name
Test status
Simulation time 121121766 ps
CPU time 1.2 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:48 PM PDT 24
Peak memory 197852 kb
Host smart-c003c206-8226-4188-8cd1-2d6673611a53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727385055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3727385055
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1838823580
Short name T342
Test name
Test status
Simulation time 1364287597 ps
CPU time 6.09 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:01:54 PM PDT 24
Peak memory 198516 kb
Host smart-b719e9a5-54e3-4c45-a109-e7065dbd8fc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838823580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1838823580
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1121003099
Short name T658
Test name
Test status
Simulation time 111488005 ps
CPU time 1.08 seconds
Started Jul 04 05:01:44 PM PDT 24
Finished Jul 04 05:01:46 PM PDT 24
Peak memory 196244 kb
Host smart-7abdee9d-55d0-434f-ac78-ce73db84180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121003099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1121003099
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.696753551
Short name T681
Test name
Test status
Simulation time 403241177 ps
CPU time 0.94 seconds
Started Jul 04 05:01:50 PM PDT 24
Finished Jul 04 05:01:51 PM PDT 24
Peak memory 196004 kb
Host smart-6bc60a7a-0897-4c39-9af3-cc110864471b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696753551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.696753551
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3143739000
Short name T281
Test name
Test status
Simulation time 41351653 ps
CPU time 0.59 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:01:48 PM PDT 24
Peak memory 194844 kb
Host smart-02cd44c7-1d77-43cf-b12c-01b6217ee8d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143739000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3143739000
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.474818388
Short name T78
Test name
Test status
Simulation time 25814389 ps
CPU time 0.72 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 194608 kb
Host smart-b374efc8-6148-4123-a3bb-1ba4d34efb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474818388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.474818388
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3772224593
Short name T541
Test name
Test status
Simulation time 626044765 ps
CPU time 23.51 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:02:11 PM PDT 24
Peak memory 196132 kb
Host smart-2a5cc02c-4f12-4978-a309-829a5592048f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772224593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3772224593
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2203740477
Short name T408
Test name
Test status
Simulation time 75897376 ps
CPU time 0.97 seconds
Started Jul 04 05:01:49 PM PDT 24
Finished Jul 04 05:01:51 PM PDT 24
Peak memory 197876 kb
Host smart-a7e565f0-9ed1-4568-a9a1-e79dcbe3b6cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203740477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2203740477
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1774112557
Short name T147
Test name
Test status
Simulation time 59617848 ps
CPU time 1.06 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:48 PM PDT 24
Peak memory 196492 kb
Host smart-3791e387-999c-445c-893e-126ea8e697bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774112557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1774112557
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.893710155
Short name T280
Test name
Test status
Simulation time 37658015 ps
CPU time 1.68 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:48 PM PDT 24
Peak memory 198584 kb
Host smart-ada3ae93-6659-4ad1-ab88-babbb9fd6108
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893710155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.893710155
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2151174341
Short name T357
Test name
Test status
Simulation time 92392515 ps
CPU time 2.81 seconds
Started Jul 04 05:01:48 PM PDT 24
Finished Jul 04 05:01:51 PM PDT 24
Peak memory 197972 kb
Host smart-b965aeee-fba2-4e69-a58d-f2c29917313a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151174341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2151174341
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.583977238
Short name T623
Test name
Test status
Simulation time 156076866 ps
CPU time 1.13 seconds
Started Jul 04 05:01:43 PM PDT 24
Finished Jul 04 05:01:45 PM PDT 24
Peak memory 197296 kb
Host smart-3024da42-b362-4186-a32f-4b902d0a591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583977238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.583977238
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3752389976
Short name T607
Test name
Test status
Simulation time 91571128 ps
CPU time 0.77 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 196100 kb
Host smart-10188aba-e1b5-4d2e-adaf-ae234f46b894
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752389976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3752389976
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1303153285
Short name T3
Test name
Test status
Simulation time 2519063832 ps
CPU time 3.99 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:01:52 PM PDT 24
Peak memory 198600 kb
Host smart-cf5fa18c-5649-481a-bfbc-afa4986eedda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303153285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1303153285
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1199782754
Short name T262
Test name
Test status
Simulation time 107369801 ps
CPU time 1 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:48 PM PDT 24
Peak memory 195988 kb
Host smart-d90ebe88-1f6d-455a-9659-160c923001b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199782754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1199782754
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2625592712
Short name T123
Test name
Test status
Simulation time 40301403 ps
CPU time 0.9 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 196792 kb
Host smart-3f166950-1046-47dd-aeb6-ebb6197039e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625592712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2625592712
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2154248812
Short name T59
Test name
Test status
Simulation time 4484539179 ps
CPU time 46.08 seconds
Started Jul 04 05:01:49 PM PDT 24
Finished Jul 04 05:02:36 PM PDT 24
Peak memory 198520 kb
Host smart-5316c2b8-4ee9-45dd-9901-2df5449d4cb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154248812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2154248812
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1837380197
Short name T69
Test name
Test status
Simulation time 501699282825 ps
CPU time 1516.28 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:27:03 PM PDT 24
Peak memory 198940 kb
Host smart-00d0668c-d567-4c01-a5f7-fe75a3bea55c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1837380197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1837380197
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3379903973
Short name T707
Test name
Test status
Simulation time 14333177 ps
CPU time 0.6 seconds
Started Jul 04 05:01:58 PM PDT 24
Finished Jul 04 05:01:59 PM PDT 24
Peak memory 194060 kb
Host smart-799a923e-03ef-4209-bd84-a08a3e6ac11f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379903973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3379903973
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2080441475
Short name T325
Test name
Test status
Simulation time 31601659 ps
CPU time 0.65 seconds
Started Jul 04 05:01:49 PM PDT 24
Finished Jul 04 05:01:50 PM PDT 24
Peak memory 194380 kb
Host smart-7829bf1e-083b-47cc-9391-d6a4a5070811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080441475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2080441475
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3407145033
Short name T120
Test name
Test status
Simulation time 4956626656 ps
CPU time 16.08 seconds
Started Jul 04 05:01:45 PM PDT 24
Finished Jul 04 05:02:02 PM PDT 24
Peak memory 198612 kb
Host smart-1d6ee071-059e-41d1-bcae-9fd819678b00
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407145033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3407145033
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1272255745
Short name T516
Test name
Test status
Simulation time 51661079 ps
CPU time 0.84 seconds
Started Jul 04 05:01:51 PM PDT 24
Finished Jul 04 05:01:52 PM PDT 24
Peak memory 196484 kb
Host smart-81bb3a63-a0cd-41b7-9274-add3df5e4649
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272255745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1272255745
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.638677073
Short name T679
Test name
Test status
Simulation time 50985787 ps
CPU time 0.88 seconds
Started Jul 04 05:01:51 PM PDT 24
Finished Jul 04 05:01:52 PM PDT 24
Peak memory 197744 kb
Host smart-8e8fb90c-1ae9-48da-9872-d29952b8f3bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638677073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.638677073
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.229077700
Short name T550
Test name
Test status
Simulation time 139423420 ps
CPU time 1.54 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 197340 kb
Host smart-00640164-76bd-4822-a7f4-08cc508e28bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229077700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.229077700
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2246183911
Short name T219
Test name
Test status
Simulation time 151518646 ps
CPU time 2.91 seconds
Started Jul 04 05:01:44 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 197868 kb
Host smart-a643b17f-525a-4012-b7b1-c9aeafdfb248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246183911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2246183911
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2701899382
Short name T685
Test name
Test status
Simulation time 83988355 ps
CPU time 0.79 seconds
Started Jul 04 05:01:49 PM PDT 24
Finished Jul 04 05:01:50 PM PDT 24
Peak memory 196700 kb
Host smart-6d76b124-1258-4c53-8ee1-3b41d09bb23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701899382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2701899382
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.24982773
Short name T311
Test name
Test status
Simulation time 26126354 ps
CPU time 1.04 seconds
Started Jul 04 05:01:47 PM PDT 24
Finished Jul 04 05:01:49 PM PDT 24
Peak memory 196612 kb
Host smart-a3679735-e502-4093-b288-0dd4671003c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24982773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup_
pulldown.24982773
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3133848097
Short name T12
Test name
Test status
Simulation time 1082841157 ps
CPU time 5.09 seconds
Started Jul 04 05:01:57 PM PDT 24
Finished Jul 04 05:02:02 PM PDT 24
Peak memory 198268 kb
Host smart-5ab57198-1f14-4afa-8e95-02b239ba2fc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133848097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3133848097
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1642948257
Short name T318
Test name
Test status
Simulation time 35116241 ps
CPU time 0.81 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 195556 kb
Host smart-67a479c0-2c4f-4000-bd3e-c8d7304a8561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642948257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1642948257
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3326572895
Short name T166
Test name
Test status
Simulation time 183311081 ps
CPU time 0.89 seconds
Started Jul 04 05:01:46 PM PDT 24
Finished Jul 04 05:01:47 PM PDT 24
Peak memory 196240 kb
Host smart-95bfa6a6-3157-4236-ae0a-6be1ff194726
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326572895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3326572895
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.317505214
Short name T522
Test name
Test status
Simulation time 27361278596 ps
CPU time 94.05 seconds
Started Jul 04 05:01:55 PM PDT 24
Finished Jul 04 05:03:29 PM PDT 24
Peak memory 198784 kb
Host smart-4da27172-da62-4447-a066-c487f5c97f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317505214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.317505214
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3066079579
Short name T170
Test name
Test status
Simulation time 21125076 ps
CPU time 0.57 seconds
Started Jul 04 05:01:55 PM PDT 24
Finished Jul 04 05:01:56 PM PDT 24
Peak memory 194536 kb
Host smart-2a47644a-efad-43a2-9dc4-b93ccd4810a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066079579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3066079579
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2602529807
Short name T539
Test name
Test status
Simulation time 41276199 ps
CPU time 0.84 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:01:55 PM PDT 24
Peak memory 196008 kb
Host smart-ea50f02c-7de1-4d2a-9f6e-aff913caf6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602529807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2602529807
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3789962189
Short name T151
Test name
Test status
Simulation time 457988971 ps
CPU time 13.53 seconds
Started Jul 04 05:01:55 PM PDT 24
Finished Jul 04 05:02:08 PM PDT 24
Peak memory 198676 kb
Host smart-82832a22-5a2c-403b-820f-9e67b7dd2902
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789962189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3789962189
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1324147994
Short name T616
Test name
Test status
Simulation time 93034063 ps
CPU time 0.75 seconds
Started Jul 04 05:01:54 PM PDT 24
Finished Jul 04 05:01:55 PM PDT 24
Peak memory 195400 kb
Host smart-0d93cd79-e2cd-4a5b-b6d9-604742e21b20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324147994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1324147994
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.115015737
Short name T317
Test name
Test status
Simulation time 63317412 ps
CPU time 0.73 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:01:54 PM PDT 24
Peak memory 196616 kb
Host smart-17f376f6-aecd-4b5e-9e9d-0b611fff8eb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115015737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.115015737
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.146347875
Short name T627
Test name
Test status
Simulation time 167201737 ps
CPU time 3.69 seconds
Started Jul 04 05:01:54 PM PDT 24
Finished Jul 04 05:01:58 PM PDT 24
Peak memory 198340 kb
Host smart-6107a014-a698-4e84-8261-6b3474241b2c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146347875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.146347875
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2160284733
Short name T339
Test name
Test status
Simulation time 209188270 ps
CPU time 3.07 seconds
Started Jul 04 05:01:57 PM PDT 24
Finished Jul 04 05:02:00 PM PDT 24
Peak memory 197712 kb
Host smart-9caaa412-a9de-468c-b677-3dd8d2f73b03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160284733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2160284733
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2476348329
Short name T30
Test name
Test status
Simulation time 20468623 ps
CPU time 0.7 seconds
Started Jul 04 05:01:54 PM PDT 24
Finished Jul 04 05:01:55 PM PDT 24
Peak memory 194756 kb
Host smart-59c7c7df-631d-4910-a63d-0fac922d6efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476348329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2476348329
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1595934019
Short name T599
Test name
Test status
Simulation time 111511706 ps
CPU time 1.23 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:01:54 PM PDT 24
Peak memory 197504 kb
Host smart-69b8237d-34c7-4b99-af2b-0a527971c504
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595934019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1595934019
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.294198871
Short name T148
Test name
Test status
Simulation time 81635994 ps
CPU time 1.65 seconds
Started Jul 04 05:01:52 PM PDT 24
Finished Jul 04 05:01:55 PM PDT 24
Peak memory 198496 kb
Host smart-f66a2953-ba55-4ed6-99b4-e3352e7dbf8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294198871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.294198871
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1913009471
Short name T520
Test name
Test status
Simulation time 222227771 ps
CPU time 1.02 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:01:54 PM PDT 24
Peak memory 196328 kb
Host smart-707d19ee-89d2-4471-8e7c-7eafc8fdca36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913009471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1913009471
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.935289985
Short name T144
Test name
Test status
Simulation time 77368566 ps
CPU time 0.98 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:01:54 PM PDT 24
Peak memory 197084 kb
Host smart-94ce6ba3-6136-4609-8074-d69e59db2b86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935289985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.935289985
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3118024793
Short name T269
Test name
Test status
Simulation time 17882312716 ps
CPU time 111.48 seconds
Started Jul 04 05:01:56 PM PDT 24
Finished Jul 04 05:03:48 PM PDT 24
Peak memory 198720 kb
Host smart-c81db4e8-e1c8-4d82-b168-406a4557f63d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118024793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3118024793
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2218097260
Short name T356
Test name
Test status
Simulation time 39610809 ps
CPU time 0.56 seconds
Started Jul 04 05:01:56 PM PDT 24
Finished Jul 04 05:01:56 PM PDT 24
Peak memory 195228 kb
Host smart-0700bcf9-e0e7-4bdd-a695-7d0b524741a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218097260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2218097260
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3411752931
Short name T294
Test name
Test status
Simulation time 211000313 ps
CPU time 0.97 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:01:55 PM PDT 24
Peak memory 196468 kb
Host smart-978fd33e-6042-447f-9564-99b5f3ba299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411752931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3411752931
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2134575344
Short name T17
Test name
Test status
Simulation time 264533145 ps
CPU time 9.4 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:02:03 PM PDT 24
Peak memory 196052 kb
Host smart-30c95d79-eed1-4e5c-89c5-b95dcce1dad9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134575344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2134575344
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1421125032
Short name T230
Test name
Test status
Simulation time 43587032 ps
CPU time 0.8 seconds
Started Jul 04 05:01:54 PM PDT 24
Finished Jul 04 05:01:55 PM PDT 24
Peak memory 196416 kb
Host smart-48232e52-6b15-4901-ab0c-2b7552b3ea0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421125032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1421125032
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.187138952
Short name T716
Test name
Test status
Simulation time 224439873 ps
CPU time 0.92 seconds
Started Jul 04 05:01:51 PM PDT 24
Finished Jul 04 05:01:53 PM PDT 24
Peak memory 198000 kb
Host smart-6ec9a45e-2cdc-4d50-a3c0-a884ad99a97d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187138952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.187138952
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4130751981
Short name T268
Test name
Test status
Simulation time 65718263 ps
CPU time 2.69 seconds
Started Jul 04 05:01:55 PM PDT 24
Finished Jul 04 05:01:57 PM PDT 24
Peak memory 198660 kb
Host smart-3a19d92d-de6e-4d99-a378-8f7df3ccbc9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130751981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4130751981
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.4200150394
Short name T569
Test name
Test status
Simulation time 78532063 ps
CPU time 1.37 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:01:54 PM PDT 24
Peak memory 196388 kb
Host smart-32e322be-e187-4b29-a5f4-cf29335bbb96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200150394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.4200150394
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2048262754
Short name T11
Test name
Test status
Simulation time 32186221 ps
CPU time 1.19 seconds
Started Jul 04 05:01:55 PM PDT 24
Finished Jul 04 05:01:57 PM PDT 24
Peak memory 197520 kb
Host smart-cbf8e436-b81b-4f7a-96df-be3f116ed262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048262754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2048262754
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2784700561
Short name T232
Test name
Test status
Simulation time 195422312 ps
CPU time 1.3 seconds
Started Jul 04 05:01:54 PM PDT 24
Finished Jul 04 05:01:56 PM PDT 24
Peak memory 197456 kb
Host smart-d836c52d-cee8-462f-884b-7a996c19ce4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784700561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2784700561
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.492133025
Short name T370
Test name
Test status
Simulation time 701560087 ps
CPU time 3.52 seconds
Started Jul 04 05:01:54 PM PDT 24
Finished Jul 04 05:01:58 PM PDT 24
Peak memory 198484 kb
Host smart-30f7a647-393d-4ac7-8502-995a3c3d1d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492133025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.492133025
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1241188814
Short name T354
Test name
Test status
Simulation time 33059819 ps
CPU time 0.9 seconds
Started Jul 04 05:01:52 PM PDT 24
Finished Jul 04 05:01:53 PM PDT 24
Peak memory 195956 kb
Host smart-fb1c7446-e0d1-4b91-9a2d-d9b55b28c4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241188814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1241188814
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1514055889
Short name T704
Test name
Test status
Simulation time 51361179 ps
CPU time 1.07 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:01:54 PM PDT 24
Peak memory 197000 kb
Host smart-f14ac073-77f2-4445-ab3f-4c831385b2c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514055889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1514055889
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_alert_test.878643616
Short name T470
Test name
Test status
Simulation time 60983570 ps
CPU time 0.59 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:04 PM PDT 24
Peak memory 194844 kb
Host smart-cf087fe5-9beb-4a5e-87dc-3ab7e36febf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878643616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.878643616
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3800772832
Short name T32
Test name
Test status
Simulation time 79239954 ps
CPU time 0.7 seconds
Started Jul 04 05:02:01 PM PDT 24
Finished Jul 04 05:02:02 PM PDT 24
Peak memory 195596 kb
Host smart-07ba8939-34d0-482d-8604-bbb5999e5205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800772832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3800772832
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3801882452
Short name T614
Test name
Test status
Simulation time 1170350240 ps
CPU time 10.53 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:02:12 PM PDT 24
Peak memory 197540 kb
Host smart-21bdfa2a-e98f-4f58-b484-184387ae41f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801882452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3801882452
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2072904840
Short name T562
Test name
Test status
Simulation time 19953126 ps
CPU time 0.65 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:02:03 PM PDT 24
Peak memory 194876 kb
Host smart-def567f7-76da-4a6a-9211-9d6c3d606ef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072904840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2072904840
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.560854108
Short name T296
Test name
Test status
Simulation time 192691040 ps
CPU time 0.91 seconds
Started Jul 04 05:02:05 PM PDT 24
Finished Jul 04 05:02:07 PM PDT 24
Peak memory 196340 kb
Host smart-53c2d387-2ebc-44b9-8a17-747d871be3e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560854108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.560854108
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.4261488471
Short name T560
Test name
Test status
Simulation time 274904350 ps
CPU time 2.94 seconds
Started Jul 04 05:02:01 PM PDT 24
Finished Jul 04 05:02:04 PM PDT 24
Peak memory 198592 kb
Host smart-3c007015-2791-4d93-b00e-422f9105bfc7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261488471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.4261488471
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.4104579847
Short name T191
Test name
Test status
Simulation time 180242522 ps
CPU time 3.11 seconds
Started Jul 04 05:02:05 PM PDT 24
Finished Jul 04 05:02:08 PM PDT 24
Peak memory 196472 kb
Host smart-a390712c-0fde-463b-947c-6bf7cadd9d46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104579847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.4104579847
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.233664825
Short name T462
Test name
Test status
Simulation time 369856221 ps
CPU time 1 seconds
Started Jul 04 05:02:04 PM PDT 24
Finished Jul 04 05:02:06 PM PDT 24
Peak memory 196616 kb
Host smart-e85044d1-adfc-4cf7-9100-2ae8b28b8611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233664825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.233664825
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1037577430
Short name T260
Test name
Test status
Simulation time 55793552 ps
CPU time 1.07 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:05 PM PDT 24
Peak memory 196684 kb
Host smart-96e1372c-f5a3-4ba6-ac63-d15b444e55aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037577430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1037577430
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.605096539
Short name T572
Test name
Test status
Simulation time 1383893194 ps
CPU time 5.66 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:10 PM PDT 24
Peak memory 198616 kb
Host smart-d88c0093-37b2-43bd-a4d1-ca4506f42870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605096539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.605096539
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3591332156
Short name T676
Test name
Test status
Simulation time 223229491 ps
CPU time 1.07 seconds
Started Jul 04 05:01:53 PM PDT 24
Finished Jul 04 05:01:55 PM PDT 24
Peak memory 196780 kb
Host smart-8ac59c9d-fac4-4e4c-b2c2-56386c2ca729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591332156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3591332156
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2623210002
Short name T203
Test name
Test status
Simulation time 58720944 ps
CPU time 1.61 seconds
Started Jul 04 05:01:58 PM PDT 24
Finished Jul 04 05:02:00 PM PDT 24
Peak memory 197388 kb
Host smart-0cb49272-b7f8-419e-9d41-62b0198feb96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623210002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2623210002
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.817436288
Short name T9
Test name
Test status
Simulation time 87378266681 ps
CPU time 194.64 seconds
Started Jul 04 05:02:05 PM PDT 24
Finished Jul 04 05:05:20 PM PDT 24
Peak memory 198676 kb
Host smart-ea1c6a67-ba44-4b07-bbdd-000c0e8072ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817436288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.817436288
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.299946141
Short name T424
Test name
Test status
Simulation time 114100727849 ps
CPU time 1525.57 seconds
Started Jul 04 05:02:01 PM PDT 24
Finished Jul 04 05:27:27 PM PDT 24
Peak memory 198864 kb
Host smart-5039ec7a-951a-4279-91b7-ac02a97276b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=299946141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.299946141
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3543047159
Short name T718
Test name
Test status
Simulation time 12029114 ps
CPU time 0.58 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:02:03 PM PDT 24
Peak memory 193340 kb
Host smart-84589d08-8a7a-4494-a695-303cd2c380f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543047159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3543047159
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3411037500
Short name T188
Test name
Test status
Simulation time 51397644 ps
CPU time 0.9 seconds
Started Jul 04 05:02:05 PM PDT 24
Finished Jul 04 05:02:06 PM PDT 24
Peak memory 196372 kb
Host smart-02839fe0-3864-4f34-a110-c233455f281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411037500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3411037500
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.4212803989
Short name T133
Test name
Test status
Simulation time 1589434647 ps
CPU time 20.55 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:24 PM PDT 24
Peak memory 197508 kb
Host smart-a0c1fde6-e3c0-4221-97d7-fb249f1fdeef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212803989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4212803989
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.937912382
Short name T375
Test name
Test status
Simulation time 248943334 ps
CPU time 1.05 seconds
Started Jul 04 05:02:05 PM PDT 24
Finished Jul 04 05:02:06 PM PDT 24
Peak memory 198492 kb
Host smart-6c2ffc27-1114-4f6f-91a4-2d98d3191a5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937912382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.937912382
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3554990456
Short name T644
Test name
Test status
Simulation time 302445910 ps
CPU time 1.37 seconds
Started Jul 04 05:02:01 PM PDT 24
Finished Jul 04 05:02:03 PM PDT 24
Peak memory 197092 kb
Host smart-21219cde-28aa-42a9-8a86-0919917cbfb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554990456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3554990456
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.875567449
Short name T556
Test name
Test status
Simulation time 41374120 ps
CPU time 1.81 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:02:04 PM PDT 24
Peak memory 197508 kb
Host smart-80a74afc-b640-49ed-9994-1eabcf566407
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875567449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.875567449
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2216920903
Short name T162
Test name
Test status
Simulation time 821149512 ps
CPU time 3.53 seconds
Started Jul 04 05:02:01 PM PDT 24
Finished Jul 04 05:02:04 PM PDT 24
Peak memory 197468 kb
Host smart-5b7e4d10-6ba9-45fc-ba40-bcc2b4bfab17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216920903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2216920903
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2872202325
Short name T453
Test name
Test status
Simulation time 33422467 ps
CPU time 1.12 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:04 PM PDT 24
Peak memory 196388 kb
Host smart-a8d0c49b-d2f3-4d87-8775-d7c869592143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872202325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2872202325
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1824095196
Short name T687
Test name
Test status
Simulation time 20220815 ps
CPU time 0.81 seconds
Started Jul 04 05:02:01 PM PDT 24
Finished Jul 04 05:02:02 PM PDT 24
Peak memory 195928 kb
Host smart-cf0d85d7-a057-44e6-8c0e-f4936667d163
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824095196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1824095196
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1631758015
Short name T286
Test name
Test status
Simulation time 145675441 ps
CPU time 1.71 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:05 PM PDT 24
Peak memory 198588 kb
Host smart-39f4bc2a-7565-4d71-a5fa-5b0288a75486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631758015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1631758015
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2504500199
Short name T693
Test name
Test status
Simulation time 70554020 ps
CPU time 1.33 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:02:03 PM PDT 24
Peak memory 196440 kb
Host smart-9a53773a-82c0-43e6-aab7-b44f75e6435a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504500199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2504500199
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2685341662
Short name T482
Test name
Test status
Simulation time 157603940 ps
CPU time 0.9 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:04 PM PDT 24
Peak memory 196036 kb
Host smart-3fe99e4b-c63f-4ef6-a931-e6f5d43c1d4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685341662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2685341662
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3683313237
Short name T467
Test name
Test status
Simulation time 81421999933 ps
CPU time 243.46 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:06:06 PM PDT 24
Peak memory 198656 kb
Host smart-615eeb9e-cebe-4bf4-8221-1829cf2789e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683313237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3683313237
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3424948126
Short name T362
Test name
Test status
Simulation time 159540642149 ps
CPU time 575.4 seconds
Started Jul 04 05:02:04 PM PDT 24
Finished Jul 04 05:11:40 PM PDT 24
Peak memory 198804 kb
Host smart-ac87751e-8d2d-4b48-8d97-c91e1b0bcfcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3424948126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3424948126
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2283763138
Short name T475
Test name
Test status
Simulation time 24451373 ps
CPU time 0.62 seconds
Started Jul 04 05:02:14 PM PDT 24
Finished Jul 04 05:02:15 PM PDT 24
Peak memory 194652 kb
Host smart-33ae5771-5ec7-4b97-ad44-3da50a3a4f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283763138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2283763138
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2636036205
Short name T266
Test name
Test status
Simulation time 18351656 ps
CPU time 0.66 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:02:03 PM PDT 24
Peak memory 194592 kb
Host smart-495b1cf5-f4f3-456a-bc2b-d5dc226c18bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636036205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2636036205
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4011091368
Short name T635
Test name
Test status
Simulation time 1652786884 ps
CPU time 16.38 seconds
Started Jul 04 05:02:06 PM PDT 24
Finished Jul 04 05:02:23 PM PDT 24
Peak memory 197380 kb
Host smart-7ea5d2d7-5fd1-4337-b4b0-ec1ccfc25fa6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011091368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4011091368
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.4288101824
Short name T542
Test name
Test status
Simulation time 105148890 ps
CPU time 0.66 seconds
Started Jul 04 05:02:05 PM PDT 24
Finished Jul 04 05:02:05 PM PDT 24
Peak memory 195152 kb
Host smart-3d773f0f-61ac-47e1-a208-3976bcbc8576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288101824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.4288101824
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2780035099
Short name T246
Test name
Test status
Simulation time 106953437 ps
CPU time 1.46 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:05 PM PDT 24
Peak memory 197720 kb
Host smart-7b2adad1-c4c1-4713-b186-9e676c31a1a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780035099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2780035099
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2663444238
Short name T708
Test name
Test status
Simulation time 147250706 ps
CPU time 1.64 seconds
Started Jul 04 05:02:01 PM PDT 24
Finished Jul 04 05:02:03 PM PDT 24
Peak memory 198620 kb
Host smart-cd598229-6b59-407c-8db4-05c9479bfd66
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663444238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2663444238
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1699925820
Short name T287
Test name
Test status
Simulation time 613610765 ps
CPU time 3 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:02:05 PM PDT 24
Peak memory 198580 kb
Host smart-ca939722-e289-440e-a6f3-6bea7370cc85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699925820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1699925820
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.203468826
Short name T145
Test name
Test status
Simulation time 69736593 ps
CPU time 0.88 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:02:04 PM PDT 24
Peak memory 197012 kb
Host smart-6d1a3682-1c18-4328-8a32-03f2cb0c947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203468826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.203468826
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3856975079
Short name T336
Test name
Test status
Simulation time 133478874 ps
CPU time 0.9 seconds
Started Jul 04 05:02:00 PM PDT 24
Finished Jul 04 05:02:02 PM PDT 24
Peak memory 197108 kb
Host smart-c1d0e1a2-860a-41c6-a77d-15cd46d2583d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856975079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3856975079
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3371597642
Short name T709
Test name
Test status
Simulation time 87540738 ps
CPU time 2.21 seconds
Started Jul 04 05:02:01 PM PDT 24
Finished Jul 04 05:02:04 PM PDT 24
Peak memory 198520 kb
Host smart-048bf81e-7c66-4441-9349-29f71b98272f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371597642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3371597642
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1860403450
Short name T503
Test name
Test status
Simulation time 524124868 ps
CPU time 1.21 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:05 PM PDT 24
Peak memory 198576 kb
Host smart-8a2b87a2-103e-4b5b-b944-8c6f50374680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860403450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1860403450
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3253232450
Short name T312
Test name
Test status
Simulation time 324277092 ps
CPU time 1.28 seconds
Started Jul 04 05:02:03 PM PDT 24
Finished Jul 04 05:02:05 PM PDT 24
Peak memory 196108 kb
Host smart-70bae238-1727-4b38-829c-7967033a8de2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253232450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3253232450
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.43326711
Short name T288
Test name
Test status
Simulation time 181596267131 ps
CPU time 217.4 seconds
Started Jul 04 05:02:02 PM PDT 24
Finished Jul 04 05:05:40 PM PDT 24
Peak memory 198776 kb
Host smart-5b6df0ce-40b6-4ecd-a521-4c9fbdeb9c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43326711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gp
io_stress_all.43326711
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2021210990
Short name T72
Test name
Test status
Simulation time 99048713333 ps
CPU time 1159.06 seconds
Started Jul 04 05:02:14 PM PDT 24
Finished Jul 04 05:21:33 PM PDT 24
Peak memory 198876 kb
Host smart-a20a2251-1791-4e95-be75-fec4d4f5d7df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2021210990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2021210990
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2716708328
Short name T663
Test name
Test status
Simulation time 14750041 ps
CPU time 0.62 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:17 PM PDT 24
Peak memory 194532 kb
Host smart-d78b9a2b-f95c-439c-bb5c-0f6575311833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716708328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2716708328
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.201283227
Short name T678
Test name
Test status
Simulation time 148224706 ps
CPU time 0.92 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:17 PM PDT 24
Peak memory 197084 kb
Host smart-876c7d95-d692-4e21-905d-bc66ab92901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201283227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.201283227
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.417952651
Short name T81
Test name
Test status
Simulation time 886053421 ps
CPU time 13.23 seconds
Started Jul 04 05:01:14 PM PDT 24
Finished Jul 04 05:01:27 PM PDT 24
Peak memory 196080 kb
Host smart-1f656984-15d2-4580-b58f-db716bc9e070
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417952651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.417952651
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.64840512
Short name T493
Test name
Test status
Simulation time 25791595 ps
CPU time 0.62 seconds
Started Jul 04 05:01:15 PM PDT 24
Finished Jul 04 05:01:16 PM PDT 24
Peak memory 194704 kb
Host smart-4f2064fd-0101-4345-acd5-2b47e251d66a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64840512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.64840512
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1384040685
Short name T652
Test name
Test status
Simulation time 156719354 ps
CPU time 0.99 seconds
Started Jul 04 05:01:15 PM PDT 24
Finished Jul 04 05:01:16 PM PDT 24
Peak memory 196572 kb
Host smart-401923ed-374d-46af-83f2-29599a4785a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384040685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1384040685
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3661283468
Short name T118
Test name
Test status
Simulation time 100931660 ps
CPU time 3.12 seconds
Started Jul 04 05:01:18 PM PDT 24
Finished Jul 04 05:01:22 PM PDT 24
Peak memory 198576 kb
Host smart-f913906b-4093-4cb4-8946-e2a7e3e39243
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661283468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3661283468
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.4049476012
Short name T164
Test name
Test status
Simulation time 91005236 ps
CPU time 1.83 seconds
Started Jul 04 05:01:18 PM PDT 24
Finished Jul 04 05:01:20 PM PDT 24
Peak memory 196448 kb
Host smart-d0c65c7a-3bc6-42d7-a140-a64764f84e40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049476012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
4049476012
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3306092114
Short name T84
Test name
Test status
Simulation time 58339305 ps
CPU time 1.17 seconds
Started Jul 04 05:01:17 PM PDT 24
Finished Jul 04 05:01:18 PM PDT 24
Peak memory 197628 kb
Host smart-352235ce-a94a-4283-8887-f7f296a08130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306092114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3306092114
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3605003810
Short name T302
Test name
Test status
Simulation time 31922946 ps
CPU time 0.7 seconds
Started Jul 04 05:01:17 PM PDT 24
Finished Jul 04 05:01:18 PM PDT 24
Peak memory 194820 kb
Host smart-74749a77-bf5b-4836-a9e1-dd733d331244
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605003810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3605003810
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3999697767
Short name T637
Test name
Test status
Simulation time 142491915 ps
CPU time 1.98 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:18 PM PDT 24
Peak memory 198524 kb
Host smart-ca61085c-cdb4-4040-93c9-98c87f8a31dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999697767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3999697767
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1174477228
Short name T42
Test name
Test status
Simulation time 228594740 ps
CPU time 0.88 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:17 PM PDT 24
Peak memory 214152 kb
Host smart-67d10efc-5874-4b4a-a893-0a82b590093a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174477228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1174477228
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1332007886
Short name T381
Test name
Test status
Simulation time 1209155012 ps
CPU time 1.47 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:17 PM PDT 24
Peak memory 197396 kb
Host smart-ecac589d-7902-4160-b404-d42145111434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332007886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1332007886
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1389430891
Short name T238
Test name
Test status
Simulation time 46474899 ps
CPU time 1.13 seconds
Started Jul 04 05:01:15 PM PDT 24
Finished Jul 04 05:01:16 PM PDT 24
Peak memory 197032 kb
Host smart-72364e96-4814-4ca2-a10a-6695c99367b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389430891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1389430891
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.738579871
Short name T488
Test name
Test status
Simulation time 30763063188 ps
CPU time 209.22 seconds
Started Jul 04 05:01:15 PM PDT 24
Finished Jul 04 05:04:45 PM PDT 24
Peak memory 198620 kb
Host smart-129a4384-1515-441b-a1f1-f7dbc94b5556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738579871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.738579871
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.471492130
Short name T309
Test name
Test status
Simulation time 44564003 ps
CPU time 0.61 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 194524 kb
Host smart-01ca8c52-52df-494c-961b-cea0a79267d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471492130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.471492130
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.661332405
Short name T255
Test name
Test status
Simulation time 147930536 ps
CPU time 0.82 seconds
Started Jul 04 05:02:10 PM PDT 24
Finished Jul 04 05:02:11 PM PDT 24
Peak memory 195808 kb
Host smart-e925d5cd-8480-4a99-841c-ec423c0e2db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661332405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.661332405
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.786888419
Short name T62
Test name
Test status
Simulation time 545702127 ps
CPU time 16.29 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:29 PM PDT 24
Peak memory 196020 kb
Host smart-2cd3b337-d107-4daf-9fb6-25e831b85338
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786888419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.786888419
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1063564472
Short name T33
Test name
Test status
Simulation time 68669997 ps
CPU time 0.73 seconds
Started Jul 04 05:02:11 PM PDT 24
Finished Jul 04 05:02:11 PM PDT 24
Peak memory 196420 kb
Host smart-d2444707-410c-4477-aef7-87ff6db08522
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063564472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1063564472
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1053881292
Short name T527
Test name
Test status
Simulation time 59864948 ps
CPU time 1.25 seconds
Started Jul 04 05:02:11 PM PDT 24
Finished Jul 04 05:02:13 PM PDT 24
Peak memory 196628 kb
Host smart-5f491dd9-b77c-42ba-acc2-88e1952eaf3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053881292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1053881292
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.509393360
Short name T263
Test name
Test status
Simulation time 910868025 ps
CPU time 2.88 seconds
Started Jul 04 05:02:10 PM PDT 24
Finished Jul 04 05:02:13 PM PDT 24
Peak memory 198608 kb
Host smart-00318463-496d-461e-8a57-3eb1bcf31f1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509393360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.509393360
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3772452169
Short name T206
Test name
Test status
Simulation time 234715667 ps
CPU time 1.36 seconds
Started Jul 04 05:02:10 PM PDT 24
Finished Jul 04 05:02:12 PM PDT 24
Peak memory 197324 kb
Host smart-fc4e30ed-e658-466c-ad46-77fa66676a3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772452169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3772452169
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3881480003
Short name T427
Test name
Test status
Simulation time 99960995 ps
CPU time 0.78 seconds
Started Jul 04 05:02:11 PM PDT 24
Finished Jul 04 05:02:12 PM PDT 24
Peak memory 195848 kb
Host smart-162d43cf-35bb-42c0-9a51-f2b047e90ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881480003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3881480003
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.240965595
Short name T31
Test name
Test status
Simulation time 105858400 ps
CPU time 1.04 seconds
Started Jul 04 05:02:11 PM PDT 24
Finished Jul 04 05:02:12 PM PDT 24
Peak memory 196412 kb
Host smart-49e93b4f-449a-4a09-baa2-6d343ce75638
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240965595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.240965595
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3226328751
Short name T256
Test name
Test status
Simulation time 93774903 ps
CPU time 4.12 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:17 PM PDT 24
Peak memory 198500 kb
Host smart-858590ff-f96c-431e-b87b-922714569a4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226328751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3226328751
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1707812295
Short name T213
Test name
Test status
Simulation time 33208021 ps
CPU time 0.94 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 195864 kb
Host smart-9824cbf8-bc42-49af-826f-b0ed8175032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707812295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1707812295
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3472633137
Short name T169
Test name
Test status
Simulation time 88009018 ps
CPU time 1.44 seconds
Started Jul 04 05:02:13 PM PDT 24
Finished Jul 04 05:02:15 PM PDT 24
Peak memory 198556 kb
Host smart-bb197b94-0ecd-41c9-a94f-5f47c841235b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472633137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3472633137
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1125710726
Short name T472
Test name
Test status
Simulation time 14147789927 ps
CPU time 48.78 seconds
Started Jul 04 05:02:13 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 198660 kb
Host smart-17ac1e5e-5747-448d-af2d-c6ef694c71ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125710726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1125710726
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.1160489436
Short name T37
Test name
Test status
Simulation time 94825857946 ps
CPU time 1116.16 seconds
Started Jul 04 05:02:15 PM PDT 24
Finished Jul 04 05:20:51 PM PDT 24
Peak memory 198836 kb
Host smart-2f39084a-5637-4fa6-a85c-6aa15015b2d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1160489436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.1160489436
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.936208925
Short name T208
Test name
Test status
Simulation time 14843687 ps
CPU time 0.57 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:13 PM PDT 24
Peak memory 194548 kb
Host smart-d971782f-7d54-49dd-a138-32b6c77327d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936208925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.936208925
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1114809743
Short name T168
Test name
Test status
Simulation time 63342878 ps
CPU time 0.68 seconds
Started Jul 04 05:02:13 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 194612 kb
Host smart-2fad8450-3378-411d-94aa-98a15f03a828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114809743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1114809743
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3007977006
Short name T433
Test name
Test status
Simulation time 351246123 ps
CPU time 3.39 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:16 PM PDT 24
Peak memory 196548 kb
Host smart-0c06abfa-524b-4413-a326-00c2e49c98fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007977006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3007977006
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.388923529
Short name T222
Test name
Test status
Simulation time 262615642 ps
CPU time 1 seconds
Started Jul 04 05:02:14 PM PDT 24
Finished Jul 04 05:02:16 PM PDT 24
Peak memory 197140 kb
Host smart-32c1d085-94a2-4f84-9ed0-e69ef0c88cad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388923529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.388923529
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1769317159
Short name T565
Test name
Test status
Simulation time 256529942 ps
CPU time 1.12 seconds
Started Jul 04 05:02:11 PM PDT 24
Finished Jul 04 05:02:12 PM PDT 24
Peak memory 197284 kb
Host smart-3d06ed1a-c5ce-48ab-893b-52e5d6f24de7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769317159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1769317159
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.474660689
Short name T514
Test name
Test status
Simulation time 71388070 ps
CPU time 2.81 seconds
Started Jul 04 05:02:11 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 198584 kb
Host smart-5a937fb4-5446-4b90-8cdb-bba501aa68ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474660689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.474660689
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1210368778
Short name T575
Test name
Test status
Simulation time 123327432 ps
CPU time 2.68 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:16 PM PDT 24
Peak memory 196388 kb
Host smart-f764a004-db65-45d8-829f-de6f1ae9ead6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210368778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1210368778
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.4100866081
Short name T621
Test name
Test status
Simulation time 43455725 ps
CPU time 1.09 seconds
Started Jul 04 05:02:13 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 196364 kb
Host smart-c80587af-2a28-4303-b858-78f4f2bc26bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100866081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.4100866081
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1932283098
Short name T537
Test name
Test status
Simulation time 71065766 ps
CPU time 1.43 seconds
Started Jul 04 05:02:13 PM PDT 24
Finished Jul 04 05:02:15 PM PDT 24
Peak memory 197588 kb
Host smart-328c4e31-28ba-4a72-b292-a18f8b4cd2b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932283098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1932283098
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1133458338
Short name T315
Test name
Test status
Simulation time 1826105440 ps
CPU time 4.32 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:16 PM PDT 24
Peak memory 198500 kb
Host smart-bc20cfc4-b9f0-438d-9ed8-3d4c6f29d211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133458338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1133458338
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1665080724
Short name T289
Test name
Test status
Simulation time 178008943 ps
CPU time 1.28 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:13 PM PDT 24
Peak memory 197564 kb
Host smart-336a3065-c046-4609-8891-b2e9428e2784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665080724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1665080724
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3358805324
Short name T480
Test name
Test status
Simulation time 228331681 ps
CPU time 0.91 seconds
Started Jul 04 05:02:09 PM PDT 24
Finished Jul 04 05:02:10 PM PDT 24
Peak memory 196936 kb
Host smart-eb98e5d0-b2f4-4841-a503-f930f6ee9b3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358805324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3358805324
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2525672787
Short name T236
Test name
Test status
Simulation time 53951485774 ps
CPU time 189.01 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:05:22 PM PDT 24
Peak memory 198784 kb
Host smart-cc145953-3f54-406d-b01b-5b0d04c06211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525672787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2525672787
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1536772620
Short name T390
Test name
Test status
Simulation time 51955247 ps
CPU time 0.57 seconds
Started Jul 04 05:02:09 PM PDT 24
Finished Jul 04 05:02:10 PM PDT 24
Peak memory 194824 kb
Host smart-d0aeb60d-51e3-44c8-8922-afae1238a7d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536772620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1536772620
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2659179473
Short name T244
Test name
Test status
Simulation time 38284798 ps
CPU time 0.93 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 196988 kb
Host smart-1335eb7c-388b-4f0f-bd8b-acffec96a2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659179473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2659179473
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.230363634
Short name T489
Test name
Test status
Simulation time 2926924615 ps
CPU time 27.87 seconds
Started Jul 04 05:02:10 PM PDT 24
Finished Jul 04 05:02:38 PM PDT 24
Peak memory 197324 kb
Host smart-924e2196-b724-4c9f-ab4d-053d4a5bf5aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230363634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.230363634
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1367285801
Short name T580
Test name
Test status
Simulation time 76694987 ps
CPU time 0.89 seconds
Started Jul 04 05:02:15 PM PDT 24
Finished Jul 04 05:02:16 PM PDT 24
Peak memory 197520 kb
Host smart-35d408a3-4d38-40ca-a5f6-58d9986e6758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367285801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1367285801
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.847011682
Short name T125
Test name
Test status
Simulation time 32823836 ps
CPU time 1.05 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:13 PM PDT 24
Peak memory 196532 kb
Host smart-a260346d-8016-49a4-924f-095ae93118a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847011682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.847011682
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1455392718
Short name T319
Test name
Test status
Simulation time 343171823 ps
CPU time 3.34 seconds
Started Jul 04 05:02:11 PM PDT 24
Finished Jul 04 05:02:15 PM PDT 24
Peak memory 198544 kb
Host smart-121880df-1b2b-489b-9c84-271383fa6493
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455392718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1455392718
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.423094995
Short name T171
Test name
Test status
Simulation time 358359899 ps
CPU time 1.15 seconds
Started Jul 04 05:02:10 PM PDT 24
Finished Jul 04 05:02:11 PM PDT 24
Peak memory 196996 kb
Host smart-abe3db1b-4748-419c-97ca-5505e7d48ff1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423094995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
423094995
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2639962753
Short name T242
Test name
Test status
Simulation time 390009249 ps
CPU time 0.97 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 196496 kb
Host smart-c36960f4-1bc2-43fb-987c-24d1d832faa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639962753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2639962753
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.607848117
Short name T465
Test name
Test status
Simulation time 335170364 ps
CPU time 0.97 seconds
Started Jul 04 05:02:14 PM PDT 24
Finished Jul 04 05:02:15 PM PDT 24
Peak memory 196396 kb
Host smart-a73f1478-c5d4-4b8a-b488-7eda0fa5fc75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607848117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.607848117
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1408426372
Short name T596
Test name
Test status
Simulation time 58468355 ps
CPU time 2.65 seconds
Started Jul 04 05:02:11 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 198544 kb
Host smart-725fa8b8-9118-40f0-885b-1ee951d99562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408426372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1408426372
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3431714919
Short name T140
Test name
Test status
Simulation time 171353384 ps
CPU time 1.12 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:13 PM PDT 24
Peak memory 196144 kb
Host smart-309f1afa-7f6e-47af-a67e-27c59401ecb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431714919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3431714919
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3484878220
Short name T715
Test name
Test status
Simulation time 85250672 ps
CPU time 1.56 seconds
Started Jul 04 05:02:11 PM PDT 24
Finished Jul 04 05:02:12 PM PDT 24
Peak memory 197424 kb
Host smart-a8e69e38-0a53-4ac9-9d4d-c9f9f0c6fbc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484878220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3484878220
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.821209164
Short name T690
Test name
Test status
Simulation time 10358420284 ps
CPU time 139.41 seconds
Started Jul 04 05:02:13 PM PDT 24
Finished Jul 04 05:04:33 PM PDT 24
Peak memory 198760 kb
Host smart-0f16c465-fe95-4bd1-bc7f-2d5fe2c0abbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821209164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.821209164
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.389109893
Short name T568
Test name
Test status
Simulation time 106718509 ps
CPU time 0.59 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:24 PM PDT 24
Peak memory 194728 kb
Host smart-c7696bb5-4488-41b4-a992-7f6d00d70dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389109893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.389109893
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.792664761
Short name T251
Test name
Test status
Simulation time 256565628 ps
CPU time 0.88 seconds
Started Jul 04 05:02:25 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 197004 kb
Host smart-0fe9f476-80f5-461d-a2dd-5ce969440f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792664761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.792664761
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2135429424
Short name T389
Test name
Test status
Simulation time 2119087179 ps
CPU time 27.48 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:54 PM PDT 24
Peak memory 197108 kb
Host smart-2c699951-1c13-45f9-bede-1a2c256f6e85
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135429424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2135429424
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3095352480
Short name T449
Test name
Test status
Simulation time 94148687 ps
CPU time 1.1 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 197176 kb
Host smart-14aff0a0-bab4-4a69-8353-f1194507f5c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095352480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3095352480
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1683903976
Short name T149
Test name
Test status
Simulation time 58123568 ps
CPU time 0.79 seconds
Started Jul 04 05:02:22 PM PDT 24
Finished Jul 04 05:02:23 PM PDT 24
Peak memory 195896 kb
Host smart-7a2b5c67-dbc2-4d18-b1ee-88a2f06bdc6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683903976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1683903976
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1788959876
Short name T529
Test name
Test status
Simulation time 90495847 ps
CPU time 1.15 seconds
Started Jul 04 05:02:24 PM PDT 24
Finished Jul 04 05:02:26 PM PDT 24
Peak memory 197752 kb
Host smart-41c09da9-894b-4a98-9621-07981e0d669d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788959876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1788959876
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.194496436
Short name T521
Test name
Test status
Simulation time 275485015 ps
CPU time 2.67 seconds
Started Jul 04 05:02:22 PM PDT 24
Finished Jul 04 05:02:25 PM PDT 24
Peak memory 197568 kb
Host smart-44ab118f-3ee7-4ee7-bb5c-fec91f86253b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194496436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
194496436
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.4103055548
Short name T337
Test name
Test status
Simulation time 271687694 ps
CPU time 1.35 seconds
Started Jul 04 05:02:22 PM PDT 24
Finished Jul 04 05:02:24 PM PDT 24
Peak memory 197124 kb
Host smart-41623788-35f1-466e-be65-b41e28abf148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103055548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.4103055548
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.580941275
Short name T413
Test name
Test status
Simulation time 64674957 ps
CPU time 0.74 seconds
Started Jul 04 05:02:25 PM PDT 24
Finished Jul 04 05:02:26 PM PDT 24
Peak memory 195908 kb
Host smart-583872e7-1c07-42e8-a8da-8368651b04fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580941275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.580941275
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.649877024
Short name T639
Test name
Test status
Simulation time 65568150 ps
CPU time 1.81 seconds
Started Jul 04 05:02:21 PM PDT 24
Finished Jul 04 05:02:23 PM PDT 24
Peak memory 198476 kb
Host smart-233d9217-eaed-489c-a7f5-80905f35a8b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649877024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.649877024
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1654572143
Short name T551
Test name
Test status
Simulation time 269295701 ps
CPU time 1.02 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 197040 kb
Host smart-78ecc35a-ab05-4b17-b65f-d67e46a046c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654572143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1654572143
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1599876929
Short name T217
Test name
Test status
Simulation time 123313543 ps
CPU time 0.9 seconds
Started Jul 04 05:02:12 PM PDT 24
Finished Jul 04 05:02:14 PM PDT 24
Peak memory 196392 kb
Host smart-eefe8f92-3609-477f-ab71-bcf4841cba5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599876929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1599876929
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1339571009
Short name T443
Test name
Test status
Simulation time 3234968563 ps
CPU time 45.2 seconds
Started Jul 04 05:02:28 PM PDT 24
Finished Jul 04 05:03:14 PM PDT 24
Peak memory 198648 kb
Host smart-6b0b05ff-0181-42ee-b2b7-b950c7156a57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339571009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1339571009
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3074587199
Short name T221
Test name
Test status
Simulation time 12380388 ps
CPU time 0.58 seconds
Started Jul 04 05:02:24 PM PDT 24
Finished Jul 04 05:02:25 PM PDT 24
Peak memory 194724 kb
Host smart-ee6fe881-9dc4-4472-9a73-902503126752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074587199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3074587199
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.687640226
Short name T74
Test name
Test status
Simulation time 69799594 ps
CPU time 1 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 196400 kb
Host smart-9895d0f3-c1a5-4835-9c83-b427dd54a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687640226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.687640226
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.4007393765
Short name T352
Test name
Test status
Simulation time 990840050 ps
CPU time 9.76 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:38 PM PDT 24
Peak memory 197368 kb
Host smart-3a749e24-d48f-489b-9543-ef8961768f06
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007393765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.4007393765
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1861237944
Short name T1
Test name
Test status
Simulation time 349337908 ps
CPU time 1.13 seconds
Started Jul 04 05:02:22 PM PDT 24
Finished Jul 04 05:02:23 PM PDT 24
Peak memory 197200 kb
Host smart-782430ae-053f-4627-968d-b96c31a89d3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861237944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1861237944
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3582092726
Short name T697
Test name
Test status
Simulation time 148582317 ps
CPU time 0.68 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 194928 kb
Host smart-42a9781e-1c8d-460a-9011-aba859a95df4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582092726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3582092726
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2697477198
Short name T668
Test name
Test status
Simulation time 48102454 ps
CPU time 2 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:25 PM PDT 24
Peak memory 198744 kb
Host smart-869b2bd6-6764-4cc5-af67-a27119f5468d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697477198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2697477198
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1479953576
Short name T411
Test name
Test status
Simulation time 219454030 ps
CPU time 1.38 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:25 PM PDT 24
Peak memory 198044 kb
Host smart-0333f1ae-bd56-4dfb-ba4d-0d73e0508730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479953576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1479953576
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2253990483
Short name T613
Test name
Test status
Simulation time 60886950 ps
CPU time 0.89 seconds
Started Jul 04 05:02:25 PM PDT 24
Finished Jul 04 05:02:26 PM PDT 24
Peak memory 197844 kb
Host smart-ecc06f2c-03e2-4ffe-953f-48fff3e002c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253990483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2253990483
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2510688750
Short name T77
Test name
Test status
Simulation time 108929827 ps
CPU time 1.33 seconds
Started Jul 04 05:02:24 PM PDT 24
Finished Jul 04 05:02:26 PM PDT 24
Peak memory 197508 kb
Host smart-1d838ca5-1886-445b-ba29-ffc07e85b4b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510688750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2510688750
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2293290802
Short name T721
Test name
Test status
Simulation time 267267566 ps
CPU time 5.16 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:31 PM PDT 24
Peak memory 198520 kb
Host smart-9daeecfa-86be-4b54-8119-61f2506ead30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293290802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2293290802
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1484056843
Short name T492
Test name
Test status
Simulation time 256854412 ps
CPU time 1.26 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:25 PM PDT 24
Peak memory 198508 kb
Host smart-529cab10-a99f-44a9-9c73-6776a8480da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484056843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1484056843
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3688578862
Short name T484
Test name
Test status
Simulation time 319114274 ps
CPU time 1.33 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:24 PM PDT 24
Peak memory 197312 kb
Host smart-ab7a2f3f-922f-4f2b-8b9d-cc6a91451bf4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688578862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3688578862
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2621947701
Short name T518
Test name
Test status
Simulation time 46431184094 ps
CPU time 189.61 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:05:36 PM PDT 24
Peak memory 198628 kb
Host smart-a9283616-0add-4c7c-886f-ee7b6d6bfb01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621947701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2621947701
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1030792855
Short name T633
Test name
Test status
Simulation time 49065765 ps
CPU time 0.6 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:24 PM PDT 24
Peak memory 195488 kb
Host smart-4701849c-dec8-497d-a0b9-b5c3127c71a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030792855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1030792855
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1122741532
Short name T578
Test name
Test status
Simulation time 102408041 ps
CPU time 0.88 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 197048 kb
Host smart-ba59ccff-781d-4e5e-b670-021f5d722088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122741532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1122741532
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2800086566
Short name T136
Test name
Test status
Simulation time 259120906 ps
CPU time 7.57 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:31 PM PDT 24
Peak memory 197468 kb
Host smart-d0863180-894d-44f6-a50b-4527e1e23641
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800086566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2800086566
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1601782067
Short name T29
Test name
Test status
Simulation time 56385229 ps
CPU time 0.69 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 195964 kb
Host smart-da74a371-aabc-4715-b83a-3ba749079b99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601782067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1601782067
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3888668294
Short name T301
Test name
Test status
Simulation time 178639108 ps
CPU time 1.28 seconds
Started Jul 04 05:02:24 PM PDT 24
Finished Jul 04 05:02:25 PM PDT 24
Peak memory 196348 kb
Host smart-62686542-6b40-4de7-a3aa-1676e9bb9c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888668294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3888668294
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3279206674
Short name T64
Test name
Test status
Simulation time 52729535 ps
CPU time 2.19 seconds
Started Jul 04 05:02:24 PM PDT 24
Finished Jul 04 05:02:26 PM PDT 24
Peak memory 198564 kb
Host smart-4e4b7d60-b4d4-43a6-914f-ed2bdf306e55
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279206674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3279206674
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3095046635
Short name T403
Test name
Test status
Simulation time 42067837 ps
CPU time 1.16 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:25 PM PDT 24
Peak memory 196236 kb
Host smart-d9ed853e-262a-4a21-86c2-858672f6d55c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095046635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3095046635
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3198775554
Short name T265
Test name
Test status
Simulation time 52708798 ps
CPU time 1.09 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:29 PM PDT 24
Peak memory 196992 kb
Host smart-dba651b9-8f55-4da4-bc84-cc066346a245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198775554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3198775554
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.121944665
Short name T674
Test name
Test status
Simulation time 82545593 ps
CPU time 1.44 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 197648 kb
Host smart-12c5dd3a-dbef-4a5a-b766-e4fed7197b71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121944665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.121944665
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2600710744
Short name T233
Test name
Test status
Simulation time 247396891 ps
CPU time 3.1 seconds
Started Jul 04 05:02:24 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 198500 kb
Host smart-0863a967-4044-47b5-a7a7-723af1178d16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600710744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2600710744
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3167186389
Short name T202
Test name
Test status
Simulation time 37140039 ps
CPU time 0.88 seconds
Started Jul 04 05:02:24 PM PDT 24
Finished Jul 04 05:02:25 PM PDT 24
Peak memory 196380 kb
Host smart-45bc159f-b888-47ef-8a9b-1756edb8fd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167186389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3167186389
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3306666387
Short name T657
Test name
Test status
Simulation time 236718753 ps
CPU time 1.12 seconds
Started Jul 04 05:02:28 PM PDT 24
Finished Jul 04 05:02:29 PM PDT 24
Peak memory 196356 kb
Host smart-604d1bb5-1365-4bb6-afc3-2cd6054ee3a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306666387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3306666387
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.521087574
Short name T124
Test name
Test status
Simulation time 5555106235 ps
CPU time 84.36 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:03:48 PM PDT 24
Peak memory 198648 kb
Host smart-e7c57dbc-a3fa-4aa9-a4da-68848c6247aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521087574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.521087574
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2333234055
Short name T243
Test name
Test status
Simulation time 20244685 ps
CPU time 0.58 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 194508 kb
Host smart-9f730e99-9b8e-476b-9cd1-2df9ab4387e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333234055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2333234055
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2283189397
Short name T558
Test name
Test status
Simulation time 60121638 ps
CPU time 0.63 seconds
Started Jul 04 05:02:22 PM PDT 24
Finished Jul 04 05:02:23 PM PDT 24
Peak memory 195276 kb
Host smart-f85646ba-b322-464a-b808-64af338f8e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283189397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2283189397
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2826241729
Short name T603
Test name
Test status
Simulation time 619414349 ps
CPU time 16.19 seconds
Started Jul 04 05:02:20 PM PDT 24
Finished Jul 04 05:02:36 PM PDT 24
Peak memory 198536 kb
Host smart-5d8dffe9-0508-4e8e-9935-6a0b6a8b4aae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826241729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2826241729
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.766496042
Short name T423
Test name
Test status
Simulation time 126200328 ps
CPU time 0.75 seconds
Started Jul 04 05:02:22 PM PDT 24
Finished Jul 04 05:02:23 PM PDT 24
Peak memory 195400 kb
Host smart-2900bd81-a9b8-4f82-8b19-f3aa2a88353a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766496042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.766496042
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3528429805
Short name T624
Test name
Test status
Simulation time 441788714 ps
CPU time 1.53 seconds
Started Jul 04 05:02:28 PM PDT 24
Finished Jul 04 05:02:30 PM PDT 24
Peak memory 196404 kb
Host smart-520ae4bd-c73a-4aa0-8e85-a6543a26b246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528429805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3528429805
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.684702194
Short name T79
Test name
Test status
Simulation time 24760507 ps
CPU time 1.03 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 196648 kb
Host smart-7c12927e-5958-4950-887b-8bb2e8501810
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684702194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.684702194
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1170928719
Short name T478
Test name
Test status
Simulation time 55885995 ps
CPU time 1.44 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 197004 kb
Host smart-8807c470-32f4-46b7-aa3c-45afa0e17ddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170928719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1170928719
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2432611691
Short name T394
Test name
Test status
Simulation time 50127930 ps
CPU time 0.95 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:24 PM PDT 24
Peak memory 196328 kb
Host smart-6bff1270-22cd-4b7e-9936-efae5db46b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432611691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2432611691
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.401835301
Short name T456
Test name
Test status
Simulation time 38231677 ps
CPU time 1.01 seconds
Started Jul 04 05:02:25 PM PDT 24
Finished Jul 04 05:02:26 PM PDT 24
Peak memory 196472 kb
Host smart-652d1410-c341-4901-b23d-c2c243ebfed8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401835301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.401835301
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3281807119
Short name T673
Test name
Test status
Simulation time 1074811809 ps
CPU time 3.85 seconds
Started Jul 04 05:02:23 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 198536 kb
Host smart-6a8a9243-fb5b-44bf-9553-4b6c17efe77a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281807119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3281807119
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1045512076
Short name T61
Test name
Test status
Simulation time 159705971 ps
CPU time 1.28 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 196196 kb
Host smart-262fdd91-42a4-491a-8b8c-334705a699af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045512076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1045512076
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1563015560
Short name T587
Test name
Test status
Simulation time 283338770 ps
CPU time 1.2 seconds
Started Jul 04 05:02:25 PM PDT 24
Finished Jul 04 05:02:26 PM PDT 24
Peak memory 197028 kb
Host smart-d01a5ee4-d9b2-41cc-9ace-a5d38cb843d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563015560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1563015560
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4183321589
Short name T393
Test name
Test status
Simulation time 52050246643 ps
CPU time 173.8 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:05:20 PM PDT 24
Peak memory 198788 kb
Host smart-9f458431-cc75-404a-aea4-d7eaf8281783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183321589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4183321589
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.4238688948
Short name T563
Test name
Test status
Simulation time 50954477350 ps
CPU time 822.82 seconds
Started Jul 04 05:02:22 PM PDT 24
Finished Jul 04 05:16:06 PM PDT 24
Peak memory 198812 kb
Host smart-f870cf15-62a4-4722-91c6-e646646a1499
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4238688948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.4238688948
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1914851504
Short name T553
Test name
Test status
Simulation time 43580980 ps
CPU time 0.62 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 194368 kb
Host smart-aa9f8df7-7c51-41e9-826f-a9054c67203d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914851504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1914851504
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1343705313
Short name T290
Test name
Test status
Simulation time 26451625 ps
CPU time 0.76 seconds
Started Jul 04 05:02:28 PM PDT 24
Finished Jul 04 05:02:29 PM PDT 24
Peak memory 196524 kb
Host smart-f2006c84-ceb8-4f86-8b0d-2cddc4c24dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343705313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1343705313
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2433042075
Short name T407
Test name
Test status
Simulation time 126594316 ps
CPU time 6.64 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:40 PM PDT 24
Peak memory 198604 kb
Host smart-f8f1e8ad-58dc-405c-85cb-b76e2e833b3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433042075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2433042075
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1993951319
Short name T564
Test name
Test status
Simulation time 508070980 ps
CPU time 0.98 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 197244 kb
Host smart-ecfc4354-078f-4389-a992-90656ed3eecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993951319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1993951319
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1284401790
Short name T438
Test name
Test status
Simulation time 291525548 ps
CPU time 1.21 seconds
Started Jul 04 05:02:24 PM PDT 24
Finished Jul 04 05:02:26 PM PDT 24
Peak memory 196556 kb
Host smart-96a94ed8-fb0e-4f1f-9fc3-46b17042e82d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284401790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1284401790
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1908755321
Short name T161
Test name
Test status
Simulation time 47613081 ps
CPU time 1.83 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 197856 kb
Host smart-320a7d1a-21fc-40c0-8af7-15ee0ba47676
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908755321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1908755321
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3015203303
Short name T498
Test name
Test status
Simulation time 157991980 ps
CPU time 1.31 seconds
Started Jul 04 05:02:28 PM PDT 24
Finished Jul 04 05:02:30 PM PDT 24
Peak memory 196716 kb
Host smart-b1d43f81-0806-4d9f-99b9-6a891e2b9763
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015203303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3015203303
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2175540089
Short name T231
Test name
Test status
Simulation time 100867044 ps
CPU time 1.24 seconds
Started Jul 04 05:02:28 PM PDT 24
Finished Jul 04 05:02:29 PM PDT 24
Peak memory 197272 kb
Host smart-c39def90-ccc4-494d-9656-3e3428e76dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175540089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2175540089
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1030354664
Short name T414
Test name
Test status
Simulation time 41994965 ps
CPU time 0.94 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 196420 kb
Host smart-fc075f53-0c34-42ef-9468-22a9cabec731
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030354664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1030354664
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1594026100
Short name T247
Test name
Test status
Simulation time 966839904 ps
CPU time 6.42 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:34 PM PDT 24
Peak memory 198496 kb
Host smart-65bec1f8-dd94-49e4-bffb-0a81b9325374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594026100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1594026100
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1154226947
Short name T496
Test name
Test status
Simulation time 178989212 ps
CPU time 1.04 seconds
Started Jul 04 05:02:25 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 196808 kb
Host smart-00f79162-c994-4106-81dd-e0049860330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154226947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1154226947
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1770941444
Short name T431
Test name
Test status
Simulation time 251286623 ps
CPU time 1.17 seconds
Started Jul 04 05:02:32 PM PDT 24
Finished Jul 04 05:02:33 PM PDT 24
Peak memory 196132 kb
Host smart-7350ff3f-03b7-4d9c-99dc-6a90466c0a4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770941444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1770941444
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3432840966
Short name T82
Test name
Test status
Simulation time 22562773776 ps
CPU time 31.12 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:59 PM PDT 24
Peak memory 198744 kb
Host smart-07e591c2-1845-4e5e-98c7-8a63697d049a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432840966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3432840966
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2144524986
Short name T543
Test name
Test status
Simulation time 56241091 ps
CPU time 0.56 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 194516 kb
Host smart-35fb0864-9eec-4cc9-8904-57f8013074d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144524986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2144524986
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2961486238
Short name T333
Test name
Test status
Simulation time 25643564 ps
CPU time 0.93 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:29 PM PDT 24
Peak memory 197808 kb
Host smart-0c715bf8-7336-4743-a22d-3dd89e15c686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961486238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2961486238
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.4028607822
Short name T300
Test name
Test status
Simulation time 1165124806 ps
CPU time 4.59 seconds
Started Jul 04 05:02:28 PM PDT 24
Finished Jul 04 05:02:33 PM PDT 24
Peak memory 196600 kb
Host smart-c3e98d09-c4e5-4a3e-8ca6-93b30548f525
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028607822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.4028607822
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1072240866
Short name T291
Test name
Test status
Simulation time 118627816 ps
CPU time 0.78 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 196300 kb
Host smart-5d8e3486-3ef2-4d27-b175-a17fcf5b92e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072240866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1072240866
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2103042388
Short name T340
Test name
Test status
Simulation time 258047795 ps
CPU time 1.28 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 197400 kb
Host smart-29d87b1a-fd2a-4a48-8cda-f9247aeade74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103042388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2103042388
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1611851538
Short name T483
Test name
Test status
Simulation time 66390563 ps
CPU time 1.55 seconds
Started Jul 04 05:02:29 PM PDT 24
Finished Jul 04 05:02:31 PM PDT 24
Peak memory 198512 kb
Host smart-35fee15d-baab-43dd-ab8b-58efdc6b3b25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611851538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1611851538
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2994510504
Short name T198
Test name
Test status
Simulation time 1937567286 ps
CPU time 3.38 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:30 PM PDT 24
Peak memory 196208 kb
Host smart-20a50474-3ac4-4dd2-9c1d-97c74a33e077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994510504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2994510504
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.4271169070
Short name T699
Test name
Test status
Simulation time 112879724 ps
CPU time 0.87 seconds
Started Jul 04 05:02:25 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 197160 kb
Host smart-e783c603-e557-4ae8-af63-04ccf8ccd4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271169070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.4271169070
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1813970303
Short name T506
Test name
Test status
Simulation time 125479157 ps
CPU time 1.36 seconds
Started Jul 04 05:02:25 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 197544 kb
Host smart-e4a93b5c-1288-4829-9f43-977f4be99ca0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813970303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1813970303
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.315398778
Short name T531
Test name
Test status
Simulation time 482260691 ps
CPU time 6.56 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:40 PM PDT 24
Peak memory 198584 kb
Host smart-ff6ff427-b300-4047-86c6-467afb65d8e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315398778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.315398778
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.747596035
Short name T552
Test name
Test status
Simulation time 163495020 ps
CPU time 1.27 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 197412 kb
Host smart-928d18f5-7772-4062-b7d9-e1513a87d582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747596035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.747596035
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1666883215
Short name T19
Test name
Test status
Simulation time 63932527 ps
CPU time 0.91 seconds
Started Jul 04 05:02:27 PM PDT 24
Finished Jul 04 05:02:29 PM PDT 24
Peak memory 195808 kb
Host smart-8cc5ca37-fd6f-44fe-8084-1e845ec7b1fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666883215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1666883215
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3401423441
Short name T258
Test name
Test status
Simulation time 2222251706 ps
CPU time 49.76 seconds
Started Jul 04 05:02:32 PM PDT 24
Finished Jul 04 05:03:22 PM PDT 24
Peak memory 198648 kb
Host smart-f09cbbcd-2994-44e7-8b53-852190a7ec25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401423441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3401423441
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4051856804
Short name T548
Test name
Test status
Simulation time 18736447 ps
CPU time 0.58 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:34 PM PDT 24
Peak memory 195224 kb
Host smart-da9fc8ae-cbce-4fb1-89b9-a6e2180ab9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051856804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4051856804
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.436779448
Short name T278
Test name
Test status
Simulation time 23781350 ps
CPU time 0.75 seconds
Started Jul 04 05:02:26 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 195468 kb
Host smart-75e7b3e1-fce1-43eb-b8f4-3147a9232113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436779448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.436779448
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3201502706
Short name T490
Test name
Test status
Simulation time 2147049968 ps
CPU time 18.19 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:52 PM PDT 24
Peak memory 197444 kb
Host smart-6e4d0f54-fd2c-4693-80df-b0ffc9a13e2b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201502706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3201502706
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2465992558
Short name T346
Test name
Test status
Simulation time 283844306 ps
CPU time 0.93 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 198200 kb
Host smart-3cc4c087-a85b-4dcb-89b5-08e0a8f18985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465992558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2465992558
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2674071548
Short name T525
Test name
Test status
Simulation time 48593978 ps
CPU time 1.45 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 196456 kb
Host smart-7ca0615c-4a6c-4d4f-81c1-a042d256e322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674071548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2674071548
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1748046095
Short name T360
Test name
Test status
Simulation time 23620985 ps
CPU time 1.02 seconds
Started Jul 04 05:02:28 PM PDT 24
Finished Jul 04 05:02:29 PM PDT 24
Peak memory 196820 kb
Host smart-b36b5e74-6282-4f82-9d94-4c345f7f61d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748046095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1748046095
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.4112544790
Short name T193
Test name
Test status
Simulation time 156773291 ps
CPU time 2.88 seconds
Started Jul 04 05:02:32 PM PDT 24
Finished Jul 04 05:02:36 PM PDT 24
Peak memory 198600 kb
Host smart-c5911583-8d2a-40cd-8863-16b478459661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112544790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.4112544790
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1461143431
Short name T121
Test name
Test status
Simulation time 118542393 ps
CPU time 0.81 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:34 PM PDT 24
Peak memory 196012 kb
Host smart-02b78d17-3b35-4035-a211-b9adeb887626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461143431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1461143431
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1561768602
Short name T481
Test name
Test status
Simulation time 47534208 ps
CPU time 1.21 seconds
Started Jul 04 05:02:32 PM PDT 24
Finished Jul 04 05:02:34 PM PDT 24
Peak memory 196724 kb
Host smart-ae86442f-bca7-4d72-9656-b363e6ffa3d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561768602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1561768602
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2723671445
Short name T23
Test name
Test status
Simulation time 368327410 ps
CPU time 4.65 seconds
Started Jul 04 05:02:35 PM PDT 24
Finished Jul 04 05:02:40 PM PDT 24
Peak memory 198628 kb
Host smart-dd0e44f9-5ab1-4f6a-bf22-a8686ce3989f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723671445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2723671445
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3834522983
Short name T579
Test name
Test status
Simulation time 99943012 ps
CPU time 0.96 seconds
Started Jul 04 05:02:24 PM PDT 24
Finished Jul 04 05:02:25 PM PDT 24
Peak memory 197348 kb
Host smart-40348b40-68ac-4bbe-a499-d61e9ba1f96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834522983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3834522983
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2140227839
Short name T63
Test name
Test status
Simulation time 71407577 ps
CPU time 1.31 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 197136 kb
Host smart-81f6c65d-3b5b-4d53-94f5-cdabadd357e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140227839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2140227839
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2274877201
Short name T533
Test name
Test status
Simulation time 25688241342 ps
CPU time 151.33 seconds
Started Jul 04 05:02:34 PM PDT 24
Finished Jul 04 05:05:06 PM PDT 24
Peak memory 198660 kb
Host smart-6d5a4d91-3ebd-4628-8050-6d53b9fbb1b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274877201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2274877201
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.354961824
Short name T68
Test name
Test status
Simulation time 441250230905 ps
CPU time 1437.42 seconds
Started Jul 04 05:02:32 PM PDT 24
Finished Jul 04 05:26:29 PM PDT 24
Peak memory 198796 kb
Host smart-13264b5a-94e8-41b9-82b3-79bf8c42d915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=354961824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.354961824
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2706436936
Short name T176
Test name
Test status
Simulation time 22784454 ps
CPU time 0.58 seconds
Started Jul 04 05:01:26 PM PDT 24
Finished Jul 04 05:01:27 PM PDT 24
Peak memory 195260 kb
Host smart-f7533185-083d-4b67-b5f8-2a4ccc69940a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706436936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2706436936
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3293310975
Short name T691
Test name
Test status
Simulation time 26897359 ps
CPU time 0.93 seconds
Started Jul 04 05:01:17 PM PDT 24
Finished Jul 04 05:01:18 PM PDT 24
Peak memory 197700 kb
Host smart-d058b6a6-8610-4c31-8051-3a2769aebfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293310975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3293310975
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1391742582
Short name T701
Test name
Test status
Simulation time 543738346 ps
CPU time 3.89 seconds
Started Jul 04 05:01:24 PM PDT 24
Finished Jul 04 05:01:28 PM PDT 24
Peak memory 196312 kb
Host smart-a35c6b48-0ff0-4373-a58c-3fda3d98ce6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391742582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1391742582
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1106287429
Short name T274
Test name
Test status
Simulation time 323429923 ps
CPU time 1.08 seconds
Started Jul 04 05:01:20 PM PDT 24
Finished Jul 04 05:01:21 PM PDT 24
Peak memory 197052 kb
Host smart-8d7882d1-ddcf-4ccf-82e3-fdd96a4b0735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106287429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1106287429
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1695612330
Short name T557
Test name
Test status
Simulation time 165818921 ps
CPU time 1.21 seconds
Started Jul 04 05:01:14 PM PDT 24
Finished Jul 04 05:01:16 PM PDT 24
Peak memory 197548 kb
Host smart-5a094c64-3369-492a-aeb2-66264ad888ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695612330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1695612330
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.968596668
Short name T385
Test name
Test status
Simulation time 265102104 ps
CPU time 2.88 seconds
Started Jul 04 05:01:17 PM PDT 24
Finished Jul 04 05:01:20 PM PDT 24
Peak memory 198612 kb
Host smart-d7ac4493-7430-47d5-92bb-ef02a17605ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968596668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.968596668
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2768674675
Short name T27
Test name
Test status
Simulation time 314345437 ps
CPU time 2.4 seconds
Started Jul 04 05:01:18 PM PDT 24
Finished Jul 04 05:01:20 PM PDT 24
Peak memory 197720 kb
Host smart-64458a34-ffb4-4585-8d6c-252612c6646f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768674675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2768674675
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.617270032
Short name T460
Test name
Test status
Simulation time 110068464 ps
CPU time 1.36 seconds
Started Jul 04 05:01:15 PM PDT 24
Finished Jul 04 05:01:17 PM PDT 24
Peak memory 198668 kb
Host smart-99f54c9c-0a74-4fdb-a3e0-53ed683926b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617270032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.617270032
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1080555903
Short name T376
Test name
Test status
Simulation time 119770045 ps
CPU time 0.81 seconds
Started Jul 04 05:01:17 PM PDT 24
Finished Jul 04 05:01:18 PM PDT 24
Peak memory 195912 kb
Host smart-7c31c9e6-83c7-4f65-a644-9bcded1398e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080555903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1080555903
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1144372745
Short name T591
Test name
Test status
Simulation time 159689334 ps
CPU time 1.91 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:01:25 PM PDT 24
Peak memory 198520 kb
Host smart-c2b8c03b-a071-49cf-a7c0-f3fa4716291d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144372745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1144372745
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3200435630
Short name T56
Test name
Test status
Simulation time 193522643 ps
CPU time 0.78 seconds
Started Jul 04 05:01:25 PM PDT 24
Finished Jul 04 05:01:26 PM PDT 24
Peak memory 214088 kb
Host smart-e8bfa37e-db79-4a7b-b5e7-a1f7d3d8e07e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200435630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3200435630
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.4254081397
Short name T405
Test name
Test status
Simulation time 66061473 ps
CPU time 1.18 seconds
Started Jul 04 05:01:19 PM PDT 24
Finished Jul 04 05:01:20 PM PDT 24
Peak memory 196224 kb
Host smart-0c4cac4a-0445-40a9-96df-0aa9b417a03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254081397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.4254081397
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3256571249
Short name T574
Test name
Test status
Simulation time 92869732 ps
CPU time 1.17 seconds
Started Jul 04 05:01:16 PM PDT 24
Finished Jul 04 05:01:18 PM PDT 24
Peak memory 197324 kb
Host smart-7d4d2863-c5c7-4c22-bad1-85651c3aa61c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256571249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3256571249
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1177265926
Short name T349
Test name
Test status
Simulation time 62853289575 ps
CPU time 218.47 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:05:02 PM PDT 24
Peak memory 198644 kb
Host smart-7a815beb-591b-42df-96bb-8357c6ba819f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177265926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1177265926
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2955661839
Short name T636
Test name
Test status
Simulation time 101969089400 ps
CPU time 2417.38 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:41:41 PM PDT 24
Peak memory 198832 kb
Host smart-cde56a07-c117-4d21-a857-c5eb603167b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2955661839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2955661839
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2591185273
Short name T428
Test name
Test status
Simulation time 31050895 ps
CPU time 0.56 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:40 PM PDT 24
Peak memory 194640 kb
Host smart-f914567c-af2a-4ffe-aeda-d7c7c92f3e76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591185273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2591185273
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1842960122
Short name T209
Test name
Test status
Simulation time 79632864 ps
CPU time 0.71 seconds
Started Jul 04 05:02:34 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 195424 kb
Host smart-f52db10b-fb50-443b-b8e2-08a05b44368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842960122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1842960122
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1739160549
Short name T367
Test name
Test status
Simulation time 535387454 ps
CPU time 16.33 seconds
Started Jul 04 05:02:34 PM PDT 24
Finished Jul 04 05:02:51 PM PDT 24
Peak memory 197340 kb
Host smart-85605c3f-1955-42eb-8d2b-1ec2a6d12fbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739160549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1739160549
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.129622712
Short name T555
Test name
Test status
Simulation time 344353871 ps
CPU time 0.99 seconds
Started Jul 04 05:02:34 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 198352 kb
Host smart-eb1fa2c4-0d12-49f1-a8c4-b2177551263d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129622712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.129622712
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2128625650
Short name T528
Test name
Test status
Simulation time 82317556 ps
CPU time 1.28 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:41 PM PDT 24
Peak memory 197696 kb
Host smart-a8bd6b85-9c62-4bb6-aa28-1cc31875ad31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128625650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2128625650
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3051374447
Short name T617
Test name
Test status
Simulation time 144158894 ps
CPU time 2.81 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:36 PM PDT 24
Peak memory 198568 kb
Host smart-26ed7112-3e44-4880-9826-b57a8f83a7ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051374447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3051374447
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3035408289
Short name T214
Test name
Test status
Simulation time 291441178 ps
CPU time 2.69 seconds
Started Jul 04 05:02:34 PM PDT 24
Finished Jul 04 05:02:37 PM PDT 24
Peak memory 197888 kb
Host smart-43f76f44-75a2-4e37-bf67-ea738dcc52c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035408289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3035408289
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.760169137
Short name T586
Test name
Test status
Simulation time 152682087 ps
CPU time 1.01 seconds
Started Jul 04 05:02:32 PM PDT 24
Finished Jul 04 05:02:34 PM PDT 24
Peak memory 196492 kb
Host smart-f9275b93-cdc1-4629-a66e-d1c4efdb2751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760169137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.760169137
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2735531071
Short name T184
Test name
Test status
Simulation time 37376868 ps
CPU time 1.42 seconds
Started Jul 04 05:02:34 PM PDT 24
Finished Jul 04 05:02:36 PM PDT 24
Peak memory 197528 kb
Host smart-cd1ae7b1-cfc9-457f-9f54-ff0825e55290
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735531071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2735531071
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3628554022
Short name T420
Test name
Test status
Simulation time 7282217025 ps
CPU time 5.68 seconds
Started Jul 04 05:02:34 PM PDT 24
Finished Jul 04 05:02:40 PM PDT 24
Peak memory 198572 kb
Host smart-0e343c8b-1e74-4bb3-acc5-8a993abdf79f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628554022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3628554022
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3351237987
Short name T128
Test name
Test status
Simulation time 84852745 ps
CPU time 1.41 seconds
Started Jul 04 05:02:32 PM PDT 24
Finished Jul 04 05:02:34 PM PDT 24
Peak memory 197032 kb
Host smart-030474af-5654-4ae0-b8d4-325a7177a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351237987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3351237987
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3654995864
Short name T507
Test name
Test status
Simulation time 62445695 ps
CPU time 1.18 seconds
Started Jul 04 05:02:31 PM PDT 24
Finished Jul 04 05:02:33 PM PDT 24
Peak memory 196948 kb
Host smart-8705e96e-f16e-4925-ae98-ae0954d7688b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654995864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3654995864
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.271453486
Short name T477
Test name
Test status
Simulation time 14413408774 ps
CPU time 159.87 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:05:20 PM PDT 24
Peak memory 198736 kb
Host smart-7993e6c3-5e74-4619-810d-b91ff51369f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271453486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.271453486
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2443203528
Short name T35
Test name
Test status
Simulation time 44597099891 ps
CPU time 747.79 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:15:08 PM PDT 24
Peak memory 198880 kb
Host smart-36aef3a4-467d-4542-8d6e-6f29ea947017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2443203528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2443203528
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3134396578
Short name T655
Test name
Test status
Simulation time 64096132 ps
CPU time 0.7 seconds
Started Jul 04 05:02:32 PM PDT 24
Finished Jul 04 05:02:33 PM PDT 24
Peak memory 195708 kb
Host smart-c0efa069-4501-47f3-a462-a54567a0e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134396578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3134396578
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3510590547
Short name T295
Test name
Test status
Simulation time 167706230 ps
CPU time 8.27 seconds
Started Jul 04 05:02:35 PM PDT 24
Finished Jul 04 05:02:43 PM PDT 24
Peak memory 197460 kb
Host smart-6bde8029-bc04-4668-9e76-a78819654030
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510590547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3510590547
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3864921212
Short name T648
Test name
Test status
Simulation time 68888815 ps
CPU time 0.89 seconds
Started Jul 04 05:02:34 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 197632 kb
Host smart-d12bc38d-4f5a-44e9-9b2d-d5044caebe08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864921212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3864921212
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2556023731
Short name T257
Test name
Test status
Simulation time 38738866 ps
CPU time 0.69 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:41 PM PDT 24
Peak memory 195640 kb
Host smart-8c645acb-698e-4041-bb69-cbe5315888f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556023731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2556023731
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.662711603
Short name T228
Test name
Test status
Simulation time 76681605 ps
CPU time 1.79 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 197296 kb
Host smart-5ce00b77-6f47-4e61-b1d9-228530390ebe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662711603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.662711603
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2517285801
Short name T163
Test name
Test status
Simulation time 630304362 ps
CPU time 3.03 seconds
Started Jul 04 05:02:35 PM PDT 24
Finished Jul 04 05:02:38 PM PDT 24
Peak memory 197672 kb
Host smart-4267c6b7-eddd-4028-b052-51718cdc1f80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517285801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2517285801
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.4157521809
Short name T323
Test name
Test status
Simulation time 52666661 ps
CPU time 1.44 seconds
Started Jul 04 05:02:34 PM PDT 24
Finished Jul 04 05:02:36 PM PDT 24
Peak memory 198596 kb
Host smart-9fb30995-5ac0-486d-bd6e-16304642394a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157521809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.4157521809
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1158261060
Short name T499
Test name
Test status
Simulation time 24506233 ps
CPU time 0.71 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:34 PM PDT 24
Peak memory 194828 kb
Host smart-8780bb0a-cbdc-4a98-bc47-2c326cb29edb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158261060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1158261060
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3714599435
Short name T380
Test name
Test status
Simulation time 1225182130 ps
CPU time 4.34 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:38 PM PDT 24
Peak memory 198364 kb
Host smart-50cefa77-069b-4a57-be18-733393d48cb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714599435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3714599435
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.447207470
Short name T364
Test name
Test status
Simulation time 57031212 ps
CPU time 1.48 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 197312 kb
Host smart-57daf228-ae57-43f1-adca-a4b5ed19a22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447207470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.447207470
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1605113354
Short name T152
Test name
Test status
Simulation time 209032871 ps
CPU time 1.13 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:02:35 PM PDT 24
Peak memory 196360 kb
Host smart-40858d07-4a72-4b67-985f-759b02dce51b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605113354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1605113354
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3202528808
Short name T277
Test name
Test status
Simulation time 24348484246 ps
CPU time 140.56 seconds
Started Jul 04 05:02:33 PM PDT 24
Finished Jul 04 05:04:54 PM PDT 24
Peak memory 198676 kb
Host smart-6cfc2561-a7cf-4e41-b2e9-e3067fcd7933
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202528808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3202528808
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3676613344
Short name T642
Test name
Test status
Simulation time 42417166 ps
CPU time 0.58 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:41 PM PDT 24
Peak memory 195228 kb
Host smart-068b3d53-1f2c-43f3-9fc7-48cdcf9e6526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676613344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3676613344
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1695696648
Short name T593
Test name
Test status
Simulation time 77088500 ps
CPU time 0.88 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:42 PM PDT 24
Peak memory 196404 kb
Host smart-2304c25f-6f8c-48b1-a003-3756dbe9a111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695696648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1695696648
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1768748294
Short name T455
Test name
Test status
Simulation time 477167871 ps
CPU time 17.74 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:03:00 PM PDT 24
Peak memory 196156 kb
Host smart-903d0d71-ea0f-4602-99cb-0ef36f7742dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768748294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1768748294
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2766405023
Short name T310
Test name
Test status
Simulation time 34174497 ps
CPU time 0.74 seconds
Started Jul 04 05:02:38 PM PDT 24
Finished Jul 04 05:02:39 PM PDT 24
Peak memory 196004 kb
Host smart-62fad366-2eb4-4d0b-98eb-7373aa370797
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766405023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2766405023
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.346352619
Short name T510
Test name
Test status
Simulation time 156190263 ps
CPU time 0.86 seconds
Started Jul 04 05:02:38 PM PDT 24
Finished Jul 04 05:02:39 PM PDT 24
Peak memory 197192 kb
Host smart-96909720-85ce-4e00-acff-3fa9ebeebf08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346352619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.346352619
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1718219651
Short name T298
Test name
Test status
Simulation time 90196197 ps
CPU time 3.86 seconds
Started Jul 04 05:02:45 PM PDT 24
Finished Jul 04 05:02:49 PM PDT 24
Peak memory 198544 kb
Host smart-ff7cf588-018b-48c4-a0c8-f77796f70e5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718219651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1718219651
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1759885580
Short name T167
Test name
Test status
Simulation time 662809983 ps
CPU time 2.7 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:43 PM PDT 24
Peak memory 198556 kb
Host smart-3ff3ccd5-a1c3-482c-ad76-51810e195a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759885580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1759885580
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3178599420
Short name T409
Test name
Test status
Simulation time 74322042 ps
CPU time 0.74 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:41 PM PDT 24
Peak memory 195848 kb
Host smart-aa28c3ba-3e0c-47b4-a8ef-5b41a5fbbcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178599420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3178599420
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3215562049
Short name T402
Test name
Test status
Simulation time 385746166 ps
CPU time 1.13 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:02:43 PM PDT 24
Peak memory 197212 kb
Host smart-d65f866a-c826-463f-bda7-e9608573fe8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215562049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3215562049
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3229011983
Short name T119
Test name
Test status
Simulation time 258442579 ps
CPU time 4.03 seconds
Started Jul 04 05:02:45 PM PDT 24
Finished Jul 04 05:02:49 PM PDT 24
Peak memory 198500 kb
Host smart-0a9c706e-0013-47c1-a382-762de7154b6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229011983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3229011983
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1019125934
Short name T172
Test name
Test status
Simulation time 111036915 ps
CPU time 1.22 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:42 PM PDT 24
Peak memory 196296 kb
Host smart-28c313cc-1bd7-4db5-8ea5-f9baa623742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019125934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1019125934
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2925544931
Short name T638
Test name
Test status
Simulation time 193327005 ps
CPU time 1.23 seconds
Started Jul 04 05:02:41 PM PDT 24
Finished Jul 04 05:02:42 PM PDT 24
Peak memory 196348 kb
Host smart-0fc976f9-ff29-4619-ad0b-6372233a79e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925544931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2925544931
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1301854092
Short name T8
Test name
Test status
Simulation time 10021858715 ps
CPU time 115.39 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:04:36 PM PDT 24
Peak memory 198652 kb
Host smart-de024092-a5fc-42f7-bc6f-e8463eae9875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301854092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1301854092
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3037095869
Short name T276
Test name
Test status
Simulation time 17353933 ps
CPU time 0.59 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:02:43 PM PDT 24
Peak memory 194636 kb
Host smart-ad312325-9f7b-437e-80a2-c930808393fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037095869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3037095869
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2936094562
Short name T448
Test name
Test status
Simulation time 78373284 ps
CPU time 0.8 seconds
Started Jul 04 05:02:46 PM PDT 24
Finished Jul 04 05:02:47 PM PDT 24
Peak memory 195944 kb
Host smart-66b22552-9a79-44e8-8dcb-e4dfebbab73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936094562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2936094562
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.375578488
Short name T379
Test name
Test status
Simulation time 3975451912 ps
CPU time 21.65 seconds
Started Jul 04 05:02:39 PM PDT 24
Finished Jul 04 05:03:01 PM PDT 24
Peak memory 197608 kb
Host smart-2ad6b7f6-328f-4771-8e59-80b4787bb518
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375578488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.375578488
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1987701526
Short name T532
Test name
Test status
Simulation time 53591541 ps
CPU time 0.92 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:02:43 PM PDT 24
Peak memory 196544 kb
Host smart-ea990c11-87e8-4f95-8750-a2a586894a92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987701526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1987701526
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.601775347
Short name T463
Test name
Test status
Simulation time 569076964 ps
CPU time 0.88 seconds
Started Jul 04 05:02:46 PM PDT 24
Finished Jul 04 05:02:47 PM PDT 24
Peak memory 196160 kb
Host smart-d722e5c0-0f1d-432c-ab66-5f421032c93f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601775347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.601775347
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3543824698
Short name T692
Test name
Test status
Simulation time 39935453 ps
CPU time 1.75 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:02:44 PM PDT 24
Peak memory 198628 kb
Host smart-0ea145a4-1a7a-45a5-ba9b-ae09e3ec03a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543824698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3543824698
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2700304097
Short name T464
Test name
Test status
Simulation time 78864736 ps
CPU time 2.62 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:02:45 PM PDT 24
Peak memory 198568 kb
Host smart-45dd041a-fac5-4e61-9769-08904c2e2149
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700304097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2700304097
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2916843466
Short name T686
Test name
Test status
Simulation time 103088101 ps
CPU time 1.21 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:42 PM PDT 24
Peak memory 197216 kb
Host smart-d170d1d0-ccaa-4c3e-bf4b-af92d2395a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916843466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2916843466
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1118100165
Short name T526
Test name
Test status
Simulation time 21729564 ps
CPU time 0.66 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:02:43 PM PDT 24
Peak memory 195596 kb
Host smart-6df30118-23c2-4c2e-9fa0-2bcad832ad76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118100165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1118100165
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1911263157
Short name T321
Test name
Test status
Simulation time 299569171 ps
CPU time 2.31 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:43 PM PDT 24
Peak memory 198512 kb
Host smart-f560e784-d7ff-4c16-ab66-43dc57169a2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911263157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1911263157
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3605930393
Short name T700
Test name
Test status
Simulation time 190560253 ps
CPU time 0.95 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:42 PM PDT 24
Peak memory 197020 kb
Host smart-716e133e-72d7-49d1-b6cd-eda181c99d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605930393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3605930393
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1960448632
Short name T712
Test name
Test status
Simulation time 142409681 ps
CPU time 1.28 seconds
Started Jul 04 05:02:40 PM PDT 24
Finished Jul 04 05:02:41 PM PDT 24
Peak memory 196064 kb
Host smart-9cf3ad87-4125-4cfa-830f-c35347256780
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960448632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1960448632
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3604281217
Short name T440
Test name
Test status
Simulation time 8531006019 ps
CPU time 21.2 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 198664 kb
Host smart-9247bb3f-8b97-4aeb-8f78-5069bf222b99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604281217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3604281217
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2443279279
Short name T36
Test name
Test status
Simulation time 43065551632 ps
CPU time 858.08 seconds
Started Jul 04 05:02:45 PM PDT 24
Finished Jul 04 05:17:03 PM PDT 24
Peak memory 198808 kb
Host smart-5a872ed5-40ce-4e77-a015-f396c7dfff19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2443279279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2443279279
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1186875463
Short name T513
Test name
Test status
Simulation time 19809642 ps
CPU time 0.62 seconds
Started Jul 04 05:02:50 PM PDT 24
Finished Jul 04 05:02:51 PM PDT 24
Peak memory 195192 kb
Host smart-3e2754c9-d552-4453-a579-0c160a6ea4ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186875463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1186875463
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1004815345
Short name T373
Test name
Test status
Simulation time 62616104 ps
CPU time 0.66 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:02:43 PM PDT 24
Peak memory 195292 kb
Host smart-c258637f-8b9f-4688-b980-d16d17a29b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004815345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1004815345
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.955364359
Short name T606
Test name
Test status
Simulation time 775825936 ps
CPU time 26.7 seconds
Started Jul 04 05:02:48 PM PDT 24
Finished Jul 04 05:03:15 PM PDT 24
Peak memory 198528 kb
Host smart-7de965e4-45b8-473a-ac03-a901a015c269
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955364359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.955364359
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.940102569
Short name T240
Test name
Test status
Simulation time 364839961 ps
CPU time 0.87 seconds
Started Jul 04 05:02:47 PM PDT 24
Finished Jul 04 05:02:48 PM PDT 24
Peak memory 196556 kb
Host smart-ee763c12-b56b-41c4-b90f-7d0284af6494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940102569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.940102569
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.229108186
Short name T154
Test name
Test status
Simulation time 406268670 ps
CPU time 1.27 seconds
Started Jul 04 05:02:41 PM PDT 24
Finished Jul 04 05:02:42 PM PDT 24
Peak memory 196504 kb
Host smart-007003df-4498-4a7f-8336-26be8353ba16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229108186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.229108186
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3299083902
Short name T358
Test name
Test status
Simulation time 207426318 ps
CPU time 2.41 seconds
Started Jul 04 05:02:49 PM PDT 24
Finished Jul 04 05:02:51 PM PDT 24
Peak memory 198732 kb
Host smart-996416c9-ee66-4bba-b3b2-08c21ad5faba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299083902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3299083902
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1779866773
Short name T711
Test name
Test status
Simulation time 272646232 ps
CPU time 2.32 seconds
Started Jul 04 05:02:49 PM PDT 24
Finished Jul 04 05:02:52 PM PDT 24
Peak memory 197112 kb
Host smart-6f13b3a4-e8bd-4856-886b-9b50e951688a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779866773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1779866773
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3723578510
Short name T412
Test name
Test status
Simulation time 174958187 ps
CPU time 1.41 seconds
Started Jul 04 05:02:41 PM PDT 24
Finished Jul 04 05:02:42 PM PDT 24
Peak memory 197764 kb
Host smart-f87c839a-a360-47a6-bab2-18f6f5924120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723578510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3723578510
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1701121324
Short name T334
Test name
Test status
Simulation time 152714070 ps
CPU time 1.18 seconds
Started Jul 04 05:02:42 PM PDT 24
Finished Jul 04 05:02:44 PM PDT 24
Peak memory 197372 kb
Host smart-6bd6e1a2-0e6d-4988-be32-b000529d4186
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701121324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1701121324
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3996414659
Short name T141
Test name
Test status
Simulation time 60452638 ps
CPU time 2.66 seconds
Started Jul 04 05:02:48 PM PDT 24
Finished Jul 04 05:02:51 PM PDT 24
Peak memory 198480 kb
Host smart-5e510fb4-5d27-4e8a-ba0b-436a2d5d60bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996414659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3996414659
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1817114979
Short name T25
Test name
Test status
Simulation time 219180180 ps
CPU time 0.85 seconds
Started Jul 04 05:02:41 PM PDT 24
Finished Jul 04 05:02:42 PM PDT 24
Peak memory 195796 kb
Host smart-fc0d7e4e-6b4d-41b3-9bbb-e9c7c5742e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817114979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1817114979
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.4100789404
Short name T374
Test name
Test status
Simulation time 46214277 ps
CPU time 0.77 seconds
Started Jul 04 05:02:46 PM PDT 24
Finished Jul 04 05:02:47 PM PDT 24
Peak memory 195836 kb
Host smart-831f3e05-8e42-4714-9f71-0b2a0e91ed08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100789404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.4100789404
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2779827180
Short name T326
Test name
Test status
Simulation time 24766370078 ps
CPU time 163.22 seconds
Started Jul 04 05:02:48 PM PDT 24
Finished Jul 04 05:05:32 PM PDT 24
Peak memory 198668 kb
Host smart-273e4b3f-55da-4e6c-8bc5-89bc22714e11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779827180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2779827180
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1548736202
Short name T26
Test name
Test status
Simulation time 34428570 ps
CPU time 0.59 seconds
Started Jul 04 05:02:47 PM PDT 24
Finished Jul 04 05:02:48 PM PDT 24
Peak memory 194612 kb
Host smart-07e889f3-971f-4a4a-b255-9fd08666f509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548736202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1548736202
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3811717895
Short name T241
Test name
Test status
Simulation time 22426261 ps
CPU time 0.69 seconds
Started Jul 04 05:02:49 PM PDT 24
Finished Jul 04 05:02:50 PM PDT 24
Peak memory 194644 kb
Host smart-9b1302a0-fe4b-4b7c-bfe2-90349d264d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811717895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3811717895
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4044808438
Short name T417
Test name
Test status
Simulation time 1829716857 ps
CPU time 9.21 seconds
Started Jul 04 05:02:51 PM PDT 24
Finished Jul 04 05:03:00 PM PDT 24
Peak memory 197316 kb
Host smart-533bac8e-13ab-4a77-816c-fe8f771d303e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044808438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4044808438
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.813916796
Short name T245
Test name
Test status
Simulation time 48126570 ps
CPU time 0.65 seconds
Started Jul 04 05:02:48 PM PDT 24
Finished Jul 04 05:02:49 PM PDT 24
Peak memory 195776 kb
Host smart-44464898-092c-4d93-882a-ccc917ddfb9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813916796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.813916796
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3358062389
Short name T567
Test name
Test status
Simulation time 23259934 ps
CPU time 0.81 seconds
Started Jul 04 05:02:48 PM PDT 24
Finished Jul 04 05:02:50 PM PDT 24
Peak memory 196040 kb
Host smart-8d0a63b6-eeb9-47ec-855f-6474a6cfd7d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358062389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3358062389
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.765064346
Short name T451
Test name
Test status
Simulation time 91234195 ps
CPU time 2.12 seconds
Started Jul 04 05:02:46 PM PDT 24
Finished Jul 04 05:02:48 PM PDT 24
Peak memory 196880 kb
Host smart-c282186c-a29f-434f-ae2a-5c73c5caae42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765064346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.765064346
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1479186665
Short name T620
Test name
Test status
Simulation time 146761904 ps
CPU time 2.87 seconds
Started Jul 04 05:02:49 PM PDT 24
Finished Jul 04 05:02:52 PM PDT 24
Peak memory 196484 kb
Host smart-a2676966-ecaf-468c-ac94-176b0a065dce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479186665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1479186665
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3442961237
Short name T630
Test name
Test status
Simulation time 31659157 ps
CPU time 0.99 seconds
Started Jul 04 05:02:47 PM PDT 24
Finished Jul 04 05:02:48 PM PDT 24
Peak memory 196604 kb
Host smart-b11f7e76-4b64-4611-9857-099a7d596916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442961237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3442961237
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.360179279
Short name T628
Test name
Test status
Simulation time 42935283 ps
CPU time 1.06 seconds
Started Jul 04 05:02:48 PM PDT 24
Finished Jul 04 05:02:49 PM PDT 24
Peak memory 196452 kb
Host smart-d1c627ab-a46c-445c-a21d-a86dce5eeaea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360179279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.360179279
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.168333921
Short name T5
Test name
Test status
Simulation time 180270710 ps
CPU time 2.4 seconds
Started Jul 04 05:02:46 PM PDT 24
Finished Jul 04 05:02:49 PM PDT 24
Peak memory 198540 kb
Host smart-7bb2fd66-6550-42ce-8ad7-c884b5d0825b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168333921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.168333921
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1244384373
Short name T308
Test name
Test status
Simulation time 120044718 ps
CPU time 1.09 seconds
Started Jul 04 05:02:46 PM PDT 24
Finished Jul 04 05:02:48 PM PDT 24
Peak memory 196384 kb
Host smart-33327e69-295f-445b-b964-2bb4de928a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244384373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1244384373
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3933447228
Short name T183
Test name
Test status
Simulation time 249752502 ps
CPU time 1.08 seconds
Started Jul 04 05:02:50 PM PDT 24
Finished Jul 04 05:02:51 PM PDT 24
Peak memory 196208 kb
Host smart-f78edd12-5d42-4e0b-8db6-e96683902a4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933447228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3933447228
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3574716083
Short name T292
Test name
Test status
Simulation time 34466887172 ps
CPU time 123.45 seconds
Started Jul 04 05:02:50 PM PDT 24
Finished Jul 04 05:04:53 PM PDT 24
Peak memory 198632 kb
Host smart-6a825eba-0dac-4ed1-a71d-4238a916616a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574716083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3574716083
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1406004742
Short name T491
Test name
Test status
Simulation time 12325830461 ps
CPU time 215.48 seconds
Started Jul 04 05:02:47 PM PDT 24
Finished Jul 04 05:06:23 PM PDT 24
Peak memory 198808 kb
Host smart-c326be6b-7fbc-4682-a791-38c1ca41c926
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1406004742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1406004742
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2170902535
Short name T361
Test name
Test status
Simulation time 18049510 ps
CPU time 0.59 seconds
Started Jul 04 05:02:55 PM PDT 24
Finished Jul 04 05:02:56 PM PDT 24
Peak memory 194516 kb
Host smart-cff7d984-4aa3-408b-8f75-c5e173c51b75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170902535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2170902535
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3031778569
Short name T610
Test name
Test status
Simulation time 22708846 ps
CPU time 0.61 seconds
Started Jul 04 05:02:55 PM PDT 24
Finished Jul 04 05:02:56 PM PDT 24
Peak memory 194572 kb
Host smart-6379011d-7888-4dce-9a60-0ce41ec5e1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031778569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3031778569
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.653992150
Short name T130
Test name
Test status
Simulation time 677549799 ps
CPU time 16.97 seconds
Started Jul 04 05:02:54 PM PDT 24
Finished Jul 04 05:03:11 PM PDT 24
Peak memory 198504 kb
Host smart-9b2bcf28-436e-4c9d-a8a6-f7bcb4364dc5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653992150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.653992150
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2679898488
Short name T406
Test name
Test status
Simulation time 66819789 ps
CPU time 0.71 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:03 PM PDT 24
Peak memory 194996 kb
Host smart-72d09f0a-f742-41a5-8b97-3df5ef28c022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679898488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2679898488
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1228661689
Short name T75
Test name
Test status
Simulation time 84795192 ps
CPU time 0.89 seconds
Started Jul 04 05:02:55 PM PDT 24
Finished Jul 04 05:02:56 PM PDT 24
Peak memory 196864 kb
Host smart-a3ffc8b1-43ff-499a-afb7-222c59832f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228661689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1228661689
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2906177455
Short name T284
Test name
Test status
Simulation time 20364079 ps
CPU time 0.91 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 196780 kb
Host smart-9649cfd2-90e2-4b70-b5fc-8d80b1624201
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906177455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2906177455
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.919805343
Short name T647
Test name
Test status
Simulation time 71792953 ps
CPU time 2.28 seconds
Started Jul 04 05:02:56 PM PDT 24
Finished Jul 04 05:02:58 PM PDT 24
Peak memory 197568 kb
Host smart-2eefc80e-5c20-4fc9-82be-5c461407588d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919805343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
919805343
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2120999531
Short name T632
Test name
Test status
Simulation time 19357732 ps
CPU time 0.68 seconds
Started Jul 04 05:02:57 PM PDT 24
Finished Jul 04 05:02:58 PM PDT 24
Peak memory 194888 kb
Host smart-05620d67-8b47-4db0-a161-bf5b28f3fec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120999531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2120999531
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.4202456492
Short name T58
Test name
Test status
Simulation time 126349491 ps
CPU time 0.92 seconds
Started Jul 04 05:02:56 PM PDT 24
Finished Jul 04 05:02:57 PM PDT 24
Peak memory 196492 kb
Host smart-a2a32740-9b0d-4c38-a46e-b599bb872b6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202456492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.4202456492
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.811169507
Short name T2
Test name
Test status
Simulation time 6283327996 ps
CPU time 5.09 seconds
Started Jul 04 05:02:57 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 198588 kb
Host smart-4aebcbc9-98c2-4c60-9c96-2f89176b0a7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811169507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.811169507
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2645699130
Short name T76
Test name
Test status
Simulation time 42754987 ps
CPU time 0.98 seconds
Started Jul 04 05:02:47 PM PDT 24
Finished Jul 04 05:02:49 PM PDT 24
Peak memory 195900 kb
Host smart-d26afe3e-a52d-4692-aa94-1ebdb061a728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645699130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2645699130
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2421726081
Short name T223
Test name
Test status
Simulation time 124109115 ps
CPU time 1.08 seconds
Started Jul 04 05:02:51 PM PDT 24
Finished Jul 04 05:02:52 PM PDT 24
Peak memory 196384 kb
Host smart-1798dc65-0b55-4a2e-805e-b65caffe5a53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421726081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2421726081
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1365286031
Short name T355
Test name
Test status
Simulation time 5052363986 ps
CPU time 68.22 seconds
Started Jul 04 05:02:59 PM PDT 24
Finished Jul 04 05:04:07 PM PDT 24
Peak memory 198652 kb
Host smart-aa0efcf8-0eb3-4d3c-83c5-3123eab91c43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365286031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1365286031
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2946408657
Short name T371
Test name
Test status
Simulation time 257861168934 ps
CPU time 1488.98 seconds
Started Jul 04 05:02:56 PM PDT 24
Finished Jul 04 05:27:45 PM PDT 24
Peak memory 198948 kb
Host smart-894e4f3a-e851-4f24-9626-96277fa9a196
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2946408657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2946408657
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1908225312
Short name T205
Test name
Test status
Simulation time 13134631 ps
CPU time 0.59 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 194520 kb
Host smart-439da487-5a11-4028-8d74-c807e1965e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908225312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1908225312
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2085621029
Short name T659
Test name
Test status
Simulation time 47865841 ps
CPU time 0.97 seconds
Started Jul 04 05:02:56 PM PDT 24
Finished Jul 04 05:02:57 PM PDT 24
Peak memory 197748 kb
Host smart-de342af8-b67b-4beb-b5ac-a5841a9125de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085621029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2085621029
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2059966101
Short name T273
Test name
Test status
Simulation time 1054924379 ps
CPU time 26.66 seconds
Started Jul 04 05:03:00 PM PDT 24
Finished Jul 04 05:03:26 PM PDT 24
Peak memory 197624 kb
Host smart-2be39327-479d-4f10-adee-41cc865c4d22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059966101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2059966101
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1921138278
Short name T645
Test name
Test status
Simulation time 123631369 ps
CPU time 0.88 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 196552 kb
Host smart-d504406b-840f-4bcb-bdde-0fc69fd8173a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921138278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1921138278
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.823123159
Short name T473
Test name
Test status
Simulation time 42052326 ps
CPU time 1.17 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 196760 kb
Host smart-27c0e9a7-ded2-4af7-ac98-8f7bbe276f0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823123159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.823123159
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1937134825
Short name T476
Test name
Test status
Simulation time 443662250 ps
CPU time 3.38 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:05 PM PDT 24
Peak memory 197636 kb
Host smart-682aedb2-661b-4644-a1c2-a5e9fcd1529c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937134825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1937134825
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3868417897
Short name T129
Test name
Test status
Simulation time 167136068 ps
CPU time 0.92 seconds
Started Jul 04 05:02:54 PM PDT 24
Finished Jul 04 05:02:55 PM PDT 24
Peak memory 197084 kb
Host smart-1a7640c8-4755-415d-ac7a-ed9ae1922bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868417897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3868417897
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2575827649
Short name T661
Test name
Test status
Simulation time 117840825 ps
CPU time 0.97 seconds
Started Jul 04 05:02:56 PM PDT 24
Finished Jul 04 05:02:57 PM PDT 24
Peak memory 197216 kb
Host smart-3443b261-b778-42bb-a32c-b62bd08975a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575827649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2575827649
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.884388208
Short name T651
Test name
Test status
Simulation time 70309315 ps
CPU time 3.11 seconds
Started Jul 04 05:02:59 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 198540 kb
Host smart-7c41c930-8fc9-437a-850c-ccabe0db686f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884388208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.884388208
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1378289289
Short name T400
Test name
Test status
Simulation time 258839895 ps
CPU time 1.37 seconds
Started Jul 04 05:03:00 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 197432 kb
Host smart-e48baa18-968c-455b-8e20-0ff1ff957def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378289289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1378289289
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1400792978
Short name T122
Test name
Test status
Simulation time 311644872 ps
CPU time 1.46 seconds
Started Jul 04 05:02:55 PM PDT 24
Finished Jul 04 05:02:56 PM PDT 24
Peak memory 197692 kb
Host smart-4f36f3e7-98a4-43e4-93ec-46fcec765d09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400792978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1400792978
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3068235564
Short name T577
Test name
Test status
Simulation time 5282388509 ps
CPU time 62.92 seconds
Started Jul 04 05:03:00 PM PDT 24
Finished Jul 04 05:04:03 PM PDT 24
Peak memory 198788 kb
Host smart-250d6d84-8f6a-41d0-bc64-d5e5b471fdc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068235564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3068235564
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1329088228
Short name T387
Test name
Test status
Simulation time 88854290151 ps
CPU time 338.74 seconds
Started Jul 04 05:03:00 PM PDT 24
Finished Jul 04 05:08:39 PM PDT 24
Peak memory 206988 kb
Host smart-3fc97a93-f400-4946-b7ef-961fecf99f5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1329088228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1329088228
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1044409563
Short name T391
Test name
Test status
Simulation time 12173076 ps
CPU time 0.59 seconds
Started Jul 04 05:03:05 PM PDT 24
Finished Jul 04 05:03:06 PM PDT 24
Peak memory 194544 kb
Host smart-e54596c3-3479-4fc3-9b7d-40fecb635cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044409563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1044409563
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2534133132
Short name T698
Test name
Test status
Simulation time 223268740 ps
CPU time 0.68 seconds
Started Jul 04 05:02:56 PM PDT 24
Finished Jul 04 05:02:57 PM PDT 24
Peak memory 194628 kb
Host smart-d6c5b8fc-b9d0-4527-ae3b-91bab9f5cbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534133132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2534133132
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.492670890
Short name T683
Test name
Test status
Simulation time 408571770 ps
CPU time 14.15 seconds
Started Jul 04 05:03:03 PM PDT 24
Finished Jul 04 05:03:17 PM PDT 24
Peak memory 197136 kb
Host smart-1ce543ee-4bb2-4677-b8c4-92fb24bd4e39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492670890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.492670890
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.4070012959
Short name T22
Test name
Test status
Simulation time 192779227 ps
CPU time 1.03 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:03:03 PM PDT 24
Peak memory 198296 kb
Host smart-be108ff5-1710-443c-b21c-e19aa7e4b902
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070012959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.4070012959
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3588793257
Short name T641
Test name
Test status
Simulation time 31372797 ps
CPU time 0.92 seconds
Started Jul 04 05:03:03 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 197276 kb
Host smart-1962163d-7a5e-481e-9519-7511078ae699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588793257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3588793257
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1129168277
Short name T631
Test name
Test status
Simulation time 575924743 ps
CPU time 2.28 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 198540 kb
Host smart-e0378e73-cc68-4afa-9271-ac75ecc80e48
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129168277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1129168277
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.600906266
Short name T559
Test name
Test status
Simulation time 315136863 ps
CPU time 1.75 seconds
Started Jul 04 05:03:04 PM PDT 24
Finished Jul 04 05:03:06 PM PDT 24
Peak memory 196596 kb
Host smart-3e96e2a2-ada1-4024-95bc-6027c71135b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600906266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
600906266
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2908827220
Short name T680
Test name
Test status
Simulation time 111689526 ps
CPU time 1.39 seconds
Started Jul 04 05:02:57 PM PDT 24
Finished Jul 04 05:02:58 PM PDT 24
Peak memory 198632 kb
Host smart-1002569d-7d3a-4d3b-84b4-edbd089ec090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908827220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2908827220
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.191112575
Short name T225
Test name
Test status
Simulation time 46235042 ps
CPU time 1.09 seconds
Started Jul 04 05:02:56 PM PDT 24
Finished Jul 04 05:02:58 PM PDT 24
Peak memory 197096 kb
Host smart-837d3e6f-07bb-435a-851b-1b878a178bfe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191112575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.191112575
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_smoke.2316370020
Short name T200
Test name
Test status
Simulation time 248385869 ps
CPU time 1.2 seconds
Started Jul 04 05:02:56 PM PDT 24
Finished Jul 04 05:02:57 PM PDT 24
Peak memory 196356 kb
Host smart-51539562-2d1b-4b55-a43f-c6ebe489dcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316370020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2316370020
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3305003380
Short name T446
Test name
Test status
Simulation time 26882980 ps
CPU time 0.95 seconds
Started Jul 04 05:02:58 PM PDT 24
Finished Jul 04 05:02:59 PM PDT 24
Peak memory 196236 kb
Host smart-517568de-220b-4460-8a6c-8c08c51560c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305003380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3305003380
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.290981886
Short name T131
Test name
Test status
Simulation time 20372702052 ps
CPU time 80.3 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:04:23 PM PDT 24
Peak memory 198696 kb
Host smart-4a3e3eb2-262d-4d5c-8d85-b3cb7159eb03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290981886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.290981886
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2683236549
Short name T237
Test name
Test status
Simulation time 15521191 ps
CPU time 0.6 seconds
Started Jul 04 05:03:03 PM PDT 24
Finished Jul 04 05:03:03 PM PDT 24
Peak memory 194552 kb
Host smart-5f301898-3687-45e5-b92c-8d4e59b8dec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683236549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2683236549
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3999718835
Short name T667
Test name
Test status
Simulation time 64301065 ps
CPU time 0.87 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 195852 kb
Host smart-8a58c46c-f4f5-49c5-8c96-043b3a005d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999718835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3999718835
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2229444680
Short name T590
Test name
Test status
Simulation time 1102197674 ps
CPU time 5.08 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:03:07 PM PDT 24
Peak memory 196260 kb
Host smart-58e8e8c6-1955-4f94-8989-3bed0c253b3a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229444680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2229444680
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.616132414
Short name T331
Test name
Test status
Simulation time 57192746 ps
CPU time 0.74 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 195016 kb
Host smart-6f8d7ab9-d232-4785-98a9-6d145bf040fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616132414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.616132414
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.917980398
Short name T605
Test name
Test status
Simulation time 75328970 ps
CPU time 0.83 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:03:03 PM PDT 24
Peak memory 196180 kb
Host smart-fb1ba832-de8d-4f56-b42d-308719d83372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917980398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.917980398
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.336019974
Short name T210
Test name
Test status
Simulation time 51274682 ps
CPU time 2.07 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 198612 kb
Host smart-4ecd6e53-721d-4e7a-8dc8-6e1049fc99c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336019974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.336019974
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1605802950
Short name T134
Test name
Test status
Simulation time 121975399 ps
CPU time 3.19 seconds
Started Jul 04 05:03:05 PM PDT 24
Finished Jul 04 05:03:09 PM PDT 24
Peak memory 197920 kb
Host smart-86ca59e5-7071-49b4-8af6-5f6358bc6258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605802950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1605802950
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3783257414
Short name T259
Test name
Test status
Simulation time 36101097 ps
CPU time 1.24 seconds
Started Jul 04 05:03:03 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 198640 kb
Host smart-bac3b155-f88e-40c1-bead-f9bf161b49f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783257414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3783257414
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2544034307
Short name T150
Test name
Test status
Simulation time 106469138 ps
CPU time 1.31 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 197676 kb
Host smart-12cfbd6e-b524-4052-b25d-4f4ffa0ff1ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544034307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2544034307
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2505784045
Short name T430
Test name
Test status
Simulation time 163046002 ps
CPU time 1.11 seconds
Started Jul 04 05:03:05 PM PDT 24
Finished Jul 04 05:03:06 PM PDT 24
Peak memory 198280 kb
Host smart-150073bd-350b-4f30-bc94-8aaea35e05d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505784045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2505784045
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1308727418
Short name T404
Test name
Test status
Simulation time 100719998 ps
CPU time 1.61 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:03 PM PDT 24
Peak memory 197296 kb
Host smart-4039233c-6999-4c0a-be7c-3f6e3d0a4a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308727418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1308727418
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3871188276
Short name T365
Test name
Test status
Simulation time 92690030 ps
CPU time 1.53 seconds
Started Jul 04 05:03:05 PM PDT 24
Finished Jul 04 05:03:07 PM PDT 24
Peak memory 196856 kb
Host smart-904c3b55-3803-45c3-9120-d1f0dd16373f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871188276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3871188276
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2210720128
Short name T173
Test name
Test status
Simulation time 5333889076 ps
CPU time 128.44 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:05:10 PM PDT 24
Peak memory 198612 kb
Host smart-e4982f94-5233-4c6d-885b-d95049ccc10b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210720128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2210720128
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.4227871677
Short name T672
Test name
Test status
Simulation time 548690802594 ps
CPU time 2000.51 seconds
Started Jul 04 05:03:05 PM PDT 24
Finished Jul 04 05:36:26 PM PDT 24
Peak memory 198832 kb
Host smart-c2487946-eaef-4c6c-a18d-a4fb7ec65071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4227871677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.4227871677
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.177560919
Short name T46
Test name
Test status
Simulation time 25209161 ps
CPU time 0.58 seconds
Started Jul 04 05:01:25 PM PDT 24
Finished Jul 04 05:01:26 PM PDT 24
Peak memory 195456 kb
Host smart-12dc0bc0-71ab-4877-9e49-40aa6892f822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177560919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.177560919
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4262136101
Short name T127
Test name
Test status
Simulation time 41487266 ps
CPU time 0.89 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:01:24 PM PDT 24
Peak memory 197692 kb
Host smart-f25c8fce-fe5e-4fc2-a77e-de95906e3ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262136101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4262136101
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2264128242
Short name T227
Test name
Test status
Simulation time 295680197 ps
CPU time 15.96 seconds
Started Jul 04 05:01:22 PM PDT 24
Finished Jul 04 05:01:38 PM PDT 24
Peak memory 198524 kb
Host smart-d6102ffb-0e45-437a-af60-d68782e8fbc9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264128242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2264128242
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1164200686
Short name T494
Test name
Test status
Simulation time 77162740 ps
CPU time 1.04 seconds
Started Jul 04 05:01:24 PM PDT 24
Finished Jul 04 05:01:26 PM PDT 24
Peak memory 198448 kb
Host smart-838dba96-5260-43dd-add5-b192144227f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164200686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1164200686
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1703420351
Short name T132
Test name
Test status
Simulation time 286311131 ps
CPU time 1.14 seconds
Started Jul 04 05:01:22 PM PDT 24
Finished Jul 04 05:01:23 PM PDT 24
Peak memory 196660 kb
Host smart-cc309418-1082-4854-ad37-838a311a4142
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703420351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1703420351
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3406146613
Short name T410
Test name
Test status
Simulation time 26544560 ps
CPU time 1.3 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:01:25 PM PDT 24
Peak memory 197468 kb
Host smart-94b3480b-4614-47c2-84cd-919cac395381
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406146613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3406146613
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2997866490
Short name T306
Test name
Test status
Simulation time 254098531 ps
CPU time 2.35 seconds
Started Jul 04 05:01:22 PM PDT 24
Finished Jul 04 05:01:24 PM PDT 24
Peak memory 198536 kb
Host smart-9fecd06e-7116-4bdb-84b7-e8b490ec2886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997866490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2997866490
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2527123941
Short name T612
Test name
Test status
Simulation time 429087910 ps
CPU time 1.07 seconds
Started Jul 04 05:01:24 PM PDT 24
Finished Jul 04 05:01:26 PM PDT 24
Peak memory 196440 kb
Host smart-dacc4cfa-bac9-4215-8d2c-09dce93319de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527123941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2527123941
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.222955939
Short name T710
Test name
Test status
Simulation time 130184594 ps
CPU time 1.31 seconds
Started Jul 04 05:01:21 PM PDT 24
Finished Jul 04 05:01:23 PM PDT 24
Peak memory 197500 kb
Host smart-bc5c2d40-1423-4059-acf4-95d07e43227b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222955939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.222955939
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2643599432
Short name T684
Test name
Test status
Simulation time 263155601 ps
CPU time 3.04 seconds
Started Jul 04 05:01:24 PM PDT 24
Finished Jul 04 05:01:27 PM PDT 24
Peak memory 198624 kb
Host smart-3cb2ab76-6503-48f4-859a-a14d5d63975f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643599432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2643599432
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.877471552
Short name T43
Test name
Test status
Simulation time 263340660 ps
CPU time 0.87 seconds
Started Jul 04 05:01:22 PM PDT 24
Finished Jul 04 05:01:24 PM PDT 24
Peak memory 214180 kb
Host smart-3c378259-3613-4fe5-9a25-65fde850fe6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877471552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.877471552
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2062017863
Short name T452
Test name
Test status
Simulation time 212829862 ps
CPU time 1.13 seconds
Started Jul 04 05:01:24 PM PDT 24
Finished Jul 04 05:01:25 PM PDT 24
Peak memory 196976 kb
Host smart-f9084dcd-1fe2-4472-9130-22280b892b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062017863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2062017863
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.606594076
Short name T422
Test name
Test status
Simulation time 182131860 ps
CPU time 1.36 seconds
Started Jul 04 05:01:26 PM PDT 24
Finished Jul 04 05:01:28 PM PDT 24
Peak memory 196184 kb
Host smart-b59007ae-9fc5-406b-b025-23d6c50b41da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606594076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.606594076
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3411116800
Short name T418
Test name
Test status
Simulation time 2423313011 ps
CPU time 66.94 seconds
Started Jul 04 05:01:24 PM PDT 24
Finished Jul 04 05:02:31 PM PDT 24
Peak memory 198652 kb
Host smart-197d16ec-8a4c-478d-8a3a-74fbd43ccaeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411116800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3411116800
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.164926275
Short name T517
Test name
Test status
Simulation time 35225978 ps
CPU time 0.57 seconds
Started Jul 04 05:03:09 PM PDT 24
Finished Jul 04 05:03:09 PM PDT 24
Peak memory 194608 kb
Host smart-c879f1a7-8615-4f3a-bb70-6ef198c8113d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164926275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.164926275
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1978149840
Short name T719
Test name
Test status
Simulation time 99027313 ps
CPU time 0.71 seconds
Started Jul 04 05:03:01 PM PDT 24
Finished Jul 04 05:03:02 PM PDT 24
Peak memory 195412 kb
Host smart-67e51480-2018-4f33-8e5d-be034e8a471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978149840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1978149840
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1355957905
Short name T157
Test name
Test status
Simulation time 466436863 ps
CPU time 23.55 seconds
Started Jul 04 05:03:05 PM PDT 24
Finished Jul 04 05:03:29 PM PDT 24
Peak memory 197460 kb
Host smart-40eba77b-2a6b-4160-a8b2-74c3ec01617b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355957905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1355957905
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1063402861
Short name T561
Test name
Test status
Simulation time 65528480 ps
CPU time 0.59 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:03:03 PM PDT 24
Peak memory 195380 kb
Host smart-26c0076b-2a78-49d1-8b44-5805eef07f45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063402861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1063402861
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.804738943
Short name T65
Test name
Test status
Simulation time 75245946 ps
CPU time 1.38 seconds
Started Jul 04 05:03:02 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 197468 kb
Host smart-83ba44d2-f625-4bee-8762-795a29c3c11e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804738943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.804738943
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3626057165
Short name T190
Test name
Test status
Simulation time 174155208 ps
CPU time 1.68 seconds
Started Jul 04 05:03:03 PM PDT 24
Finished Jul 04 05:03:05 PM PDT 24
Peak memory 198560 kb
Host smart-0b84beb5-67ce-4841-8219-378f2c217c19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626057165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3626057165
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3752365656
Short name T189
Test name
Test status
Simulation time 672413967 ps
CPU time 3.46 seconds
Started Jul 04 05:03:05 PM PDT 24
Finished Jul 04 05:03:09 PM PDT 24
Peak memory 196380 kb
Host smart-23cfb90e-6e86-484d-ad22-cbd111508b14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752365656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3752365656
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1419869952
Short name T501
Test name
Test status
Simulation time 61762397 ps
CPU time 0.72 seconds
Started Jul 04 05:03:03 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 196652 kb
Host smart-5cf2d22d-4a15-4d0e-acea-343ac9e77482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419869952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1419869952
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.539732126
Short name T524
Test name
Test status
Simulation time 38213002 ps
CPU time 0.84 seconds
Started Jul 04 05:03:03 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 196076 kb
Host smart-26428ab5-c725-4a06-add5-0e6751292296
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539732126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.539732126
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3636630946
Short name T270
Test name
Test status
Simulation time 104908141 ps
CPU time 2.96 seconds
Started Jul 04 05:03:00 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 198540 kb
Host smart-bb6ac6b1-4d9c-4b25-909a-0014a923535e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636630946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3636630946
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2698221682
Short name T179
Test name
Test status
Simulation time 52707622 ps
CPU time 1.44 seconds
Started Jul 04 05:03:06 PM PDT 24
Finished Jul 04 05:03:07 PM PDT 24
Peak memory 197360 kb
Host smart-91993de4-ecde-467e-bda3-facf59905175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698221682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2698221682
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.12737004
Short name T722
Test name
Test status
Simulation time 36916799 ps
CPU time 1 seconds
Started Jul 04 05:03:04 PM PDT 24
Finished Jul 04 05:03:05 PM PDT 24
Peak memory 196288 kb
Host smart-6042b550-835e-4ba4-a5ab-94db4cfa295a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12737004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.12737004
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2067866966
Short name T604
Test name
Test status
Simulation time 12250882648 ps
CPU time 171.81 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:06:04 PM PDT 24
Peak memory 198640 kb
Host smart-261b7f54-7fde-4a5e-bc87-ad906a0d06b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067866966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2067866966
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.85517936
Short name T316
Test name
Test status
Simulation time 17674513 ps
CPU time 0.57 seconds
Started Jul 04 05:03:09 PM PDT 24
Finished Jul 04 05:03:10 PM PDT 24
Peak memory 194640 kb
Host smart-12f3f600-e2c9-4830-b147-4f6850d19d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85517936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.85517936
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.976974081
Short name T608
Test name
Test status
Simulation time 79408234 ps
CPU time 0.66 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:13 PM PDT 24
Peak memory 194076 kb
Host smart-9ed97059-3094-4e7f-b9d1-3bbb8f26daa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976974081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.976974081
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3862786495
Short name T626
Test name
Test status
Simulation time 1333319643 ps
CPU time 12.92 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:25 PM PDT 24
Peak memory 197304 kb
Host smart-94ce0268-26ae-4605-8ef6-dc34a284c531
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862786495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3862786495
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2764622073
Short name T313
Test name
Test status
Simulation time 52135847 ps
CPU time 0.78 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:11 PM PDT 24
Peak memory 196384 kb
Host smart-eaed9a57-3840-4002-bca6-58972b0d0c21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764622073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2764622073
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.32954788
Short name T589
Test name
Test status
Simulation time 130846727 ps
CPU time 1.2 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 197504 kb
Host smart-83cdfb29-0bde-436a-87bd-95c59c927b62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32954788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.32954788
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1602494521
Short name T677
Test name
Test status
Simulation time 181121740 ps
CPU time 2.84 seconds
Started Jul 04 05:03:09 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 197116 kb
Host smart-f28179a4-b4ab-466c-a73d-2f44015f4af9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602494521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1602494521
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2984588456
Short name T666
Test name
Test status
Simulation time 240382181 ps
CPU time 2.7 seconds
Started Jul 04 05:03:13 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 197728 kb
Host smart-9823b2cf-4656-41ad-97bc-678afc467f72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984588456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2984588456
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2828366007
Short name T622
Test name
Test status
Simulation time 50117244 ps
CPU time 1.03 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:14 PM PDT 24
Peak memory 196432 kb
Host smart-aea5545a-92b6-4884-a6ca-b0c31f2a94e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828366007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2828366007
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1289616664
Short name T343
Test name
Test status
Simulation time 165899955 ps
CPU time 1.03 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 196892 kb
Host smart-c89569b8-ce7d-4fff-8cd4-77e8a3122a2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289616664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1289616664
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4042889536
Short name T662
Test name
Test status
Simulation time 516646385 ps
CPU time 5.49 seconds
Started Jul 04 05:03:14 PM PDT 24
Finished Jul 04 05:03:20 PM PDT 24
Peak memory 198288 kb
Host smart-42d7bf6a-fc62-4042-9329-f483d5132561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042889536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.4042889536
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.802715886
Short name T445
Test name
Test status
Simulation time 38551178 ps
CPU time 1.16 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:14 PM PDT 24
Peak memory 196084 kb
Host smart-fe12a383-5be3-4464-bea0-cda8db7cd867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802715886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.802715886
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1104589206
Short name T512
Test name
Test status
Simulation time 206460224 ps
CPU time 1.38 seconds
Started Jul 04 05:03:11 PM PDT 24
Finished Jul 04 05:03:13 PM PDT 24
Peak memory 196072 kb
Host smart-c0f53ffb-2386-4539-be92-0addd5348d71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104589206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1104589206
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.4132284125
Short name T18
Test name
Test status
Simulation time 8864108035 ps
CPU time 57.75 seconds
Started Jul 04 05:03:13 PM PDT 24
Finished Jul 04 05:04:11 PM PDT 24
Peak memory 198600 kb
Host smart-ccd85a25-a53e-464a-9574-11f4d05994c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132284125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.4132284125
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.4020771616
Short name T485
Test name
Test status
Simulation time 33606934166 ps
CPU time 397.34 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:09:48 PM PDT 24
Peak memory 198820 kb
Host smart-2296cd58-a5ed-491b-86ef-fec0d455d05d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4020771616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.4020771616
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3798377307
Short name T447
Test name
Test status
Simulation time 35292279 ps
CPU time 0.54 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:13 PM PDT 24
Peak memory 194032 kb
Host smart-559e7d78-d11a-40ed-9966-13449f5cac90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798377307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3798377307
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.27971447
Short name T359
Test name
Test status
Simulation time 57430871 ps
CPU time 0.81 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:14 PM PDT 24
Peak memory 195860 kb
Host smart-0c837588-46a4-4128-a88e-98d0edda38ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27971447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.27971447
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2633885670
Short name T386
Test name
Test status
Simulation time 1072048324 ps
CPU time 14.29 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 198664 kb
Host smart-18e2d796-021b-4404-bec9-e074c19812a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633885670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2633885670
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.840758269
Short name T582
Test name
Test status
Simulation time 105223886 ps
CPU time 0.82 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 196460 kb
Host smart-1f5c7f85-fa0d-481d-bb67-d0d768f924a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840758269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.840758269
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3158201031
Short name T401
Test name
Test status
Simulation time 37219132 ps
CPU time 0.78 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:11 PM PDT 24
Peak memory 196860 kb
Host smart-834a7b50-baf4-45f9-9840-59ae369508ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158201031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3158201031
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3752873371
Short name T207
Test name
Test status
Simulation time 87376155 ps
CPU time 3.64 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 198724 kb
Host smart-e8a4dcc7-22e3-4d28-acd5-149f7585522d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752873371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3752873371
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.4041743243
Short name T366
Test name
Test status
Simulation time 504889704 ps
CPU time 2.57 seconds
Started Jul 04 05:03:11 PM PDT 24
Finished Jul 04 05:03:14 PM PDT 24
Peak memory 197676 kb
Host smart-166f8b41-6ca8-4e5a-9310-7029598b0531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041743243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.4041743243
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.501700434
Short name T554
Test name
Test status
Simulation time 142418826 ps
CPU time 1.03 seconds
Started Jul 04 05:03:11 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 196496 kb
Host smart-4cb16a4a-7260-4e7d-b9bc-3336d38a9f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501700434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.501700434
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2527835234
Short name T500
Test name
Test status
Simulation time 23344915 ps
CPU time 0.62 seconds
Started Jul 04 05:03:08 PM PDT 24
Finished Jul 04 05:03:08 PM PDT 24
Peak memory 194696 kb
Host smart-c479a7e8-f500-4f05-9aff-045a2b75ba22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527835234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2527835234
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3058344470
Short name T327
Test name
Test status
Simulation time 452217613 ps
CPU time 3.69 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 198544 kb
Host smart-49e3e66d-1dd9-4abe-9479-f224b8137f90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058344470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3058344470
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2435740083
Short name T201
Test name
Test status
Simulation time 54837980 ps
CPU time 1.22 seconds
Started Jul 04 05:03:09 PM PDT 24
Finished Jul 04 05:03:10 PM PDT 24
Peak memory 196300 kb
Host smart-f39c6395-b744-47ce-b627-d1158af75b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435740083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2435740083
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2320899284
Short name T204
Test name
Test status
Simulation time 47112093 ps
CPU time 0.79 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 195792 kb
Host smart-2972dfbf-f90b-4389-b2a4-3451cdfd9806
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320899284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2320899284
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.181930815
Short name T504
Test name
Test status
Simulation time 13640914769 ps
CPU time 165.89 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:05:58 PM PDT 24
Peak memory 198636 kb
Host smart-6b3c7e0d-dfd0-47b1-9ebb-efa22fafb8fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181930815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.181930815
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3283961474
Short name T487
Test name
Test status
Simulation time 18387987 ps
CPU time 0.56 seconds
Started Jul 04 05:03:13 PM PDT 24
Finished Jul 04 05:03:14 PM PDT 24
Peak memory 194568 kb
Host smart-be886786-c868-4c51-b608-d9957d6a6648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283961474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3283961474
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3626678837
Short name T226
Test name
Test status
Simulation time 55520060 ps
CPU time 0.64 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:11 PM PDT 24
Peak memory 194612 kb
Host smart-e1fdca52-f661-44ed-8093-e1b39f4c1024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626678837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3626678837
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3058900726
Short name T66
Test name
Test status
Simulation time 438339431 ps
CPU time 23.2 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:34 PM PDT 24
Peak memory 198552 kb
Host smart-f646f66f-b93b-4026-afac-a6ea54ac8233
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058900726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3058900726
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1425176293
Short name T392
Test name
Test status
Simulation time 840405788 ps
CPU time 1.13 seconds
Started Jul 04 05:03:14 PM PDT 24
Finished Jul 04 05:03:15 PM PDT 24
Peak memory 197144 kb
Host smart-6dd177da-59a0-436f-ba37-9a47f3766d34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425176293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1425176293
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3575047197
Short name T511
Test name
Test status
Simulation time 99565251 ps
CPU time 0.96 seconds
Started Jul 04 05:03:11 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 196352 kb
Host smart-2083c2d9-ee9c-42fb-8b7e-4112fdf4d6ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575047197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3575047197
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2007202211
Short name T348
Test name
Test status
Simulation time 171246976 ps
CPU time 3.51 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:13 PM PDT 24
Peak memory 198612 kb
Host smart-87017835-df69-4d22-a871-ec531cad6ead
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007202211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2007202211
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.998052104
Short name T611
Test name
Test status
Simulation time 553869639 ps
CPU time 4.16 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 197688 kb
Host smart-bb23be39-c5f6-4279-a9e8-3ca63e9fab09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998052104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
998052104
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1973918008
Short name T299
Test name
Test status
Simulation time 203746321 ps
CPU time 1.38 seconds
Started Jul 04 05:03:14 PM PDT 24
Finished Jul 04 05:03:15 PM PDT 24
Peak memory 197488 kb
Host smart-66e51c85-0abc-4038-b8fb-9e95bed01ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973918008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1973918008
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.781515760
Short name T139
Test name
Test status
Simulation time 36230426 ps
CPU time 0.71 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:11 PM PDT 24
Peak memory 195580 kb
Host smart-2370021e-6107-4654-bf46-943de4df8dc5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781515760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.781515760
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3396022926
Short name T584
Test name
Test status
Simulation time 271184043 ps
CPU time 2.86 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:15 PM PDT 24
Peak memory 198576 kb
Host smart-cd7bef26-722d-4ad9-bd7d-11607bd5b06e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396022926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3396022926
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2525781111
Short name T629
Test name
Test status
Simulation time 228516945 ps
CPU time 1 seconds
Started Jul 04 05:03:11 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 196388 kb
Host smart-0da0936e-4497-46eb-942f-36c9f03dd332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525781111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2525781111
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.507239302
Short name T581
Test name
Test status
Simulation time 225101528 ps
CPU time 1.17 seconds
Started Jul 04 05:03:11 PM PDT 24
Finished Jul 04 05:03:13 PM PDT 24
Peak memory 196180 kb
Host smart-6c5398c3-9c01-48ef-be6e-394146a4a1c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507239302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.507239302
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2301060621
Short name T656
Test name
Test status
Simulation time 18217159690 ps
CPU time 103.64 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:04:53 PM PDT 24
Peak memory 198692 kb
Host smart-18f6bd88-41af-4429-96cd-7e0747c5fe8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301060621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2301060621
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1511915122
Short name T45
Test name
Test status
Simulation time 14982673 ps
CPU time 0.59 seconds
Started Jul 04 05:03:16 PM PDT 24
Finished Jul 04 05:03:17 PM PDT 24
Peak memory 194848 kb
Host smart-e7ccac2b-2fb3-4817-83a3-a0ee41741b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511915122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1511915122
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1342032470
Short name T468
Test name
Test status
Simulation time 25938567 ps
CPU time 0.76 seconds
Started Jul 04 05:03:11 PM PDT 24
Finished Jul 04 05:03:13 PM PDT 24
Peak memory 194724 kb
Host smart-7ba64067-24d0-4fd9-9e1e-471e646dbd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342032470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1342032470
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.635433272
Short name T585
Test name
Test status
Simulation time 1913323267 ps
CPU time 26.41 seconds
Started Jul 04 05:03:21 PM PDT 24
Finished Jul 04 05:03:47 PM PDT 24
Peak memory 198560 kb
Host smart-5513c5b4-c4c0-4431-a794-09879a72c040
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635433272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.635433272
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2977780739
Short name T471
Test name
Test status
Simulation time 88915126 ps
CPU time 0.93 seconds
Started Jul 04 05:03:17 PM PDT 24
Finished Jul 04 05:03:18 PM PDT 24
Peak memory 197784 kb
Host smart-f8f00a25-6dc9-4054-b24c-3fa7c5a510ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977780739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2977780739
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1102177149
Short name T235
Test name
Test status
Simulation time 321830679 ps
CPU time 1.23 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:14 PM PDT 24
Peak memory 196456 kb
Host smart-c63c4a46-4f53-4d32-94aa-884c338d1a72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102177149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1102177149
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.614468902
Short name T181
Test name
Test status
Simulation time 149229094 ps
CPU time 3.18 seconds
Started Jul 04 05:03:11 PM PDT 24
Finished Jul 04 05:03:15 PM PDT 24
Peak memory 198624 kb
Host smart-1368be7b-6509-4cec-8fd4-57f60a35a927
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614468902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.614468902
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3891614009
Short name T368
Test name
Test status
Simulation time 141457300 ps
CPU time 1.88 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 197212 kb
Host smart-07a818ba-c665-4d4e-8063-395eaee8bbea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891614009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3891614009
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4029204861
Short name T253
Test name
Test status
Simulation time 34265931 ps
CPU time 1.27 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 197528 kb
Host smart-79da0b63-89ca-4ceb-960c-fe4b233fd050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029204861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4029204861
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4166245903
Short name T158
Test name
Test status
Simulation time 35160586 ps
CPU time 0.84 seconds
Started Jul 04 05:03:12 PM PDT 24
Finished Jul 04 05:03:14 PM PDT 24
Peak memory 195480 kb
Host smart-43a4d030-f94f-4f8a-b9d7-8edd6020296c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166245903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4166245903
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3423239995
Short name T372
Test name
Test status
Simulation time 254439349 ps
CPU time 1.23 seconds
Started Jul 04 05:03:14 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 198532 kb
Host smart-aac90103-e296-4108-a42c-48a68c514016
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423239995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3423239995
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.166564751
Short name T335
Test name
Test status
Simulation time 400005840 ps
CPU time 1.04 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 196220 kb
Host smart-fb19457b-76a3-4bb7-8ab4-88b0b5c89d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166564751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.166564751
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.621879464
Short name T534
Test name
Test status
Simulation time 74334088 ps
CPU time 1.21 seconds
Started Jul 04 05:03:10 PM PDT 24
Finished Jul 04 05:03:12 PM PDT 24
Peak memory 196372 kb
Host smart-bc59ca6f-29bc-4af9-b2c9-30aa22767aee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621879464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.621879464
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.755420180
Short name T502
Test name
Test status
Simulation time 26688688283 ps
CPU time 171.89 seconds
Started Jul 04 05:03:15 PM PDT 24
Finished Jul 04 05:06:07 PM PDT 24
Peak memory 198688 kb
Host smart-8687b3c4-47eb-4ea8-a5e3-f623f3f0c6bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755420180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.755420180
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.576457033
Short name T187
Test name
Test status
Simulation time 125770221 ps
CPU time 0.59 seconds
Started Jul 04 05:03:15 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 194524 kb
Host smart-604dceec-b379-45e9-9e67-1858836eaae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576457033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.576457033
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3478546143
Short name T705
Test name
Test status
Simulation time 76143276 ps
CPU time 0.74 seconds
Started Jul 04 05:03:20 PM PDT 24
Finished Jul 04 05:03:21 PM PDT 24
Peak memory 195880 kb
Host smart-b9a3cfbd-0d39-467c-b693-1fd09fb9a4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478546143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3478546143
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2189589652
Short name T615
Test name
Test status
Simulation time 1733586567 ps
CPU time 16.54 seconds
Started Jul 04 05:03:16 PM PDT 24
Finished Jul 04 05:03:32 PM PDT 24
Peak memory 196068 kb
Host smart-5a4638a7-8db0-4250-b8b7-9c632ccf39fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189589652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2189589652
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2157995556
Short name T435
Test name
Test status
Simulation time 26758298 ps
CPU time 0.6 seconds
Started Jul 04 05:03:21 PM PDT 24
Finished Jul 04 05:03:22 PM PDT 24
Peak memory 194816 kb
Host smart-e6f8aad6-e1ca-4a56-bc2b-bd1c840e7ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157995556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2157995556
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.941961383
Short name T282
Test name
Test status
Simulation time 211353366 ps
CPU time 1.11 seconds
Started Jul 04 05:03:14 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 197264 kb
Host smart-41f88d54-375d-400b-8620-a4ee1489db08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941961383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.941961383
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2775951761
Short name T264
Test name
Test status
Simulation time 174579922 ps
CPU time 2.15 seconds
Started Jul 04 05:03:21 PM PDT 24
Finished Jul 04 05:03:23 PM PDT 24
Peak memory 198676 kb
Host smart-6f4154ef-eef4-4ed5-81c1-2df073a7d452
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775951761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2775951761
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2853127249
Short name T239
Test name
Test status
Simulation time 57029274 ps
CPU time 1.11 seconds
Started Jul 04 05:03:19 PM PDT 24
Finished Jul 04 05:03:21 PM PDT 24
Peak memory 197032 kb
Host smart-7f0c52d2-d4a7-4724-9701-c2ba5b7ab46d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853127249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2853127249
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3615747164
Short name T535
Test name
Test status
Simulation time 50319483 ps
CPU time 0.99 seconds
Started Jul 04 05:03:19 PM PDT 24
Finished Jul 04 05:03:20 PM PDT 24
Peak memory 196544 kb
Host smart-053c1a8f-9ae0-4b99-8304-3648ce3b277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615747164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3615747164
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1841525575
Short name T293
Test name
Test status
Simulation time 32067099 ps
CPU time 1.29 seconds
Started Jul 04 05:03:14 PM PDT 24
Finished Jul 04 05:03:15 PM PDT 24
Peak memory 197432 kb
Host smart-f2acfdc4-6966-46a4-b681-063b0031e7ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841525575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1841525575
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1071089244
Short name T60
Test name
Test status
Simulation time 25237674 ps
CPU time 1.18 seconds
Started Jul 04 05:03:14 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 198552 kb
Host smart-ac37dd78-4da6-49e3-b62f-8e201a6f74d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071089244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1071089244
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2044533636
Short name T601
Test name
Test status
Simulation time 40078549 ps
CPU time 1.28 seconds
Started Jul 04 05:03:20 PM PDT 24
Finished Jul 04 05:03:22 PM PDT 24
Peak memory 196992 kb
Host smart-d7ff7cb5-c4a7-4099-82c4-7cc7b85eda19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044533636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2044533636
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1623873327
Short name T194
Test name
Test status
Simulation time 208307248 ps
CPU time 1.11 seconds
Started Jul 04 05:03:17 PM PDT 24
Finished Jul 04 05:03:19 PM PDT 24
Peak memory 196156 kb
Host smart-256de5c9-6ab8-4af5-a9fb-941c5dbfd1fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623873327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1623873327
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1722409988
Short name T654
Test name
Test status
Simulation time 18115421675 ps
CPU time 117.22 seconds
Started Jul 04 05:03:18 PM PDT 24
Finished Jul 04 05:05:15 PM PDT 24
Peak memory 198780 kb
Host smart-837aa34d-ad95-4054-852e-f97ce36a73f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722409988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1722409988
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.229871552
Short name T458
Test name
Test status
Simulation time 45800200 ps
CPU time 0.6 seconds
Started Jul 04 05:03:16 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 194556 kb
Host smart-1c0fd971-f879-4da0-98b7-c316dd8d748c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229871552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.229871552
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2048105603
Short name T600
Test name
Test status
Simulation time 14982330 ps
CPU time 0.62 seconds
Started Jul 04 05:03:18 PM PDT 24
Finished Jul 04 05:03:19 PM PDT 24
Peak memory 194428 kb
Host smart-baf3b488-0214-43f9-9e72-1a8b35333395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048105603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2048105603
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3222013378
Short name T218
Test name
Test status
Simulation time 2002994025 ps
CPU time 17.83 seconds
Started Jul 04 05:03:19 PM PDT 24
Finished Jul 04 05:03:37 PM PDT 24
Peak memory 197236 kb
Host smart-ec54cc1c-ed3f-4c75-bc1a-373212ac04aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222013378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3222013378
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3426468055
Short name T215
Test name
Test status
Simulation time 57412223 ps
CPU time 0.92 seconds
Started Jul 04 05:03:18 PM PDT 24
Finished Jul 04 05:03:19 PM PDT 24
Peak memory 197348 kb
Host smart-4985d92f-8705-48f4-936f-528559da02ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426468055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3426468055
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2905408578
Short name T625
Test name
Test status
Simulation time 129969710 ps
CPU time 0.87 seconds
Started Jul 04 05:03:15 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 196432 kb
Host smart-4a4c327d-38c5-46a6-b706-e4e735cec24b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905408578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2905408578
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2035889429
Short name T186
Test name
Test status
Simulation time 344217789 ps
CPU time 3.64 seconds
Started Jul 04 05:03:16 PM PDT 24
Finished Jul 04 05:03:19 PM PDT 24
Peak memory 198648 kb
Host smart-bbd0144c-c50b-4dc6-b8cc-3d61c3dae86c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035889429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2035889429
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.494891664
Short name T332
Test name
Test status
Simulation time 336797777 ps
CPU time 2.44 seconds
Started Jul 04 05:03:19 PM PDT 24
Finished Jul 04 05:03:22 PM PDT 24
Peak memory 197452 kb
Host smart-65404e1a-9857-41d5-9975-2344d84a65b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494891664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
494891664
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3203167545
Short name T675
Test name
Test status
Simulation time 48946886 ps
CPU time 0.69 seconds
Started Jul 04 05:03:19 PM PDT 24
Finished Jul 04 05:03:20 PM PDT 24
Peak memory 195492 kb
Host smart-6f2260d0-4ce2-4d9f-a0d3-014dc979f7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203167545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3203167545
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2653747549
Short name T13
Test name
Test status
Simulation time 516238572 ps
CPU time 1.06 seconds
Started Jul 04 05:03:19 PM PDT 24
Finished Jul 04 05:03:20 PM PDT 24
Peak memory 196656 kb
Host smart-af8d4d40-aedf-4f08-b1a1-6856651cf36d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653747549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2653747549
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2557977482
Short name T156
Test name
Test status
Simulation time 1682608866 ps
CPU time 4.65 seconds
Started Jul 04 05:03:20 PM PDT 24
Finished Jul 04 05:03:25 PM PDT 24
Peak memory 198524 kb
Host smart-fee5610f-11d4-463b-b1ff-929c2aecd652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557977482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2557977482
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3121184060
Short name T474
Test name
Test status
Simulation time 107630488 ps
CPU time 0.87 seconds
Started Jul 04 05:03:15 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 196844 kb
Host smart-b59ad05b-42f7-4072-a01c-5e6c14cb660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121184060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3121184060
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.969686255
Short name T142
Test name
Test status
Simulation time 82287616 ps
CPU time 1.32 seconds
Started Jul 04 05:03:21 PM PDT 24
Finished Jul 04 05:03:22 PM PDT 24
Peak memory 197364 kb
Host smart-5a1e262f-3467-46fa-bf5d-b9bb38bba592
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969686255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.969686255
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.111960284
Short name T595
Test name
Test status
Simulation time 6903832344 ps
CPU time 178.39 seconds
Started Jul 04 05:03:18 PM PDT 24
Finished Jul 04 05:06:17 PM PDT 24
Peak memory 198716 kb
Host smart-a3760c0f-5e66-4364-bc4a-176aebbed2d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111960284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.111960284
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2033905292
Short name T609
Test name
Test status
Simulation time 88898488923 ps
CPU time 1815.56 seconds
Started Jul 04 05:03:18 PM PDT 24
Finished Jul 04 05:33:34 PM PDT 24
Peak memory 198820 kb
Host smart-19c79925-4d6a-4c7a-8b0d-1219490ec44e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2033905292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2033905292
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2684765076
Short name T425
Test name
Test status
Simulation time 19016519 ps
CPU time 0.62 seconds
Started Jul 04 05:03:26 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 194708 kb
Host smart-c0113f31-4d67-4eb4-87ad-582bdfa9257b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684765076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2684765076
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1342643790
Short name T398
Test name
Test status
Simulation time 294692426 ps
CPU time 0.9 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:26 PM PDT 24
Peak memory 197820 kb
Host smart-021d307b-adc5-4171-9e7c-d39f97186860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342643790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1342643790
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3306208923
Short name T329
Test name
Test status
Simulation time 1339489028 ps
CPU time 19.55 seconds
Started Jul 04 05:03:26 PM PDT 24
Finished Jul 04 05:03:46 PM PDT 24
Peak memory 196064 kb
Host smart-4aad87f9-d322-4f37-8272-d950b83bd304
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306208923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3306208923
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.244645312
Short name T304
Test name
Test status
Simulation time 39804510 ps
CPU time 0.71 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:03:26 PM PDT 24
Peak memory 195892 kb
Host smart-4605c78f-25f8-426a-ae5d-4d8076cec51b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244645312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.244645312
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1448490033
Short name T397
Test name
Test status
Simulation time 33029414 ps
CPU time 0.87 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:26 PM PDT 24
Peak memory 196060 kb
Host smart-62d5d65c-66c0-416b-ba65-b438317bb708
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448490033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1448490033
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1606167251
Short name T660
Test name
Test status
Simulation time 511357844 ps
CPU time 3.05 seconds
Started Jul 04 05:03:23 PM PDT 24
Finished Jul 04 05:03:26 PM PDT 24
Peak memory 198580 kb
Host smart-a0bdc1e8-63a8-4251-886d-a7bcb4148197
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606167251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1606167251
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3833089165
Short name T384
Test name
Test status
Simulation time 820446558 ps
CPU time 2.99 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 197028 kb
Host smart-2bdd9d59-0099-4cd3-899c-edd7d530f6ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833089165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3833089165
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2742588565
Short name T249
Test name
Test status
Simulation time 62315618 ps
CPU time 1.24 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 197388 kb
Host smart-235232be-713c-43fb-8acd-28720bf38fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742588565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2742588565
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2191420674
Short name T441
Test name
Test status
Simulation time 27605445 ps
CPU time 1.17 seconds
Started Jul 04 05:03:23 PM PDT 24
Finished Jul 04 05:03:25 PM PDT 24
Peak memory 197240 kb
Host smart-aeb28ce7-f857-48ee-85b9-d1c7d78122da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191420674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2191420674
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.935572038
Short name T196
Test name
Test status
Simulation time 83976996 ps
CPU time 3.97 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:03:28 PM PDT 24
Peak memory 198512 kb
Host smart-45e6fb5b-2441-4a7b-9599-d34ef3969e83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935572038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.935572038
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2498201864
Short name T330
Test name
Test status
Simulation time 322564114 ps
CPU time 0.91 seconds
Started Jul 04 05:03:14 PM PDT 24
Finished Jul 04 05:03:15 PM PDT 24
Peak memory 196836 kb
Host smart-9448ab20-e688-4a27-9a8c-0bfc5024db71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498201864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2498201864
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2023227803
Short name T137
Test name
Test status
Simulation time 535717324 ps
CPU time 1.07 seconds
Started Jul 04 05:03:15 PM PDT 24
Finished Jul 04 05:03:16 PM PDT 24
Peak memory 196108 kb
Host smart-73601d6f-7ca7-471c-bc0a-973a074e66ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023227803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2023227803
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.789124323
Short name T10
Test name
Test status
Simulation time 6241362236 ps
CPU time 77.16 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:04:41 PM PDT 24
Peak memory 198792 kb
Host smart-609fcaea-8252-488f-9c8a-0d07d7489b11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789124323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.789124323
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2600218439
Short name T70
Test name
Test status
Simulation time 441272983860 ps
CPU time 2047.92 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:37:33 PM PDT 24
Peak memory 198832 kb
Host smart-cf58b4a3-fb65-4963-a5c6-02e98fd148fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2600218439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2600218439
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3242617611
Short name T159
Test name
Test status
Simulation time 74079891 ps
CPU time 0.61 seconds
Started Jul 04 05:03:23 PM PDT 24
Finished Jul 04 05:03:24 PM PDT 24
Peak memory 194540 kb
Host smart-4a7eac44-2fd8-495a-9efd-a7607b11664b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242617611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3242617611
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.886115357
Short name T175
Test name
Test status
Simulation time 37279808 ps
CPU time 0.65 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:03:25 PM PDT 24
Peak memory 195212 kb
Host smart-8d216e92-9b04-4b94-9633-7bd6481d3e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886115357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.886115357
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3436492548
Short name T444
Test name
Test status
Simulation time 143978336 ps
CPU time 5.1 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:03:30 PM PDT 24
Peak memory 197844 kb
Host smart-7c98b20d-d34a-48f1-9883-ed933e24d1fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436492548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3436492548
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.650154349
Short name T16
Test name
Test status
Simulation time 99249037 ps
CPU time 1.02 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 198144 kb
Host smart-07be435e-8a10-4966-a3a6-462224b53d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650154349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.650154349
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.161156227
Short name T155
Test name
Test status
Simulation time 79243996 ps
CPU time 1.25 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 197448 kb
Host smart-8c7ce35a-ca30-4156-b265-9eb8ae1bea20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161156227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.161156227
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1203639005
Short name T160
Test name
Test status
Simulation time 260757964 ps
CPU time 2.78 seconds
Started Jul 04 05:03:23 PM PDT 24
Finished Jul 04 05:03:26 PM PDT 24
Peak memory 198676 kb
Host smart-10a4d685-5a05-4f3b-9540-5abf35fe5723
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203639005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1203639005
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3567180696
Short name T344
Test name
Test status
Simulation time 844043768 ps
CPU time 3.52 seconds
Started Jul 04 05:03:23 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 197632 kb
Host smart-623df586-1b9d-4dd2-a586-2403a798972a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567180696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3567180696
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1600319406
Short name T682
Test name
Test status
Simulation time 205860274 ps
CPU time 1.3 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 197664 kb
Host smart-4a6467ac-0ee5-472e-bbfc-200beb595abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600319406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1600319406
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2647603603
Short name T469
Test name
Test status
Simulation time 52129207 ps
CPU time 0.95 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 197060 kb
Host smart-f6fd14fe-29ed-44dd-bfff-9e0cba4074b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647603603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2647603603
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1269312711
Short name T466
Test name
Test status
Simulation time 2937208327 ps
CPU time 3.13 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:28 PM PDT 24
Peak memory 198612 kb
Host smart-e5d9ac26-bc78-4b71-9191-033b0beec2a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269312711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1269312711
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3251908761
Short name T461
Test name
Test status
Simulation time 47288533 ps
CPU time 1.1 seconds
Started Jul 04 05:03:26 PM PDT 24
Finished Jul 04 05:03:28 PM PDT 24
Peak memory 196096 kb
Host smart-830d956b-7163-412e-a3d5-c1a6cf660575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251908761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3251908761
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2256907330
Short name T545
Test name
Test status
Simulation time 191030057 ps
CPU time 0.96 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:26 PM PDT 24
Peak memory 196424 kb
Host smart-f512f295-7d9b-439e-bb73-c6b360c04750
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256907330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2256907330
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1528491652
Short name T665
Test name
Test status
Simulation time 7773427739 ps
CPU time 104.74 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:05:11 PM PDT 24
Peak memory 198692 kb
Host smart-02639641-570a-46bf-802a-fb241895a500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528491652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1528491652
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1006049159
Short name T703
Test name
Test status
Simulation time 337439759685 ps
CPU time 689.19 seconds
Started Jul 04 05:03:26 PM PDT 24
Finished Jul 04 05:14:56 PM PDT 24
Peak memory 207048 kb
Host smart-1d29c473-6cc8-463f-8b3a-ca98ca0c2843
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1006049159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1006049159
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3824575900
Short name T224
Test name
Test status
Simulation time 34875562 ps
CPU time 0.56 seconds
Started Jul 04 05:03:31 PM PDT 24
Finished Jul 04 05:03:32 PM PDT 24
Peak memory 194640 kb
Host smart-5231b766-86c4-450c-9915-44669a6063c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824575900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3824575900
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3969889271
Short name T363
Test name
Test status
Simulation time 57231110 ps
CPU time 0.94 seconds
Started Jul 04 05:03:29 PM PDT 24
Finished Jul 04 05:03:30 PM PDT 24
Peak memory 196224 kb
Host smart-b9339a51-361b-4f96-856d-b1f2da7f9193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969889271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3969889271
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2269735530
Short name T165
Test name
Test status
Simulation time 172763630 ps
CPU time 6.23 seconds
Started Jul 04 05:03:32 PM PDT 24
Finished Jul 04 05:03:38 PM PDT 24
Peak memory 196196 kb
Host smart-80a85bbb-e28a-4b22-b78f-014f391f7770
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269735530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2269735530
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.4073255707
Short name T351
Test name
Test status
Simulation time 90473304 ps
CPU time 0.8 seconds
Started Jul 04 05:03:31 PM PDT 24
Finished Jul 04 05:03:32 PM PDT 24
Peak memory 197196 kb
Host smart-43af4a8a-6fb4-49c7-8259-c76bcc4ac7b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073255707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.4073255707
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1257324264
Short name T34
Test name
Test status
Simulation time 87464892 ps
CPU time 1.44 seconds
Started Jul 04 05:03:25 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 198676 kb
Host smart-70bd2928-7342-43d6-8839-ef45d4cc4190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257324264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1257324264
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1607719912
Short name T116
Test name
Test status
Simulation time 86379099 ps
CPU time 3.43 seconds
Started Jul 04 05:03:32 PM PDT 24
Finished Jul 04 05:03:35 PM PDT 24
Peak memory 198600 kb
Host smart-ed61ab8d-1f11-4734-90db-e28d5a15bee2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607719912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1607719912
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3590449058
Short name T297
Test name
Test status
Simulation time 95003958 ps
CPU time 2.1 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 196684 kb
Host smart-c23a4172-76c9-4b11-b631-9e4d414ffdef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590449058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3590449058
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3299582357
Short name T279
Test name
Test status
Simulation time 40973457 ps
CPU time 0.84 seconds
Started Jul 04 05:03:26 PM PDT 24
Finished Jul 04 05:03:27 PM PDT 24
Peak memory 196556 kb
Host smart-65be7f95-452d-4478-800d-77217efac3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299582357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3299582357
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3556648063
Short name T634
Test name
Test status
Simulation time 36747709 ps
CPU time 0.66 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:03:25 PM PDT 24
Peak memory 194948 kb
Host smart-e03d25ba-bc18-4f58-bbbe-120c6a619e2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556648063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3556648063
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2264950335
Short name T717
Test name
Test status
Simulation time 917426943 ps
CPU time 4.04 seconds
Started Jul 04 05:03:35 PM PDT 24
Finished Jul 04 05:03:40 PM PDT 24
Peak memory 198632 kb
Host smart-20bbd790-9aa1-4f45-b26f-271e5935c0a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264950335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2264950335
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.912003247
Short name T195
Test name
Test status
Simulation time 73657438 ps
CPU time 1.05 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:03:25 PM PDT 24
Peak memory 197080 kb
Host smart-afd177e7-c452-4630-befe-4a8ae331d008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912003247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.912003247
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3436736509
Short name T15
Test name
Test status
Simulation time 217414752 ps
CPU time 1.25 seconds
Started Jul 04 05:03:24 PM PDT 24
Finished Jul 04 05:03:26 PM PDT 24
Peak memory 196068 kb
Host smart-55039bc9-6cd0-4acc-aeb2-49285d7781e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436736509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3436736509
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2220852218
Short name T4
Test name
Test status
Simulation time 3071935107 ps
CPU time 30.61 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:04:08 PM PDT 24
Peak memory 198728 kb
Host smart-ac34701c-258a-4276-98a0-9a677648076b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220852218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2220852218
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1047132230
Short name T67
Test name
Test status
Simulation time 951871056778 ps
CPU time 1531.63 seconds
Started Jul 04 05:03:31 PM PDT 24
Finished Jul 04 05:29:03 PM PDT 24
Peak memory 198800 kb
Host smart-5a31c008-d2c3-472d-9b54-d6ea9818c79f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1047132230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1047132230
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2180835748
Short name T437
Test name
Test status
Simulation time 109368180 ps
CPU time 0.59 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 195232 kb
Host smart-eb564636-662e-46c8-bf62-22c8e10060a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180835748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2180835748
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3750083795
Short name T650
Test name
Test status
Simulation time 39689832 ps
CPU time 0.77 seconds
Started Jul 04 05:01:24 PM PDT 24
Finished Jul 04 05:01:26 PM PDT 24
Peak memory 194576 kb
Host smart-10fc864c-f3c7-430d-8ea0-0988a2f0d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750083795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3750083795
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3838000756
Short name T546
Test name
Test status
Simulation time 1591202681 ps
CPU time 20.47 seconds
Started Jul 04 05:01:22 PM PDT 24
Finished Jul 04 05:01:42 PM PDT 24
Peak memory 198600 kb
Host smart-58d44562-cfe2-4989-a2ba-b5a323823b3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838000756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3838000756
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3484869892
Short name T664
Test name
Test status
Simulation time 143338906 ps
CPU time 0.76 seconds
Started Jul 04 05:01:26 PM PDT 24
Finished Jul 04 05:01:27 PM PDT 24
Peak memory 195164 kb
Host smart-81286490-079e-453d-9fb8-2618065c6df4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484869892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3484869892
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1327240129
Short name T454
Test name
Test status
Simulation time 105780750 ps
CPU time 1.3 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:01:25 PM PDT 24
Peak memory 197788 kb
Host smart-b8ab5189-6b2a-4601-8aca-57454bf5ff7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327240129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1327240129
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1722315202
Short name T248
Test name
Test status
Simulation time 374461070 ps
CPU time 0.99 seconds
Started Jul 04 05:01:26 PM PDT 24
Finished Jul 04 05:01:28 PM PDT 24
Peak memory 196504 kb
Host smart-19b2ab5f-faf2-4c3a-8a66-8cf1ae8a29ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722315202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1722315202
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.941590095
Short name T573
Test name
Test status
Simulation time 289007151 ps
CPU time 3.3 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:01:26 PM PDT 24
Peak memory 197668 kb
Host smart-7fd8a38f-f8fa-4f52-afbc-f741036d7c33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941590095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.941590095
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1936962697
Short name T508
Test name
Test status
Simulation time 55540022 ps
CPU time 1.35 seconds
Started Jul 04 05:01:24 PM PDT 24
Finished Jul 04 05:01:26 PM PDT 24
Peak memory 197520 kb
Host smart-51e6c169-8581-46a6-bc41-684b947718a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936962697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1936962697
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4109029489
Short name T497
Test name
Test status
Simulation time 207846130 ps
CPU time 1.23 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:01:24 PM PDT 24
Peak memory 197636 kb
Host smart-3be7c129-834c-466a-bdce-e4330be77a8a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109029489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4109029489
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.170052630
Short name T307
Test name
Test status
Simulation time 111332927 ps
CPU time 5.65 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:01:29 PM PDT 24
Peak memory 198456 kb
Host smart-e43780ff-f2a3-490b-bdac-b7d71ba358ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170052630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.170052630
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.851699429
Short name T486
Test name
Test status
Simulation time 113415534 ps
CPU time 1.14 seconds
Started Jul 04 05:01:25 PM PDT 24
Finished Jul 04 05:01:26 PM PDT 24
Peak memory 196928 kb
Host smart-6f193150-9d6f-4242-8d3f-e96541b67fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851699429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.851699429
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1636973518
Short name T523
Test name
Test status
Simulation time 62218860 ps
CPU time 0.96 seconds
Started Jul 04 05:01:23 PM PDT 24
Finished Jul 04 05:01:24 PM PDT 24
Peak memory 196820 kb
Host smart-ec4a34b2-d733-4dbd-99dd-b926ac18cad2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636973518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1636973518
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2535302931
Short name T143
Test name
Test status
Simulation time 6013378381 ps
CPU time 177.35 seconds
Started Jul 04 05:01:32 PM PDT 24
Finished Jul 04 05:04:29 PM PDT 24
Peak memory 198648 kb
Host smart-f23e055a-b6ce-4bea-94c6-1eb959733ddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535302931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2535302931
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3973179384
Short name T714
Test name
Test status
Simulation time 34522504187 ps
CPU time 697.47 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:13:06 PM PDT 24
Peak memory 198828 kb
Host smart-78976c0a-9958-4f9e-b1a4-2c791a3eedc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3973179384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3973179384
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3816254861
Short name T544
Test name
Test status
Simulation time 25906497 ps
CPU time 0.58 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 194544 kb
Host smart-5a1259d9-c6c0-49e6-9121-f266879487f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816254861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3816254861
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1929649803
Short name T220
Test name
Test status
Simulation time 88632241 ps
CPU time 0.78 seconds
Started Jul 04 05:01:30 PM PDT 24
Finished Jul 04 05:01:31 PM PDT 24
Peak memory 195832 kb
Host smart-f29bf8a5-93fd-4c38-b694-bc2b048be5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929649803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1929649803
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4215532545
Short name T341
Test name
Test status
Simulation time 1160438044 ps
CPU time 26.91 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:58 PM PDT 24
Peak memory 198528 kb
Host smart-d3df418e-17c0-4aed-88b9-9ac823cefc1f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215532545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4215532545
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2355593340
Short name T20
Test name
Test status
Simulation time 1612340318 ps
CPU time 1.13 seconds
Started Jul 04 05:01:32 PM PDT 24
Finished Jul 04 05:01:34 PM PDT 24
Peak memory 198316 kb
Host smart-9334f4a3-ef2c-45ab-858c-36e5105b3c58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355593340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2355593340
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3979674263
Short name T566
Test name
Test status
Simulation time 330989927 ps
CPU time 1.16 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:33 PM PDT 24
Peak memory 196616 kb
Host smart-df8f864a-320a-411d-af36-1fc38bca7f71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979674263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3979674263
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3193538835
Short name T182
Test name
Test status
Simulation time 116469821 ps
CPU time 1.43 seconds
Started Jul 04 05:01:28 PM PDT 24
Finished Jul 04 05:01:30 PM PDT 24
Peak memory 198736 kb
Host smart-7e676cba-baab-466a-82f6-3f83e09ccfb0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193538835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3193538835
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.4182894518
Short name T254
Test name
Test status
Simulation time 340204545 ps
CPU time 2.81 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:34 PM PDT 24
Peak memory 198712 kb
Host smart-d6381b09-a854-4b3a-807d-c61c60c555b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182894518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
4182894518
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.305468501
Short name T267
Test name
Test status
Simulation time 31600489 ps
CPU time 1.08 seconds
Started Jul 04 05:01:30 PM PDT 24
Finished Jul 04 05:01:31 PM PDT 24
Peak memory 196576 kb
Host smart-affa63dc-688e-4077-a011-ee6529c4d3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305468501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.305468501
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.24418907
Short name T429
Test name
Test status
Simulation time 34475322 ps
CPU time 1.12 seconds
Started Jul 04 05:01:30 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 196744 kb
Host smart-41143c74-0d76-40ad-9cfd-010989f43a41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24418907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_p
ulldown.24418907
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.60602887
Short name T706
Test name
Test status
Simulation time 1162509392 ps
CPU time 3.35 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:01:33 PM PDT 24
Peak memory 197608 kb
Host smart-1c022959-3a77-4a8d-96e9-23bd9a338d6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60602887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rando
m_long_reg_writes_reg_reads.60602887
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2447679102
Short name T378
Test name
Test status
Simulation time 692527488 ps
CPU time 1.04 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:33 PM PDT 24
Peak memory 196932 kb
Host smart-322c9fff-efd4-4cc7-94c6-700112a2b591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447679102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2447679102
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1854004693
Short name T192
Test name
Test status
Simulation time 48072401 ps
CPU time 0.98 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:33 PM PDT 24
Peak memory 196072 kb
Host smart-7f244f58-4783-4a3b-8ca6-5d5fc88c1c1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854004693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1854004693
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1057781217
Short name T583
Test name
Test status
Simulation time 25625385605 ps
CPU time 171.12 seconds
Started Jul 04 05:01:34 PM PDT 24
Finished Jul 04 05:04:26 PM PDT 24
Peak memory 198640 kb
Host smart-4a26b52b-16f5-4613-ac9e-b7482ffa870f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057781217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1057781217
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.927253962
Short name T694
Test name
Test status
Simulation time 36790354375 ps
CPU time 854.25 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:15:44 PM PDT 24
Peak memory 198796 kb
Host smart-23d67380-07bf-40ca-9668-33225d657ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=927253962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.927253962
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2383128068
Short name T285
Test name
Test status
Simulation time 44685685 ps
CPU time 0.6 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 194768 kb
Host smart-f9d8c960-7274-475c-9021-42dd7f121f1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383128068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2383128068
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1183556895
Short name T671
Test name
Test status
Simulation time 74695111 ps
CPU time 0.81 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 195856 kb
Host smart-2b04b630-f0b7-46f8-95a2-a10f450e4481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183556895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1183556895
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3425027391
Short name T135
Test name
Test status
Simulation time 1018892114 ps
CPU time 28.46 seconds
Started Jul 04 05:01:30 PM PDT 24
Finished Jul 04 05:01:59 PM PDT 24
Peak memory 197416 kb
Host smart-ede5c643-9927-479f-b43a-a5224d3611e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425027391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3425027391
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.4240916827
Short name T419
Test name
Test status
Simulation time 223280919 ps
CPU time 0.92 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:01:30 PM PDT 24
Peak memory 197376 kb
Host smart-ebf0df85-4ba7-4a85-ac0f-5b03627a8cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240916827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.4240916827
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1072335543
Short name T415
Test name
Test status
Simulation time 48719908 ps
CPU time 1.11 seconds
Started Jul 04 05:01:32 PM PDT 24
Finished Jul 04 05:01:33 PM PDT 24
Peak memory 196648 kb
Host smart-50abf33b-364b-4699-b00a-08544cc26c09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072335543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1072335543
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1540436972
Short name T197
Test name
Test status
Simulation time 155591072 ps
CPU time 1.64 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:01:30 PM PDT 24
Peak memory 196800 kb
Host smart-79866d11-5066-4c99-99a7-d0a1b7b241a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540436972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1540436972
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4162978683
Short name T619
Test name
Test status
Simulation time 368125962 ps
CPU time 1.92 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:01:31 PM PDT 24
Peak memory 196776 kb
Host smart-792e413f-0cf5-431b-b778-6adc33e55022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162978683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
4162978683
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1795315964
Short name T598
Test name
Test status
Simulation time 25769123 ps
CPU time 1.08 seconds
Started Jul 04 05:01:30 PM PDT 24
Finished Jul 04 05:01:31 PM PDT 24
Peak memory 197252 kb
Host smart-1598e487-b1c6-4397-a26c-81e02fcecdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795315964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1795315964
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1979838620
Short name T83
Test name
Test status
Simulation time 98662459 ps
CPU time 0.78 seconds
Started Jul 04 05:01:33 PM PDT 24
Finished Jul 04 05:01:34 PM PDT 24
Peak memory 196084 kb
Host smart-c19dcfdf-7860-4612-94e6-bca82e0a9c8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979838620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1979838620
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1319247828
Short name T519
Test name
Test status
Simulation time 120675273 ps
CPU time 2.24 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 198604 kb
Host smart-e8ba87cb-a334-4520-ae8c-4ed7c39f5a74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319247828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1319247828
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1031221947
Short name T377
Test name
Test status
Simulation time 31643753 ps
CPU time 0.91 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 195780 kb
Host smart-25c2e9d1-9720-4578-821f-8127ecb38dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031221947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1031221947
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.179205362
Short name T234
Test name
Test status
Simulation time 122963045 ps
CPU time 1.2 seconds
Started Jul 04 05:01:30 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 196768 kb
Host smart-c3a1a197-8cf9-461a-ab73-b3e3d0cb9307
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179205362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.179205362
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3143561256
Short name T396
Test name
Test status
Simulation time 13947966061 ps
CPU time 52.71 seconds
Started Jul 04 05:01:28 PM PDT 24
Finished Jul 04 05:02:21 PM PDT 24
Peak memory 198620 kb
Host smart-3cd1fef4-6c12-4773-a95d-7693dbb7d863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143561256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3143561256
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.319358303
Short name T177
Test name
Test status
Simulation time 34374445 ps
CPU time 0.58 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:38 PM PDT 24
Peak memory 194524 kb
Host smart-d1661ea3-1706-4b2c-802c-017871a73eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319358303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.319358303
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1119648890
Short name T702
Test name
Test status
Simulation time 248805945 ps
CPU time 0.92 seconds
Started Jul 04 05:01:33 PM PDT 24
Finished Jul 04 05:01:34 PM PDT 24
Peak memory 196464 kb
Host smart-437821fd-304d-4e1f-a240-e5628466d3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119648890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1119648890
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1308386246
Short name T689
Test name
Test status
Simulation time 267916676 ps
CPU time 7.42 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:45 PM PDT 24
Peak memory 197444 kb
Host smart-064e9aa6-f600-4372-bc60-f8aa5974a9d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308386246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1308386246
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1302119434
Short name T509
Test name
Test status
Simulation time 80958261 ps
CPU time 0.83 seconds
Started Jul 04 05:01:35 PM PDT 24
Finished Jul 04 05:01:36 PM PDT 24
Peak memory 196956 kb
Host smart-a413af8b-be93-4288-ae98-86b5593b1a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302119434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1302119434
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.135926297
Short name T388
Test name
Test status
Simulation time 164020306 ps
CPU time 0.97 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 197964 kb
Host smart-b5ee541b-ec76-4740-aae7-2d39405d35c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135926297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.135926297
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.4097267101
Short name T643
Test name
Test status
Simulation time 105555327 ps
CPU time 2.29 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:40 PM PDT 24
Peak memory 196980 kb
Host smart-895e3313-5c31-407a-972c-608b9402c686
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097267101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.4097267101
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.32638313
Short name T305
Test name
Test status
Simulation time 325501208 ps
CPU time 3.44 seconds
Started Jul 04 05:01:39 PM PDT 24
Finished Jul 04 05:01:42 PM PDT 24
Peak memory 197076 kb
Host smart-12fe9d08-dc46-4171-b0bd-ef66663f186e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32638313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.32638313
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2286264261
Short name T457
Test name
Test status
Simulation time 24660106 ps
CPU time 1.06 seconds
Started Jul 04 05:01:31 PM PDT 24
Finished Jul 04 05:01:32 PM PDT 24
Peak memory 196352 kb
Host smart-21e6e2a0-c0a0-46e9-8b3a-9ada67cae4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286264261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2286264261
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1251034590
Short name T185
Test name
Test status
Simulation time 243255651 ps
CPU time 0.89 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:01:31 PM PDT 24
Peak memory 196556 kb
Host smart-50bb285b-a589-4386-a85d-110eedaea102
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251034590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1251034590
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2759195716
Short name T7
Test name
Test status
Simulation time 355223107 ps
CPU time 4.48 seconds
Started Jul 04 05:01:39 PM PDT 24
Finished Jul 04 05:01:44 PM PDT 24
Peak memory 198520 kb
Host smart-8c16bdc9-c3d1-40f2-8806-d1aa501554e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759195716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2759195716
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3393760545
Short name T178
Test name
Test status
Simulation time 61704490 ps
CPU time 1.29 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:01:31 PM PDT 24
Peak memory 197276 kb
Host smart-010d93e4-fe1b-43a6-97f2-8a83a58df221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393760545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3393760545
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.584247116
Short name T653
Test name
Test status
Simulation time 203590852 ps
CPU time 1.19 seconds
Started Jul 04 05:01:29 PM PDT 24
Finished Jul 04 05:01:31 PM PDT 24
Peak memory 196100 kb
Host smart-f2804729-d121-4f1c-9c3b-025af2bb6f10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584247116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.584247116
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2192393359
Short name T322
Test name
Test status
Simulation time 2556096159 ps
CPU time 81.39 seconds
Started Jul 04 05:01:36 PM PDT 24
Finished Jul 04 05:02:58 PM PDT 24
Peak memory 198760 kb
Host smart-b72ff401-a6c1-4db0-b3a4-0574eb8a14be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192393359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2192393359
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2982369017
Short name T73
Test name
Test status
Simulation time 150891068050 ps
CPU time 2178.09 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:37:56 PM PDT 24
Peak memory 198816 kb
Host smart-78a24bb6-2a72-4605-b48e-c19a0d9c2460
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2982369017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2982369017
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.464536256
Short name T211
Test name
Test status
Simulation time 20539887 ps
CPU time 0.57 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:38 PM PDT 24
Peak memory 194516 kb
Host smart-26b64d4c-d0cd-4ef6-aa3d-2d407e3600b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464536256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.464536256
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2984280326
Short name T347
Test name
Test status
Simulation time 241420162 ps
CPU time 0.71 seconds
Started Jul 04 05:01:39 PM PDT 24
Finished Jul 04 05:01:40 PM PDT 24
Peak memory 195764 kb
Host smart-153171d2-3e1e-43b8-be90-2427d2306fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984280326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2984280326
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1667866128
Short name T594
Test name
Test status
Simulation time 720882360 ps
CPU time 18.76 seconds
Started Jul 04 05:01:39 PM PDT 24
Finished Jul 04 05:01:58 PM PDT 24
Peak memory 197380 kb
Host smart-53070e34-f234-49dc-9f54-e327b2ad0da6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667866128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1667866128
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2057347170
Short name T382
Test name
Test status
Simulation time 35270422 ps
CPU time 0.74 seconds
Started Jul 04 05:01:36 PM PDT 24
Finished Jul 04 05:01:37 PM PDT 24
Peak memory 196272 kb
Host smart-7aad2c66-7b51-43fd-9f92-e78f3922922b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057347170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2057347170
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2002856462
Short name T713
Test name
Test status
Simulation time 180519903 ps
CPU time 1.5 seconds
Started Jul 04 05:01:41 PM PDT 24
Finished Jul 04 05:01:42 PM PDT 24
Peak memory 198664 kb
Host smart-97a4159c-cfbb-47e6-83ea-c4b776e49831
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002856462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2002856462
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3612020748
Short name T536
Test name
Test status
Simulation time 42450367 ps
CPU time 1.84 seconds
Started Jul 04 05:01:38 PM PDT 24
Finished Jul 04 05:01:40 PM PDT 24
Peak memory 198656 kb
Host smart-568ef0a7-f974-4bf9-b4c2-50fda60f2b41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612020748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3612020748
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.857926891
Short name T549
Test name
Test status
Simulation time 109026411 ps
CPU time 3.02 seconds
Started Jul 04 05:01:36 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 196336 kb
Host smart-1374d39a-d2c1-4857-abbf-ccdc229fba2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857926891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.857926891
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.200737658
Short name T314
Test name
Test status
Simulation time 27797502 ps
CPU time 0.84 seconds
Started Jul 04 05:01:40 PM PDT 24
Finished Jul 04 05:01:41 PM PDT 24
Peak memory 196712 kb
Host smart-94c9aeb0-6a23-4744-b765-423187bea2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200737658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.200737658
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3620271962
Short name T530
Test name
Test status
Simulation time 23268329 ps
CPU time 0.78 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:38 PM PDT 24
Peak memory 196664 kb
Host smart-6d356db0-5cba-4a11-a73f-38e7165bd1f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620271962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3620271962
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1281540474
Short name T597
Test name
Test status
Simulation time 75420840 ps
CPU time 2.04 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 198548 kb
Host smart-119e8ff0-a0e7-448e-bece-eda517e21227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281540474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1281540474
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3452001768
Short name T199
Test name
Test status
Simulation time 56435069 ps
CPU time 1.25 seconds
Started Jul 04 05:01:39 PM PDT 24
Finished Jul 04 05:01:41 PM PDT 24
Peak memory 196940 kb
Host smart-ee0084e3-f6ab-4afc-bf37-2b4bf076ce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452001768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3452001768
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1601780343
Short name T275
Test name
Test status
Simulation time 93417148 ps
CPU time 1.04 seconds
Started Jul 04 05:01:37 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 196284 kb
Host smart-46ded4a6-928d-40fb-8fde-b75dca505348
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601780343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1601780343
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1874481689
Short name T439
Test name
Test status
Simulation time 8903316827 ps
CPU time 135.31 seconds
Started Jul 04 05:01:41 PM PDT 24
Finished Jul 04 05:03:56 PM PDT 24
Peak memory 198696 kb
Host smart-f3928da1-913f-4742-b41a-4b7d6abc3bc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874481689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1874481689
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.8337324
Short name T853
Test name
Test status
Simulation time 123576924 ps
CPU time 0.79 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 195788 kb
Host smart-08ea3365-3b28-42ed-9aa1-f2317dcc5dd7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=8337324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.8337324
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3491504268
Short name T921
Test name
Test status
Simulation time 68993309 ps
CPU time 1.24 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 196868 kb
Host smart-ef2de64a-073e-4be1-81e3-e37aef59b67c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491504268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3491504268
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2147986227
Short name T895
Test name
Test status
Simulation time 99425171 ps
CPU time 1.05 seconds
Started Jul 04 04:51:29 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 196920 kb
Host smart-cb505ed5-fa3d-4918-8a4f-d5e1ddcbdd0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2147986227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2147986227
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2914151072
Short name T920
Test name
Test status
Simulation time 65268660 ps
CPU time 1.07 seconds
Started Jul 04 04:51:30 PM PDT 24
Finished Jul 04 04:51:31 PM PDT 24
Peak memory 196212 kb
Host smart-2826e974-60f1-4a72-bb38-887fade37b30
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914151072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2914151072
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4202273147
Short name T918
Test name
Test status
Simulation time 23207539 ps
CPU time 0.67 seconds
Started Jul 04 04:51:37 PM PDT 24
Finished Jul 04 04:51:38 PM PDT 24
Peak memory 194580 kb
Host smart-16c36d5f-0e30-405e-8599-3bbc050e0d61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4202273147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.4202273147
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3185816512
Short name T892
Test name
Test status
Simulation time 360308196 ps
CPU time 1.24 seconds
Started Jul 04 04:51:40 PM PDT 24
Finished Jul 04 04:51:42 PM PDT 24
Peak memory 197004 kb
Host smart-662f3e2b-54b6-4fa4-9fc0-80f4f0e427ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185816512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3185816512
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1599404382
Short name T889
Test name
Test status
Simulation time 121685216 ps
CPU time 1.05 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 196964 kb
Host smart-f40ec955-7b94-4c57-85be-008a05db2f8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1599404382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1599404382
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3454913302
Short name T915
Test name
Test status
Simulation time 285410545 ps
CPU time 1.3 seconds
Started Jul 04 04:51:37 PM PDT 24
Finished Jul 04 04:51:39 PM PDT 24
Peak memory 196648 kb
Host smart-d3351a33-fee3-41aa-9192-65910bf71857
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454913302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3454913302
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3419318958
Short name T906
Test name
Test status
Simulation time 108082159 ps
CPU time 1.02 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:39 PM PDT 24
Peak memory 196740 kb
Host smart-3708cf7d-4569-4f78-84f4-2d5bc92ef64c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3419318958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3419318958
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.190817097
Short name T935
Test name
Test status
Simulation time 217927399 ps
CPU time 1.56 seconds
Started Jul 04 04:51:36 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 195936 kb
Host smart-a03aa87e-9903-4b66-a89b-fbfc0305b4bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190817097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.190817097
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.852298830
Short name T877
Test name
Test status
Simulation time 55639180 ps
CPU time 0.91 seconds
Started Jul 04 04:51:34 PM PDT 24
Finished Jul 04 04:51:35 PM PDT 24
Peak memory 196600 kb
Host smart-ae644369-10f4-48ba-851c-37cfa1193ea3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=852298830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.852298830
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1608176116
Short name T864
Test name
Test status
Simulation time 149729090 ps
CPU time 1.31 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 198280 kb
Host smart-5f2b60eb-5c4d-42fe-88ea-75246695cb6c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608176116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1608176116
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.785262112
Short name T905
Test name
Test status
Simulation time 219692816 ps
CPU time 1.12 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 196880 kb
Host smart-effd9416-fdc2-4372-a075-e0ec782884c9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=785262112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.785262112
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2521211239
Short name T902
Test name
Test status
Simulation time 90335988 ps
CPU time 0.88 seconds
Started Jul 04 04:51:34 PM PDT 24
Finished Jul 04 04:51:35 PM PDT 24
Peak memory 196944 kb
Host smart-a0683b68-0cdc-4447-ad9d-369907cb30b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521211239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2521211239
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.123071224
Short name T887
Test name
Test status
Simulation time 261173957 ps
CPU time 1.39 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:39 PM PDT 24
Peak memory 196832 kb
Host smart-f849e878-6a44-486a-a908-f072705788e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=123071224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.123071224
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3339674390
Short name T851
Test name
Test status
Simulation time 81877718 ps
CPU time 1.64 seconds
Started Jul 04 04:51:37 PM PDT 24
Finished Jul 04 04:51:39 PM PDT 24
Peak memory 197120 kb
Host smart-673c575f-e769-4b94-98ec-555feb3482d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339674390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3339674390
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3215300031
Short name T938
Test name
Test status
Simulation time 48731527 ps
CPU time 1.24 seconds
Started Jul 04 04:51:36 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 196896 kb
Host smart-b88d5842-6591-44dd-a503-abb4c19650da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3215300031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3215300031
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2829003830
Short name T893
Test name
Test status
Simulation time 201151156 ps
CPU time 1.17 seconds
Started Jul 04 04:51:36 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 197256 kb
Host smart-3e6f5ee1-1679-41c7-9760-8cf805b5d37c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829003830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2829003830
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2567296250
Short name T850
Test name
Test status
Simulation time 613224268 ps
CPU time 1.27 seconds
Started Jul 04 04:51:36 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 196800 kb
Host smart-209595c4-f675-4561-8f7c-210d60db8e09
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2567296250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2567296250
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.539169511
Short name T859
Test name
Test status
Simulation time 169844539 ps
CPU time 1.63 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 197160 kb
Host smart-a1519598-285f-4eba-a66c-8b1286625d22
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539169511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.539169511
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1616248978
Short name T885
Test name
Test status
Simulation time 76202505 ps
CPU time 1.43 seconds
Started Jul 04 04:51:37 PM PDT 24
Finished Jul 04 04:51:39 PM PDT 24
Peak memory 196908 kb
Host smart-4e9a8fbc-ed83-44c5-b3ec-a626f619fc64
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1616248978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1616248978
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.503989201
Short name T852
Test name
Test status
Simulation time 196518117 ps
CPU time 0.97 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:36 PM PDT 24
Peak memory 196784 kb
Host smart-e9853e44-2bd1-4c45-9a55-7089211466c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503989201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.503989201
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2282860283
Short name T912
Test name
Test status
Simulation time 37546627 ps
CPU time 0.95 seconds
Started Jul 04 04:51:39 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 196296 kb
Host smart-91da29d7-79ec-4e9c-a3ff-f3340a74447f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2282860283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2282860283
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1460622327
Short name T874
Test name
Test status
Simulation time 92154232 ps
CPU time 1.33 seconds
Started Jul 04 04:51:33 PM PDT 24
Finished Jul 04 04:51:35 PM PDT 24
Peak memory 197196 kb
Host smart-94b65d7e-8319-4c12-8c4c-1f1108ee381f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460622327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1460622327
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2829262221
Short name T876
Test name
Test status
Simulation time 147373405 ps
CPU time 1.45 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 197144 kb
Host smart-3180255f-389f-49fe-a59e-98def4c73943
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2829262221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2829262221
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4132568808
Short name T873
Test name
Test status
Simulation time 361574150 ps
CPU time 0.94 seconds
Started Jul 04 04:51:37 PM PDT 24
Finished Jul 04 04:51:39 PM PDT 24
Peak memory 198116 kb
Host smart-d25da964-3fd3-420b-9aa6-e67df78de19d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132568808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4132568808
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2770450765
Short name T919
Test name
Test status
Simulation time 141644315 ps
CPU time 1.15 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 196824 kb
Host smart-7c564f50-0cfe-4e58-a489-dcb4e2943ab6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2770450765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2770450765
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.204035329
Short name T878
Test name
Test status
Simulation time 222719226 ps
CPU time 1.41 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 196968 kb
Host smart-1db17dc6-3d77-4254-b0e8-8cea2a94eda9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204035329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.204035329
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2764976317
Short name T924
Test name
Test status
Simulation time 150452812 ps
CPU time 1.28 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 196796 kb
Host smart-d90c3ff4-13cc-4e9d-b724-bb70139ca2a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2764976317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2764976317
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3590881856
Short name T929
Test name
Test status
Simulation time 135429962 ps
CPU time 1.14 seconds
Started Jul 04 04:51:40 PM PDT 24
Finished Jul 04 04:51:41 PM PDT 24
Peak memory 196160 kb
Host smart-4a877978-00cd-4201-9dbe-3e313048f046
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590881856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3590881856
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.786798831
Short name T941
Test name
Test status
Simulation time 233418888 ps
CPU time 1.25 seconds
Started Jul 04 04:51:39 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 198328 kb
Host smart-52a93778-7ed9-4a62-9b20-a72101933be7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=786798831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.786798831
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.971029590
Short name T913
Test name
Test status
Simulation time 31080261 ps
CPU time 1.08 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 196032 kb
Host smart-cca2fcf1-7df1-452d-92dd-0e369f66028a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971029590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.971029590
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3134084905
Short name T943
Test name
Test status
Simulation time 35665247 ps
CPU time 0.93 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:39 PM PDT 24
Peak memory 196916 kb
Host smart-27ac60a0-0d25-46ca-b6d0-092f972d42ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3134084905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3134084905
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.402641378
Short name T886
Test name
Test status
Simulation time 125136649 ps
CPU time 0.83 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 195860 kb
Host smart-816b842e-fadc-4f74-8e33-692169a9e34d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402641378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.402641378
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2524580574
Short name T925
Test name
Test status
Simulation time 61911148 ps
CPU time 1.29 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 196876 kb
Host smart-f16e20d1-7315-4eb1-8634-fd66d430cf07
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2524580574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2524580574
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1072831912
Short name T881
Test name
Test status
Simulation time 43638106 ps
CPU time 0.96 seconds
Started Jul 04 04:51:43 PM PDT 24
Finished Jul 04 04:51:44 PM PDT 24
Peak memory 197644 kb
Host smart-39ca488c-8102-496d-b639-7234abbbcabb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072831912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1072831912
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.470988284
Short name T914
Test name
Test status
Simulation time 86121137 ps
CPU time 1.61 seconds
Started Jul 04 04:51:44 PM PDT 24
Finished Jul 04 04:51:46 PM PDT 24
Peak memory 198304 kb
Host smart-bcc23017-2d09-403f-b514-2bc7c44d46dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=470988284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.470988284
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2614715390
Short name T930
Test name
Test status
Simulation time 274074187 ps
CPU time 1.13 seconds
Started Jul 04 04:51:44 PM PDT 24
Finished Jul 04 04:51:45 PM PDT 24
Peak memory 195924 kb
Host smart-152653d3-14cc-4644-8665-fd8fd3637d3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614715390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2614715390
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4042126282
Short name T904
Test name
Test status
Simulation time 54758302 ps
CPU time 1.01 seconds
Started Jul 04 04:51:43 PM PDT 24
Finished Jul 04 04:51:44 PM PDT 24
Peak memory 198308 kb
Host smart-c7256644-ccde-4c85-934e-e42d4b52580b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4042126282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.4042126282
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1969074547
Short name T867
Test name
Test status
Simulation time 184385299 ps
CPU time 1.36 seconds
Started Jul 04 04:51:42 PM PDT 24
Finished Jul 04 04:51:44 PM PDT 24
Peak memory 195948 kb
Host smart-b348e855-5699-49f7-abeb-dfada066a6c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969074547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1969074547
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1703055346
Short name T847
Test name
Test status
Simulation time 282316775 ps
CPU time 1.34 seconds
Started Jul 04 04:51:41 PM PDT 24
Finished Jul 04 04:51:43 PM PDT 24
Peak memory 195988 kb
Host smart-f7b50bf0-0f2f-4119-a95f-e2cd2cecfa82
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1703055346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1703055346
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2074170670
Short name T863
Test name
Test status
Simulation time 51945837 ps
CPU time 1 seconds
Started Jul 04 04:51:42 PM PDT 24
Finished Jul 04 04:51:44 PM PDT 24
Peak memory 196852 kb
Host smart-81e5c5f0-f9b1-4262-9155-e7acd4cae5cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074170670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2074170670
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4122033450
Short name T870
Test name
Test status
Simulation time 186016354 ps
CPU time 1.47 seconds
Started Jul 04 04:51:44 PM PDT 24
Finished Jul 04 04:51:46 PM PDT 24
Peak memory 198344 kb
Host smart-1dbd2f50-3d1f-4cd7-bcfd-d83bae0b569a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4122033450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4122033450
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3064768742
Short name T898
Test name
Test status
Simulation time 42080129 ps
CPU time 1.18 seconds
Started Jul 04 04:51:45 PM PDT 24
Finished Jul 04 04:51:46 PM PDT 24
Peak memory 195952 kb
Host smart-d43d2d16-4ad2-45f6-970e-c3f1abdc4347
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064768742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3064768742
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.624674690
Short name T897
Test name
Test status
Simulation time 74258458 ps
CPU time 1.21 seconds
Started Jul 04 04:51:42 PM PDT 24
Finished Jul 04 04:51:43 PM PDT 24
Peak memory 198328 kb
Host smart-30b6bf36-36e3-4d6f-a35f-32e7497c283f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=624674690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.624674690
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4006211633
Short name T900
Test name
Test status
Simulation time 44450483 ps
CPU time 1.29 seconds
Started Jul 04 04:51:44 PM PDT 24
Finished Jul 04 04:51:46 PM PDT 24
Peak memory 196928 kb
Host smart-a6a81f8e-7b55-4e46-91a7-fa12dd776a1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006211633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4006211633
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.214983818
Short name T860
Test name
Test status
Simulation time 82675166 ps
CPU time 1.32 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:36 PM PDT 24
Peak memory 198336 kb
Host smart-4b8f93c6-6e43-4d07-99d2-dc27529aa6a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=214983818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.214983818
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2945160338
Short name T899
Test name
Test status
Simulation time 51538603 ps
CPU time 1.04 seconds
Started Jul 04 04:51:37 PM PDT 24
Finished Jul 04 04:51:39 PM PDT 24
Peak memory 198248 kb
Host smart-36f03779-70fb-4f59-9e27-d725ed43a0ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945160338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2945160338
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1930988987
Short name T854
Test name
Test status
Simulation time 29284378 ps
CPU time 0.94 seconds
Started Jul 04 04:51:42 PM PDT 24
Finished Jul 04 04:51:43 PM PDT 24
Peak memory 195788 kb
Host smart-bd76f621-a509-4980-b99a-14bb059f14d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1930988987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1930988987
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1127294763
Short name T849
Test name
Test status
Simulation time 27637363 ps
CPU time 0.9 seconds
Started Jul 04 04:51:44 PM PDT 24
Finished Jul 04 04:51:45 PM PDT 24
Peak memory 195528 kb
Host smart-7ab52a9c-f12c-47f4-859f-2b5aee99c3fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127294763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1127294763
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.604892910
Short name T857
Test name
Test status
Simulation time 51751659 ps
CPU time 0.72 seconds
Started Jul 04 04:51:42 PM PDT 24
Finished Jul 04 04:51:43 PM PDT 24
Peak memory 194672 kb
Host smart-a6ffb9f8-d4d6-436f-9d6c-4be38634004e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=604892910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.604892910
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.9450694
Short name T903
Test name
Test status
Simulation time 202791322 ps
CPU time 1.27 seconds
Started Jul 04 04:51:43 PM PDT 24
Finished Jul 04 04:51:44 PM PDT 24
Peak memory 197256 kb
Host smart-85a57102-d945-446c-9c6c-c28fe2400363
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9450694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.9450694
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.688016103
Short name T882
Test name
Test status
Simulation time 332765176 ps
CPU time 1.2 seconds
Started Jul 04 04:51:43 PM PDT 24
Finished Jul 04 04:51:44 PM PDT 24
Peak memory 196888 kb
Host smart-dc6f5e07-9e45-4795-8070-604bd9e88766
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=688016103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.688016103
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3923456103
Short name T861
Test name
Test status
Simulation time 400447140 ps
CPU time 1.5 seconds
Started Jul 04 04:51:46 PM PDT 24
Finished Jul 04 04:51:48 PM PDT 24
Peak memory 196884 kb
Host smart-9329d6f4-a2a3-4a33-a426-f85daa680325
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923456103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3923456103
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1334379549
Short name T939
Test name
Test status
Simulation time 141216328 ps
CPU time 1.05 seconds
Started Jul 04 04:51:43 PM PDT 24
Finished Jul 04 04:51:44 PM PDT 24
Peak memory 196692 kb
Host smart-8ba36e38-9a95-4993-bdd7-63ed43e5ae59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1334379549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1334379549
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3367922143
Short name T908
Test name
Test status
Simulation time 54662182 ps
CPU time 0.78 seconds
Started Jul 04 04:51:43 PM PDT 24
Finished Jul 04 04:51:44 PM PDT 24
Peak memory 191836 kb
Host smart-9c3a4e25-e6d2-4450-84f4-322b70681f0b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367922143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3367922143
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4251451335
Short name T894
Test name
Test status
Simulation time 234596415 ps
CPU time 1.39 seconds
Started Jul 04 04:51:43 PM PDT 24
Finished Jul 04 04:51:45 PM PDT 24
Peak memory 196332 kb
Host smart-d7f0cae7-6149-4a25-84af-bc4488abd7c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4251451335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4251451335
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4285179741
Short name T888
Test name
Test status
Simulation time 80231334 ps
CPU time 1.41 seconds
Started Jul 04 04:51:43 PM PDT 24
Finished Jul 04 04:51:45 PM PDT 24
Peak memory 198372 kb
Host smart-8fe62565-4fca-435e-a534-9fa7abdb7d3d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285179741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4285179741
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1614262529
Short name T846
Test name
Test status
Simulation time 29457704 ps
CPU time 0.91 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:01 PM PDT 24
Peak memory 195756 kb
Host smart-986b12e5-965f-4fef-b00a-3e24403c4dbb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1614262529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1614262529
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3503996981
Short name T922
Test name
Test status
Simulation time 53044270 ps
CPU time 1.05 seconds
Started Jul 04 04:51:55 PM PDT 24
Finished Jul 04 04:51:56 PM PDT 24
Peak memory 196164 kb
Host smart-97840bdd-6cf2-4c44-b78f-14d03428c742
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503996981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3503996981
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2820717242
Short name T934
Test name
Test status
Simulation time 619290994 ps
CPU time 1.23 seconds
Started Jul 04 04:51:51 PM PDT 24
Finished Jul 04 04:51:53 PM PDT 24
Peak memory 196816 kb
Host smart-24117fdc-0653-494f-a8c2-d5f645e3c92a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2820717242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2820717242
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.403553416
Short name T940
Test name
Test status
Simulation time 53215794 ps
CPU time 1 seconds
Started Jul 04 04:51:53 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 196912 kb
Host smart-25f0d5f5-5e08-4d19-8928-0236a1bafc50
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403553416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.403553416
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1492621298
Short name T890
Test name
Test status
Simulation time 21810306 ps
CPU time 0.75 seconds
Started Jul 04 04:51:51 PM PDT 24
Finished Jul 04 04:51:52 PM PDT 24
Peak memory 194596 kb
Host smart-fb6fb9cf-8598-4f21-b31b-5d86825419e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1492621298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1492621298
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1013990626
Short name T875
Test name
Test status
Simulation time 199318555 ps
CPU time 1.14 seconds
Started Jul 04 04:51:51 PM PDT 24
Finished Jul 04 04:51:53 PM PDT 24
Peak memory 198304 kb
Host smart-0a13e1aa-d1f1-43ed-8ba9-24f815f76a61
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013990626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1013990626
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.431995577
Short name T884
Test name
Test status
Simulation time 161114619 ps
CPU time 1.2 seconds
Started Jul 04 04:51:53 PM PDT 24
Finished Jul 04 04:51:54 PM PDT 24
Peak memory 198328 kb
Host smart-41ce8966-97ad-45ff-ad71-dececf24e992
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=431995577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.431995577
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2180422857
Short name T944
Test name
Test status
Simulation time 40887611 ps
CPU time 1.01 seconds
Started Jul 04 04:51:53 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 196420 kb
Host smart-b5329744-53a8-4cc2-8ae9-231a29efcd24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180422857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2180422857
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1085953793
Short name T937
Test name
Test status
Simulation time 194907407 ps
CPU time 1.46 seconds
Started Jul 04 04:51:54 PM PDT 24
Finished Jul 04 04:51:56 PM PDT 24
Peak memory 196888 kb
Host smart-221e9af0-c307-4bbf-a5cb-02ad81e6019d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1085953793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1085953793
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4259810122
Short name T896
Test name
Test status
Simulation time 139854716 ps
CPU time 1.27 seconds
Started Jul 04 04:51:52 PM PDT 24
Finished Jul 04 04:51:54 PM PDT 24
Peak memory 196164 kb
Host smart-2ceea198-3194-4ed0-a717-e2cb4059d672
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259810122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4259810122
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2733170107
Short name T931
Test name
Test status
Simulation time 71485582 ps
CPU time 1.44 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:36 PM PDT 24
Peak memory 196668 kb
Host smart-075d5237-885c-4143-9858-203340d6cbf4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2733170107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2733170107
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2688962265
Short name T926
Test name
Test status
Simulation time 170182558 ps
CPU time 1.15 seconds
Started Jul 04 04:51:34 PM PDT 24
Finished Jul 04 04:51:36 PM PDT 24
Peak memory 196896 kb
Host smart-19346df3-e850-4227-a51a-9ad058d09732
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688962265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2688962265
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.256975298
Short name T936
Test name
Test status
Simulation time 37797712 ps
CPU time 0.9 seconds
Started Jul 04 04:51:51 PM PDT 24
Finished Jul 04 04:51:53 PM PDT 24
Peak memory 195780 kb
Host smart-c61cade8-8488-421d-9310-f31dd3ce8943
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=256975298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.256975298
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1922421620
Short name T909
Test name
Test status
Simulation time 127102930 ps
CPU time 0.85 seconds
Started Jul 04 04:51:52 PM PDT 24
Finished Jul 04 04:51:53 PM PDT 24
Peak memory 196388 kb
Host smart-f5071036-1e3c-4e66-8456-742aca18f32a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922421620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1922421620
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1522689768
Short name T855
Test name
Test status
Simulation time 298060075 ps
CPU time 1.33 seconds
Started Jul 04 04:51:53 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 197352 kb
Host smart-95e2638e-6c6b-40c4-936b-91c07382e18e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1522689768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1522689768
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3427229262
Short name T848
Test name
Test status
Simulation time 354247230 ps
CPU time 1.23 seconds
Started Jul 04 04:51:53 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 196108 kb
Host smart-ac421d10-2dc5-4fcd-ad72-572c8fc8786f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427229262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3427229262
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.140257452
Short name T869
Test name
Test status
Simulation time 232605807 ps
CPU time 1.5 seconds
Started Jul 04 04:51:54 PM PDT 24
Finished Jul 04 04:51:56 PM PDT 24
Peak memory 195992 kb
Host smart-5d8bb372-53da-4e95-b9f7-fecb232c0ec7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=140257452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.140257452
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1719995500
Short name T923
Test name
Test status
Simulation time 134626790 ps
CPU time 1.08 seconds
Started Jul 04 04:51:54 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 196804 kb
Host smart-00e0d54f-386e-4b5c-ad36-61813004cdb1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719995500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1719995500
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.315905182
Short name T856
Test name
Test status
Simulation time 679675393 ps
CPU time 1.34 seconds
Started Jul 04 04:51:52 PM PDT 24
Finished Jul 04 04:51:54 PM PDT 24
Peak memory 197364 kb
Host smart-af2c2d38-f66f-4b65-9823-233436e720bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=315905182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.315905182
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.925748685
Short name T858
Test name
Test status
Simulation time 49384445 ps
CPU time 1.3 seconds
Started Jul 04 04:51:53 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 197184 kb
Host smart-a85217cb-a5fa-4dd2-886a-10139d178798
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925748685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.925748685
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2467718664
Short name T883
Test name
Test status
Simulation time 78366844 ps
CPU time 0.74 seconds
Started Jul 04 04:51:55 PM PDT 24
Finished Jul 04 04:51:56 PM PDT 24
Peak memory 194688 kb
Host smart-62a74ff8-6102-4d0c-a7ff-5cb03545258c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2467718664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2467718664
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750861018
Short name T901
Test name
Test status
Simulation time 52289627 ps
CPU time 1.5 seconds
Started Jul 04 04:51:50 PM PDT 24
Finished Jul 04 04:51:52 PM PDT 24
Peak memory 197032 kb
Host smart-253085d2-b554-48f3-90b1-8ad23903de76
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750861018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2750861018
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.309060436
Short name T910
Test name
Test status
Simulation time 267283097 ps
CPU time 1.19 seconds
Started Jul 04 04:51:51 PM PDT 24
Finished Jul 04 04:51:53 PM PDT 24
Peak memory 196884 kb
Host smart-3d2ce65c-33c9-4995-a72b-ff0ac43032e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=309060436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.309060436
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387245848
Short name T932
Test name
Test status
Simulation time 293109503 ps
CPU time 1.44 seconds
Started Jul 04 04:51:54 PM PDT 24
Finished Jul 04 04:51:56 PM PDT 24
Peak memory 197340 kb
Host smart-0968d41d-e1b4-468f-8d9e-8c920615cd32
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387245848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.387245848
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.979861569
Short name T942
Test name
Test status
Simulation time 129488031 ps
CPU time 1.08 seconds
Started Jul 04 04:51:55 PM PDT 24
Finished Jul 04 04:51:56 PM PDT 24
Peak memory 196904 kb
Host smart-7b9bd1d3-1f0b-40f0-a814-2652446393ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=979861569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.979861569
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2290091966
Short name T872
Test name
Test status
Simulation time 291730842 ps
CPU time 1.47 seconds
Started Jul 04 04:51:54 PM PDT 24
Finished Jul 04 04:51:56 PM PDT 24
Peak memory 196900 kb
Host smart-1b9f1e66-cdef-48a6-b8dc-60451049787d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290091966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2290091966
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.562501713
Short name T933
Test name
Test status
Simulation time 71004984 ps
CPU time 1.13 seconds
Started Jul 04 04:51:55 PM PDT 24
Finished Jul 04 04:51:57 PM PDT 24
Peak memory 196848 kb
Host smart-fb115671-6108-48e7-a9b1-f37873ab1a0e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=562501713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.562501713
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2710323531
Short name T916
Test name
Test status
Simulation time 320783726 ps
CPU time 1.41 seconds
Started Jul 04 04:51:52 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 197296 kb
Host smart-745b20eb-11ed-4370-95b5-9cb61e22fae1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710323531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2710323531
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1687613936
Short name T928
Test name
Test status
Simulation time 62881796 ps
CPU time 1.22 seconds
Started Jul 04 04:51:54 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 198064 kb
Host smart-6edf2c46-723e-4fcd-818a-d0f08acfbb18
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1687613936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1687613936
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1481768657
Short name T868
Test name
Test status
Simulation time 38243746 ps
CPU time 0.94 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:02 PM PDT 24
Peak memory 198336 kb
Host smart-9974869c-f4f3-4ff1-a951-4ac3cb9aa552
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481768657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1481768657
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2149138813
Short name T879
Test name
Test status
Simulation time 145751990 ps
CPU time 1.22 seconds
Started Jul 04 04:51:53 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 198320 kb
Host smart-4ea5dc96-9981-4d7b-8e22-2ee0a23f63db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2149138813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2149138813
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2597730436
Short name T880
Test name
Test status
Simulation time 92707353 ps
CPU time 1.47 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:01 PM PDT 24
Peak memory 198300 kb
Host smart-f3bb3f17-ba60-43d8-aee2-4dde2efe007b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597730436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2597730436
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4157385773
Short name T866
Test name
Test status
Simulation time 66596810 ps
CPU time 0.96 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:36 PM PDT 24
Peak memory 196532 kb
Host smart-2c610b41-97ec-4e38-b096-98e4af338460
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4157385773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.4157385773
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.827643321
Short name T927
Test name
Test status
Simulation time 103767253 ps
CPU time 1.09 seconds
Started Jul 04 04:51:35 PM PDT 24
Finished Jul 04 04:51:36 PM PDT 24
Peak memory 196888 kb
Host smart-99943630-f4b5-474e-a0dc-9b8541ae2d13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827643321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.827643321
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.958949044
Short name T865
Test name
Test status
Simulation time 78217439 ps
CPU time 1.34 seconds
Started Jul 04 04:51:36 PM PDT 24
Finished Jul 04 04:51:37 PM PDT 24
Peak memory 196912 kb
Host smart-8d8e6b12-96fd-4ca0-83e5-42cc340defd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=958949044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.958949044
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2285611872
Short name T917
Test name
Test status
Simulation time 48988090 ps
CPU time 1.12 seconds
Started Jul 04 04:51:37 PM PDT 24
Finished Jul 04 04:51:38 PM PDT 24
Peak memory 196892 kb
Host smart-ed23ab9a-f259-47c1-b643-372b03a2bd5a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285611872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2285611872
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2012729282
Short name T891
Test name
Test status
Simulation time 194973088 ps
CPU time 1.05 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 196072 kb
Host smart-8dbae98a-c3f3-4993-ae50-991e3c762b4c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2012729282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2012729282
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.125501463
Short name T871
Test name
Test status
Simulation time 300320305 ps
CPU time 1.44 seconds
Started Jul 04 04:51:37 PM PDT 24
Finished Jul 04 04:51:38 PM PDT 24
Peak memory 196156 kb
Host smart-5ebba3f4-c33a-4e87-bacc-44b56ce6b4ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125501463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.125501463
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3237106365
Short name T862
Test name
Test status
Simulation time 110203209 ps
CPU time 1.16 seconds
Started Jul 04 04:51:40 PM PDT 24
Finished Jul 04 04:51:41 PM PDT 24
Peak memory 198304 kb
Host smart-85979bae-9a5b-43c3-a340-82656093b960
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3237106365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3237106365
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4256491762
Short name T911
Test name
Test status
Simulation time 65808397 ps
CPU time 1.58 seconds
Started Jul 04 04:51:38 PM PDT 24
Finished Jul 04 04:51:40 PM PDT 24
Peak memory 196928 kb
Host smart-e4c47410-b861-4cb3-9cd2-bbd55abee5b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256491762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4256491762
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.334518418
Short name T907
Test name
Test status
Simulation time 105448376 ps
CPU time 1.1 seconds
Started Jul 04 04:51:41 PM PDT 24
Finished Jul 04 04:51:42 PM PDT 24
Peak memory 196752 kb
Host smart-0e3ea7fd-e67f-428d-a571-badc57142a83
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=334518418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.334518418
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2543212977
Short name T845
Test name
Test status
Simulation time 66627345 ps
CPU time 1.29 seconds
Started Jul 04 04:51:36 PM PDT 24
Finished Jul 04 04:51:38 PM PDT 24
Peak memory 197040 kb
Host smart-046db547-5762-4029-80e2-a4dff1a5a085
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543212977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2543212977
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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