Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3643268	1			T31	1		T32	24		T33	1
all_pins[1]	3643268	1			T31	1		T32	24		T33	1
all_pins[2]	3643268	1			T31	1		T32	24		T33	1
all_pins[3]	3643268	1			T31	1		T32	24		T33	1
all_pins[4]	3643268	1			T31	1		T32	24		T33	1
all_pins[5]	3643268	1			T31	1		T32	24		T33	1
all_pins[6]	3643268	1			T31	1		T32	24		T33	1
all_pins[7]	3643268	1			T31	1		T32	24		T33	1
all_pins[8]	3643268	1			T31	1		T32	24		T33	1
all_pins[9]	3643268	1			T31	1		T32	24		T33	1
all_pins[10]	3643268	1			T31	1		T32	24		T33	1
all_pins[11]	3643268	1			T31	1		T32	24		T33	1
all_pins[12]	3643268	1			T31	1		T32	24		T33	1
all_pins[13]	3643268	1			T31	1		T32	24		T33	1
all_pins[14]	3643268	1			T31	1		T32	24		T33	1
all_pins[15]	3643268	1			T31	1		T32	24		T33	1
all_pins[16]	3643268	1			T31	1		T32	24		T33	1
all_pins[17]	3643268	1			T31	1		T32	24		T33	1
all_pins[18]	3643268	1			T31	1		T32	24		T33	1
all_pins[19]	3643268	1			T31	1		T32	24		T33	1
all_pins[20]	3643268	1			T31	1		T32	24		T33	1
all_pins[21]	3643268	1			T31	1		T32	24		T33	1
all_pins[22]	3643268	1			T31	1		T32	24		T33	1
all_pins[23]	3643268	1			T31	1		T32	24		T33	1
all_pins[24]	3643268	1			T31	1		T32	24		T33	1
all_pins[25]	3643268	1			T31	1		T32	24		T33	1
all_pins[26]	3643268	1			T31	1		T32	24		T33	1
all_pins[27]	3643268	1			T31	1		T32	24		T33	1
all_pins[28]	3643268	1			T31	1		T32	24		T33	1
all_pins[29]	3643268	1			T31	1		T32	24		T33	1
all_pins[30]	3643268	1			T31	1		T32	24		T33	1
all_pins[31]	3643268	1			T31	1		T32	24		T33	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	72427627	1			T31	32		T32	401		T33	32
values[0x1]	44156949	1			T32	367		T36	760		T37	305
transitions[0x0=>0x1]	26465485	1			T32	177		T36	479		T37	163
transitions[0x1=>0x0]	26465338	1			T32	177		T36	478		T37	162

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2261446	1			T31	1		T32	17		T33	1
all_pins[0]	values[0x1]	1381822	1			T32	7		T36	20		T37	6
all_pins[0]	transitions[0x0=>0x1]	852849	1			T32	5		T36	14		T37	2
all_pins[0]	transitions[0x1=>0x0]	857409	1			T32	6		T36	13		T37	2
all_pins[1]	values[0x0]	2261259	1			T31	1		T32	11		T33	1
all_pins[1]	values[0x1]	1382009	1			T32	13		T36	29		T37	7
all_pins[1]	transitions[0x0=>0x1]	829075	1			T32	9		T36	17		T37	5
all_pins[1]	transitions[0x1=>0x0]	828888	1			T32	3		T36	8		T37	4
all_pins[2]	values[0x0]	2258979	1			T31	1		T32	12		T33	1
all_pins[2]	values[0x1]	1384289	1			T32	12		T36	18		T37	10
all_pins[2]	transitions[0x0=>0x1]	826197	1			T32	5		T36	11		T37	6
all_pins[2]	transitions[0x1=>0x0]	823917	1			T32	6		T36	22		T37	3
all_pins[3]	values[0x0]	2262673	1			T31	1		T32	16		T33	1
all_pins[3]	values[0x1]	1380595	1			T32	8		T36	23		T37	9
all_pins[3]	transitions[0x0=>0x1]	824214	1			T32	2		T36	18		T37	3
all_pins[3]	transitions[0x1=>0x0]	827908	1			T32	6		T36	13		T37	4
all_pins[4]	values[0x0]	2261310	1			T31	1		T32	13		T33	1
all_pins[4]	values[0x1]	1381958	1			T32	11		T36	12		T37	15
all_pins[4]	transitions[0x0=>0x1]	825183	1			T32	6		T36	7		T37	11
all_pins[4]	transitions[0x1=>0x0]	823820	1			T32	3		T36	18		T37	5
all_pins[5]	values[0x0]	2259612	1			T31	1		T32	10		T33	1
all_pins[5]	values[0x1]	1383656	1			T32	14		T36	18		T37	11
all_pins[5]	transitions[0x0=>0x1]	827867	1			T32	8		T36	15		T37	6
all_pins[5]	transitions[0x1=>0x0]	826169	1			T32	5		T36	9		T37	10
all_pins[6]	values[0x0]	2266416	1			T31	1		T32	11		T33	1
all_pins[6]	values[0x1]	1376852	1			T32	13		T36	24		T37	10
all_pins[6]	transitions[0x0=>0x1]	822969	1			T32	5		T36	17		T37	3
all_pins[6]	transitions[0x1=>0x0]	829773	1			T32	6		T36	11		T37	4
all_pins[7]	values[0x0]	2268439	1			T31	1		T32	13		T33	1
all_pins[7]	values[0x1]	1374829	1			T32	11		T36	19		T37	6
all_pins[7]	transitions[0x0=>0x1]	824421	1			T32	4		T36	15		T37	2
all_pins[7]	transitions[0x1=>0x0]	826444	1			T32	6		T36	20		T37	6
all_pins[8]	values[0x0]	2263428	1			T31	1		T32	16		T33	1
all_pins[8]	values[0x1]	1379840	1			T32	8		T36	24		T37	5
all_pins[8]	transitions[0x0=>0x1]	829308	1			T32	6		T36	16		T37	3
all_pins[8]	transitions[0x1=>0x0]	824297	1			T32	9		T36	11		T37	4
all_pins[9]	values[0x0]	2264327	1			T31	1		T32	15		T33	1
all_pins[9]	values[0x1]	1378941	1			T32	9		T36	25		T37	8
all_pins[9]	transitions[0x0=>0x1]	826430	1			T32	6		T36	17		T37	4
all_pins[9]	transitions[0x1=>0x0]	827329	1			T32	5		T36	16		T37	1
all_pins[10]	values[0x0]	2263094	1			T31	1		T32	11		T33	1
all_pins[10]	values[0x1]	1380174	1			T32	13		T36	23		T37	4
all_pins[10]	transitions[0x0=>0x1]	828500	1			T32	8		T36	15		T37	2
all_pins[10]	transitions[0x1=>0x0]	827267	1			T32	4		T36	17		T37	6
all_pins[11]	values[0x0]	2268720	1			T31	1		T32	12		T33	1
all_pins[11]	values[0x1]	1374548	1			T32	12		T36	4		T37	16
all_pins[11]	transitions[0x0=>0x1]	824402	1			T32	6		T36	3		T37	13
all_pins[11]	transitions[0x1=>0x0]	830028	1			T32	7		T36	22		T37	1
all_pins[12]	values[0x0]	2260970	1			T31	1		T32	13		T33	1
all_pins[12]	values[0x1]	1382298	1			T32	11		T36	8		T37	10
all_pins[12]	transitions[0x0=>0x1]	831292	1			T32	7		T36	8		T37	4
all_pins[12]	transitions[0x1=>0x0]	823542	1			T32	8		T36	4		T37	10
all_pins[13]	values[0x0]	2262561	1			T31	1		T32	13		T33	1
all_pins[13]	values[0x1]	1380707	1			T32	11		T36	41		T37	9
all_pins[13]	transitions[0x0=>0x1]	826399	1			T32	6		T36	34		T37	5
all_pins[13]	transitions[0x1=>0x0]	827990	1			T32	6		T36	1		T37	6
all_pins[14]	values[0x0]	2264421	1			T31	1		T32	17		T33	1
all_pins[14]	values[0x1]	1378847	1			T32	7		T36	6		T37	7
all_pins[14]	transitions[0x0=>0x1]	823733	1			T32	4		T36	2		T37	5
all_pins[14]	transitions[0x1=>0x0]	825593	1			T32	8		T36	37		T37	7
all_pins[15]	values[0x0]	2265729	1			T31	1		T32	14		T33	1
all_pins[15]	values[0x1]	1377539	1			T32	10		T36	29		T37	13
all_pins[15]	transitions[0x0=>0x1]	823823	1			T32	4		T36	24		T37	9
all_pins[15]	transitions[0x1=>0x0]	825131	1			T32	1		T36	1		T37	3
all_pins[16]	values[0x0]	2266232	1			T31	1		T32	10		T33	1
all_pins[16]	values[0x1]	1377036	1			T32	14		T36	37		T37	14
all_pins[16]	transitions[0x0=>0x1]	824906	1			T32	7		T36	19		T37	6
all_pins[16]	transitions[0x1=>0x0]	825409	1			T32	3		T36	11		T37	5
all_pins[17]	values[0x0]	2270349	1			T31	1		T32	12		T33	1
all_pins[17]	values[0x1]	1372919	1			T32	12		T36	47		T37	4
all_pins[17]	transitions[0x0=>0x1]	824662	1			T32	6		T36	22		T37	4
all_pins[17]	transitions[0x1=>0x0]	828779	1			T32	8		T36	12		T37	14
all_pins[18]	values[0x0]	2260342	1			T31	1		T32	8		T33	1
all_pins[18]	values[0x1]	1382926	1			T32	16		T36	32		T37	16
all_pins[18]	transitions[0x0=>0x1]	831050	1			T32	10		T36	11		T37	14
all_pins[18]	transitions[0x1=>0x0]	821043	1			T32	6		T36	26		T37	2
all_pins[19]	values[0x0]	2261932	1			T31	1		T32	8		T33	1
all_pins[19]	values[0x1]	1381336	1			T32	16		T36	32		T37	13
all_pins[19]	transitions[0x0=>0x1]	826372	1			T32	4		T36	15		T37	3
all_pins[19]	transitions[0x1=>0x0]	827962	1			T32	4		T36	15		T37	6
all_pins[20]	values[0x0]	2265550	1			T31	1		T32	15		T33	1
all_pins[20]	values[0x1]	1377718	1			T32	9		T36	19		T37	10
all_pins[20]	transitions[0x0=>0x1]	824912	1			T32	1		T36	7		T37	2
all_pins[20]	transitions[0x1=>0x0]	828530	1			T32	8		T36	20		T37	5
all_pins[21]	values[0x0]	2265549	1			T31	1		T32	13		T33	1
all_pins[21]	values[0x1]	1377719	1			T32	11		T36	25		T37	10
all_pins[21]	transitions[0x0=>0x1]	826147	1			T32	6		T36	14		T37	7
all_pins[21]	transitions[0x1=>0x0]	826146	1			T32	4		T36	8		T37	7
all_pins[22]	values[0x0]	2263278	1			T31	1		T32	13		T33	1
all_pins[22]	values[0x1]	1379990	1			T32	11		T36	14		T37	10
all_pins[22]	transitions[0x0=>0x1]	825488	1			T32	6		T36	8		T37	5
all_pins[22]	transitions[0x1=>0x0]	823217	1			T32	6		T36	19		T37	5
all_pins[23]	values[0x0]	2259662	1			T31	1		T32	11		T33	1
all_pins[23]	values[0x1]	1383606	1			T32	13		T36	32		T37	8
all_pins[23]	transitions[0x0=>0x1]	828668	1			T32	6		T36	26		T37	5
all_pins[23]	transitions[0x1=>0x0]	825052	1			T32	4		T36	8		T37	7
all_pins[24]	values[0x0]	2267184	1			T31	1		T32	11		T33	1
all_pins[24]	values[0x1]	1376084	1			T32	13		T36	25		T37	8
all_pins[24]	transitions[0x0=>0x1]	822927	1			T32	4		T36	12		T37	5
all_pins[24]	transitions[0x1=>0x0]	830449	1			T32	4		T36	19		T37	5
all_pins[25]	values[0x0]	2259056	1			T31	1		T32	12		T33	1
all_pins[25]	values[0x1]	1384212	1			T32	12		T36	15		T37	10
all_pins[25]	transitions[0x0=>0x1]	829861	1			T32	4		T36	10		T37	5
all_pins[25]	transitions[0x1=>0x0]	821733	1			T32	5		T36	20		T37	3
all_pins[26]	values[0x0]	2263283	1			T31	1		T32	13		T33	1
all_pins[26]	values[0x1]	1379985	1			T32	11		T36	22		T37	9
all_pins[26]	transitions[0x0=>0x1]	823273	1			T32	6		T36	17		T37	4
all_pins[26]	transitions[0x1=>0x0]	827500	1			T32	7		T36	10		T37	5
all_pins[27]	values[0x0]	2262754	1			T31	1		T32	12		T33	1
all_pins[27]	values[0x1]	1380514	1			T32	12		T36	32		T37	11
all_pins[27]	transitions[0x0=>0x1]	825839	1			T32	6		T36	23		T37	5
all_pins[27]	transitions[0x1=>0x0]	825310	1			T32	5		T36	13		T37	3
all_pins[28]	values[0x0]	2267347	1			T31	1		T32	7		T33	1
all_pins[28]	values[0x1]	1375921	1			T32	17		T36	33		T37	7
all_pins[28]	transitions[0x0=>0x1]	822680	1			T32	9		T36	21		T37	1
all_pins[28]	transitions[0x1=>0x0]	827273	1			T32	4		T36	20		T37	5
all_pins[29]	values[0x0]	2261897	1			T31	1		T32	15		T33	1
all_pins[29]	values[0x1]	1381371	1			T32	9		T36	18		T37	14
all_pins[29]	transitions[0x0=>0x1]	827589	1			T32	3		T36	8		T37	9
all_pins[29]	transitions[0x1=>0x0]	822139	1			T32	11		T36	23		T37	2
all_pins[30]	values[0x0]	2263089	1			T31	1		T32	11		T33	1
all_pins[30]	values[0x1]	1380179	1			T32	13		T36	34		T37	8
all_pins[30]	transitions[0x0=>0x1]	826628	1			T32	7		T36	23		T37	3
all_pins[30]	transitions[0x1=>0x0]	827820	1			T32	3		T36	7		T37	9
all_pins[31]	values[0x0]	2256739	1			T31	1		T32	16		T33	1
all_pins[31]	values[0x1]	1386529	1			T32	8		T36	20		T37	7
all_pins[31]	transitions[0x0=>0x1]	827821	1			T32	1		T36	10		T37	2
all_pins[31]	transitions[0x1=>0x0]	821471	1			T32	6		T36	24		T37	3