Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12337286	1			T31	529		T32	408		T33	79
all_values[1]	12337286	1			T31	529		T32	408		T33	79
all_values[2]	12337286	1			T31	529		T32	408		T33	79
all_values[3]	12337286	1			T31	529		T32	408		T33	79
all_values[4]	12337286	1			T31	529		T32	408		T33	79
all_values[5]	12337286	1			T31	529		T32	408		T33	79
all_values[6]	12337286	1			T31	529		T32	408		T33	79
all_values[7]	12337286	1			T31	529		T32	408		T33	79
all_values[8]	12337286	1			T31	529		T32	408		T33	79
all_values[9]	12337286	1			T31	529		T32	408		T33	79
all_values[10]	12337286	1			T31	529		T32	408		T33	79
all_values[11]	12337286	1			T31	529		T32	408		T33	79
all_values[12]	12337286	1			T31	529		T32	408		T33	79
all_values[13]	12337286	1			T31	529		T32	408		T33	79
all_values[14]	12337286	1			T31	529		T32	408		T33	79
all_values[15]	12337286	1			T31	529		T32	408		T33	79
all_values[16]	12337286	1			T31	529		T32	408		T33	79
all_values[17]	12337286	1			T31	529		T32	408		T33	79
all_values[18]	12337286	1			T31	529		T32	408		T33	79
all_values[19]	12337286	1			T31	529		T32	408		T33	79
all_values[20]	12337286	1			T31	529		T32	408		T33	79
all_values[21]	12337286	1			T31	529		T32	408		T33	79
all_values[22]	12337286	1			T31	529		T32	408		T33	79
all_values[23]	12337286	1			T31	529		T32	408		T33	79
all_values[24]	12337286	1			T31	529		T32	408		T33	79
all_values[25]	12337286	1			T31	529		T32	408		T33	79
all_values[26]	12337286	1			T31	529		T32	408		T33	79
all_values[27]	12337286	1			T31	529		T32	408		T33	79
all_values[28]	12337286	1			T31	529		T32	408		T33	79
all_values[29]	12337286	1			T31	529		T32	408		T33	79
all_values[30]	12337286	1			T31	529		T32	408		T33	79
all_values[31]	12337286	1			T31	529		T32	408		T33	79

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231436176

1

T31

16928

T32

13056

T33

2528

auto[1]

163356976

1

T36

1637

T40

608626

T41

911

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99632126

1

T31

16928

T32

13056

T33

2528

auto[1]

295161026

1

T36

2689

T40

108788

T41

1135

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

390420431

1

T31

16928

T32

13056

T33

2528

auto[1]

4372721

1

T40

17682

T41

189

T51

2022

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2619853	1			T31	529		T32	408		T33	79
all_values[0]	auto[0]	auto[0]	auto[1]	4567776	1			T36	40		T40	16884		T41	23
all_values[0]	auto[0]	auto[1]	auto[0]	508470	1			T36	17		T40	2416		T41	13
all_values[0]	auto[0]	auto[1]	auto[1]	4504388	1			T36	37		T40	16348		T41	8
all_values[0]	auto[1]	auto[0]	auto[1]	68592	1			T40	266		T41	5		T51	25
all_values[0]	auto[1]	auto[1]	auto[1]	68207	1			T40	286		T41	3		T51	36
all_values[1]	auto[0]	auto[0]	auto[0]	2612768	1			T31	529		T32	408		T33	79
all_values[1]	auto[0]	auto[0]	auto[1]	4533420	1			T36	42		T40	16635		T41	19
all_values[1]	auto[0]	auto[1]	auto[0]	498569	1			T36	7		T40	2129		T41	23
all_values[1]	auto[0]	auto[1]	auto[1]	4555820	1			T36	55		T40	16790		T41	10
all_values[1]	auto[1]	auto[0]	auto[1]	68427	1			T40	256		T41	4		T51	30
all_values[1]	auto[1]	auto[1]	auto[1]	68282	1			T40	278		T41	1		T51	30
all_values[2]	auto[0]	auto[0]	auto[0]	2614640	1			T31	529		T32	408		T33	79
all_values[2]	auto[0]	auto[0]	auto[1]	4535110	1			T36	46		T40	17652		T41	6
all_values[2]	auto[0]	auto[1]	auto[0]	499163	1			T36	14		T40	2110		T41	15
all_values[2]	auto[0]	auto[1]	auto[1]	4551169	1			T36	33		T40	15919		T41	12
all_values[2]	auto[1]	auto[0]	auto[1]	68936	1			T40	285		T41	4		T51	26
all_values[2]	auto[1]	auto[1]	auto[1]	68268	1			T40	253		T41	1		T51	37
all_values[3]	auto[0]	auto[0]	auto[0]	2620443	1			T31	529		T32	408		T33	79
all_values[3]	auto[0]	auto[0]	auto[1]	4527972	1			T36	67		T40	16799		T41	18
all_values[3]	auto[0]	auto[1]	auto[0]	500755	1			T36	6		T40	2158		T41	26
all_values[3]	auto[0]	auto[1]	auto[1]	4551284	1			T36	31		T40	16509		T41	8
all_values[3]	auto[1]	auto[0]	auto[1]	68210	1			T40	270		T41	7		T51	32
all_values[3]	auto[1]	auto[1]	auto[1]	68622	1			T40	306		T51	26		T42	2097
all_values[4]	auto[0]	auto[0]	auto[0]	2614008	1			T31	529		T32	408		T33	79
all_values[4]	auto[0]	auto[0]	auto[1]	4555640	1			T36	51		T40	17818		T41	43
all_values[4]	auto[0]	auto[1]	auto[0]	489372	1			T36	2		T40	2098		T41	10
all_values[4]	auto[0]	auto[1]	auto[1]	4541456	1			T36	17		T40	15623		T41	7
all_values[4]	auto[1]	auto[0]	auto[1]	68366	1			T40	317		T41	5		T51	30
all_values[4]	auto[1]	auto[1]	auto[1]	68444	1			T40	259		T41	2		T51	38
all_values[5]	auto[0]	auto[0]	auto[0]	2608800	1			T31	529		T32	408		T33	79
all_values[5]	auto[0]	auto[0]	auto[1]	4543187	1			T36	52		T40	18466		T41	15
all_values[5]	auto[0]	auto[1]	auto[0]	495644	1			T36	12		T40	1846		T41	7
all_values[5]	auto[0]	auto[1]	auto[1]	4553142	1			T36	33		T40	15191		T41	18
all_values[5]	auto[1]	auto[0]	auto[1]	68196	1			T40	263		T41	3		T51	26
all_values[5]	auto[1]	auto[1]	auto[1]	68317	1			T40	285		T41	1		T51	32
all_values[6]	auto[0]	auto[0]	auto[0]	2619182	1			T31	529		T32	408		T33	79
all_values[6]	auto[0]	auto[0]	auto[1]	4553302	1			T36	47		T40	16189		T41	20
all_values[6]	auto[0]	auto[1]	auto[0]	497465	1			T36	14		T40	2281		T41	22
all_values[6]	auto[0]	auto[1]	auto[1]	4530618	1			T36	37		T40	17264		T41	8
all_values[6]	auto[1]	auto[0]	auto[1]	69087	1			T40	261		T41	1		T51	39
all_values[6]	auto[1]	auto[1]	auto[1]	67632	1			T40	273		T41	3		T51	26
all_values[7]	auto[0]	auto[0]	auto[0]	2616635	1			T31	529		T32	408		T33	79
all_values[7]	auto[0]	auto[0]	auto[1]	4542985	1			T36	30		T40	16417		T41	8
all_values[7]	auto[0]	auto[1]	auto[0]	498994	1			T36	13		T40	2193		T41	8
all_values[7]	auto[0]	auto[1]	auto[1]	4542044	1			T36	45		T40	16754		T41	21
all_values[7]	auto[1]	auto[0]	auto[1]	68826	1			T40	270		T41	3		T51	40
all_values[7]	auto[1]	auto[1]	auto[1]	67802	1			T40	281		T41	2		T51	24
all_values[8]	auto[0]	auto[0]	auto[0]	2610674	1			T31	529		T32	408		T33	79
all_values[8]	auto[0]	auto[0]	auto[1]	4557538	1			T36	43		T40	16566		T41	23
all_values[8]	auto[0]	auto[1]	auto[0]	498308	1			T36	20		T40	2154		T41	17
all_values[8]	auto[0]	auto[1]	auto[1]	4534275	1			T36	36		T40	16695		T41	14
all_values[8]	auto[1]	auto[0]	auto[1]	68375	1			T40	266		T41	3		T51	39
all_values[8]	auto[1]	auto[1]	auto[1]	68116	1			T40	278		T41	3		T51	24
all_values[9]	auto[0]	auto[0]	auto[0]	2619033	1			T31	529		T32	408		T33	79
all_values[9]	auto[0]	auto[0]	auto[1]	4532932	1			T36	25		T40	17496		T41	26
all_values[9]	auto[0]	auto[1]	auto[0]	506285	1			T36	6		T40	2120		T41	14
all_values[9]	auto[0]	auto[1]	auto[1]	4542112	1			T36	52		T40	16090		T41	13
all_values[9]	auto[1]	auto[0]	auto[1]	68587	1			T40	266		T41	7		T51	20
all_values[9]	auto[1]	auto[1]	auto[1]	68337	1			T40	287		T41	1		T51	42
all_values[10]	auto[0]	auto[0]	auto[0]	2610830	1			T31	529		T32	408		T33	79
all_values[10]	auto[0]	auto[0]	auto[1]	4526128	1			T36	49		T40	15824		T41	4
all_values[10]	auto[0]	auto[1]	auto[0]	498470	1			T36	3		T40	2012		T41	13
all_values[10]	auto[0]	auto[1]	auto[1]	4565764	1			T36	42		T40	17158		T41	16
all_values[10]	auto[1]	auto[0]	auto[1]	68247	1			T40	268		T41	3		T51	22
all_values[10]	auto[1]	auto[1]	auto[1]	67847	1			T40	294		T41	2		T51	32
all_values[11]	auto[0]	auto[0]	auto[0]	2618606	1			T31	529		T32	408		T33	79
all_values[11]	auto[0]	auto[0]	auto[1]	4565905	1			T36	84		T40	17611		T41	10
all_values[11]	auto[0]	auto[1]	auto[0]	496384	1			T36	1		T40	2227		T41	16
all_values[11]	auto[0]	auto[1]	auto[1]	4520335	1			T36	9		T40	16016		T41	17
all_values[11]	auto[1]	auto[0]	auto[1]	67987	1			T40	278		T41	5		T51	44
all_values[11]	auto[1]	auto[1]	auto[1]	68069	1			T40	250		T41	2		T51	27
all_values[12]	auto[0]	auto[0]	auto[0]	2607722	1			T31	529		T32	408		T33	79
all_values[12]	auto[0]	auto[0]	auto[1]	4566760	1			T36	74		T40	17049		T41	26
all_values[12]	auto[0]	auto[1]	auto[0]	496266	1			T40	2035		T41	12		T51	110
all_values[12]	auto[0]	auto[1]	auto[1]	4529714	1			T36	24		T40	16414		T51	818
all_values[12]	auto[1]	auto[0]	auto[1]	68387	1			T40	290		T41	2		T51	30
all_values[12]	auto[1]	auto[1]	auto[1]	68437	1			T40	270		T41	2		T51	33
all_values[13]	auto[0]	auto[0]	auto[0]	2620584	1			T31	529		T32	408		T33	79
all_values[13]	auto[0]	auto[0]	auto[1]	4539426	1			T36	22		T40	16281		T41	25
all_values[13]	auto[0]	auto[1]	auto[0]	501152	1			T36	9		T40	2016		T41	16
all_values[13]	auto[0]	auto[1]	auto[1]	4539047	1			T36	73		T40	17511		T41	17
all_values[13]	auto[1]	auto[0]	auto[1]	68379	1			T40	307		T41	3		T51	31
all_values[13]	auto[1]	auto[1]	auto[1]	68698	1			T40	270		T41	4		T51	39
all_values[14]	auto[0]	auto[0]	auto[0]	2609892	1			T31	529		T32	408		T33	79
all_values[14]	auto[0]	auto[0]	auto[1]	4562687	1			T36	81		T40	16319		T41	33
all_values[14]	auto[0]	auto[1]	auto[0]	493837	1			T40	2179		T41	5		T51	96
all_values[14]	auto[0]	auto[1]	auto[1]	4534197	1			T36	8		T40	16798		T41	16
all_values[14]	auto[1]	auto[0]	auto[1]	68638	1			T40	276		T41	2		T51	27
all_values[14]	auto[1]	auto[1]	auto[1]	68035	1			T40	260		T41	3		T51	38
all_values[15]	auto[0]	auto[0]	auto[0]	2615769	1			T31	529		T32	408		T33	79
all_values[15]	auto[0]	auto[0]	auto[1]	4567895	1			T36	40		T40	16452		T41	12
all_values[15]	auto[0]	auto[1]	auto[0]	503531	1			T36	10		T40	2146		T41	13
all_values[15]	auto[0]	auto[1]	auto[1]	4513683	1			T36	38		T40	17057		T41	14
all_values[15]	auto[1]	auto[0]	auto[1]	68871	1			T40	246		T41	4		T51	26
all_values[15]	auto[1]	auto[1]	auto[1]	67537	1			T40	298		T41	2		T51	39
all_values[16]	auto[0]	auto[0]	auto[0]	2613048	1			T31	529		T32	408		T33	79
all_values[16]	auto[0]	auto[0]	auto[1]	4540016	1			T36	10		T40	16992		T41	17
all_values[16]	auto[0]	auto[1]	auto[0]	499617	1			T36	19		T40	1925		T41	20
all_values[16]	auto[0]	auto[1]	auto[1]	4547733	1			T36	68		T40	16750		T51	609
all_values[16]	auto[1]	auto[0]	auto[1]	68573	1			T40	280		T41	5		T51	38
all_values[16]	auto[1]	auto[1]	auto[1]	68299	1			T40	287		T41	1		T51	27
all_values[17]	auto[0]	auto[0]	auto[0]	2616741	1			T31	529		T32	408		T33	79
all_values[17]	auto[0]	auto[0]	auto[1]	4561714	1			T36	19		T40	15534		T41	13
all_values[17]	auto[0]	auto[1]	auto[0]	502852	1			T36	9		T40	1945		T41	15
all_values[17]	auto[0]	auto[1]	auto[1]	4519915	1			T36	76		T40	18299		T41	26
all_values[17]	auto[1]	auto[0]	auto[1]	68484	1			T40	255		T41	3		T51	36
all_values[17]	auto[1]	auto[1]	auto[1]	67580	1			T40	251		T41	2		T51	28
all_values[18]	auto[0]	auto[0]	auto[0]	2610348	1			T31	529		T32	408		T33	79
all_values[18]	auto[0]	auto[0]	auto[1]	4595869	1			T36	34		T40	16618		T41	24
all_values[18]	auto[0]	auto[1]	auto[0]	493842	1			T36	11		T40	2032		T41	13
all_values[18]	auto[0]	auto[1]	auto[1]	4500616	1			T36	59		T40	17039		T41	11
all_values[18]	auto[1]	auto[0]	auto[1]	68441	1			T40	257		T41	4		T51	32
all_values[18]	auto[1]	auto[1]	auto[1]	68170	1			T40	284		T41	2		T51	31
all_values[19]	auto[0]	auto[0]	auto[0]	2609586	1			T31	529		T32	408		T33	79
all_values[19]	auto[0]	auto[0]	auto[1]	4552311	1			T36	24		T40	17079		T41	15
all_values[19]	auto[0]	auto[1]	auto[0]	497397	1			T36	15		T40	2888		T41	3
all_values[19]	auto[0]	auto[1]	auto[1]	4541605	1			T36	57		T40	15436		T41	20
all_values[19]	auto[1]	auto[0]	auto[1]	68367	1			T40	275		T41	5		T51	46
all_values[19]	auto[1]	auto[1]	auto[1]	68020	1			T40	286		T41	2		T51	18
all_values[20]	auto[0]	auto[0]	auto[0]	2618084	1			T31	529		T32	408		T33	79
all_values[20]	auto[0]	auto[0]	auto[1]	4547914	1			T36	55		T40	17357		T41	21
all_values[20]	auto[0]	auto[1]	auto[0]	503437	1			T36	15		T40	1862		T41	19
all_values[20]	auto[0]	auto[1]	auto[1]	4531020	1			T36	31		T40	16333		T41	12
all_values[20]	auto[1]	auto[0]	auto[1]	68784	1			T40	284		T41	2		T51	42
all_values[20]	auto[1]	auto[1]	auto[1]	68047	1			T40	291		T41	2		T51	26
all_values[21]	auto[0]	auto[0]	auto[0]	2606048	1			T31	529		T32	408		T33	79
all_values[21]	auto[0]	auto[0]	auto[1]	4540411	1			T36	48		T40	17640		T41	26
all_values[21]	auto[0]	auto[1]	auto[0]	502705	1			T36	24		T40	2020		T41	24
all_values[21]	auto[0]	auto[1]	auto[1]	4551125	1			T36	30		T40	15690		T41	9
all_values[21]	auto[1]	auto[0]	auto[1]	68838	1			T40	269		T41	5		T51	40
all_values[21]	auto[1]	auto[1]	auto[1]	68159	1			T40	299		T41	2		T51	21
all_values[22]	auto[0]	auto[0]	auto[0]	2610701	1			T31	529		T32	408		T33	79
all_values[22]	auto[0]	auto[0]	auto[1]	4572620	1			T36	62		T40	17221		T41	7
all_values[22]	auto[0]	auto[1]	auto[0]	503601	1			T36	13		T40	2282		T41	3
all_values[22]	auto[0]	auto[1]	auto[1]	4513611	1			T36	24		T40	15835		T41	9
all_values[22]	auto[1]	auto[0]	auto[1]	69225	1			T40	263		T41	3		T51	29
all_values[22]	auto[1]	auto[1]	auto[1]	67528	1			T40	275		T41	1		T51	25
all_values[23]	auto[0]	auto[0]	auto[0]	2615628	1			T31	529		T32	408		T33	79
all_values[23]	auto[0]	auto[0]	auto[1]	4548392	1			T36	41		T40	15626		T41	25
all_values[23]	auto[0]	auto[1]	auto[0]	507321	1			T36	8		T40	2063		T41	4
all_values[23]	auto[0]	auto[1]	auto[1]	4529504	1			T36	47		T40	17765		T41	11
all_values[23]	auto[1]	auto[0]	auto[1]	68372	1			T40	295		T41	5		T51	38
all_values[23]	auto[1]	auto[1]	auto[1]	68069	1			T40	279		T41	1		T51	29
all_values[24]	auto[0]	auto[0]	auto[0]	2611112	1			T31	529		T32	408		T33	79
all_values[24]	auto[0]	auto[0]	auto[1]	4537290	1			T36	58		T40	16912		T41	12
all_values[24]	auto[0]	auto[1]	auto[0]	496117	1			T36	9		T40	1953		T41	21
all_values[24]	auto[0]	auto[1]	auto[1]	4556340	1			T36	29		T40	16585		T41	5
all_values[24]	auto[1]	auto[0]	auto[1]	68579	1			T40	299		T41	5		T51	30
all_values[24]	auto[1]	auto[1]	auto[1]	67848	1			T40	260		T41	2		T51	30
all_values[25]	auto[0]	auto[0]	auto[0]	2613954	1			T31	529		T32	408		T33	79
all_values[25]	auto[0]	auto[0]	auto[1]	4533698	1			T36	45		T40	16283		T41	13
all_values[25]	auto[0]	auto[1]	auto[0]	496695	1			T36	25		T40	2005		T41	19
all_values[25]	auto[0]	auto[1]	auto[1]	4556617	1			T36	28		T40	17463		T41	5
all_values[25]	auto[1]	auto[0]	auto[1]	68044	1			T40	260		T41	5		T51	42
all_values[25]	auto[1]	auto[1]	auto[1]	68278	1			T40	304		T41	3		T51	28
all_values[26]	auto[0]	auto[0]	auto[0]	2611765	1			T31	529		T32	408		T33	79
all_values[26]	auto[0]	auto[0]	auto[1]	4546031	1			T36	44		T40	17273		T41	20
all_values[26]	auto[0]	auto[1]	auto[0]	504808	1			T36	18		T40	2101		T41	14
all_values[26]	auto[0]	auto[1]	auto[1]	4538374	1			T36	40		T40	16070		T41	16
all_values[26]	auto[1]	auto[0]	auto[1]	68782	1			T40	270		T41	4		T51	33
all_values[26]	auto[1]	auto[1]	auto[1]	67526	1			T40	267		T41	3		T51	34
all_values[27]	auto[0]	auto[0]	auto[0]	2612086	1			T31	529		T32	408		T33	79
all_values[27]	auto[0]	auto[0]	auto[1]	4554093	1			T36	39		T40	16893		T41	28
all_values[27]	auto[0]	auto[1]	auto[0]	493029	1			T36	15		T40	1828		T41	12
all_values[27]	auto[0]	auto[1]	auto[1]	4541156	1			T36	45		T40	17000		T41	6
all_values[27]	auto[1]	auto[0]	auto[1]	68855	1			T40	271		T41	4		T51	24
all_values[27]	auto[1]	auto[1]	auto[1]	68067	1			T40	275		T41	2		T51	35
all_values[28]	auto[0]	auto[0]	auto[0]	2615211	1			T31	529		T32	408		T33	79
all_values[28]	auto[0]	auto[0]	auto[1]	4553811	1			T36	11		T40	16440		T41	14
all_values[28]	auto[0]	auto[1]	auto[0]	496463	1			T36	7		T40	2079		T41	25
all_values[28]	auto[0]	auto[1]	auto[1]	4535012	1			T36	64		T40	17061		T41	10
all_values[28]	auto[1]	auto[0]	auto[1]	68681	1			T40	313		T41	6		T51	35
all_values[28]	auto[1]	auto[1]	auto[1]	68108	1			T40	256		T41	2		T51	30
all_values[29]	auto[0]	auto[0]	auto[0]	2615978	1			T31	529		T32	408		T33	79
all_values[29]	auto[0]	auto[0]	auto[1]	4537337	1			T36	30		T40	16234		T41	13
all_values[29]	auto[0]	auto[1]	auto[0]	505331	1			T36	23		T40	2227		T41	25
all_values[29]	auto[0]	auto[1]	auto[1]	4541961	1			T36	35		T40	17122		T41	2
all_values[29]	auto[1]	auto[0]	auto[1]	68107	1			T40	288		T41	3		T51	36
all_values[29]	auto[1]	auto[1]	auto[1]	68572	1			T40	278		T41	2		T51	32
all_values[30]	auto[0]	auto[0]	auto[0]	2611494	1			T31	529		T32	408		T33	79
all_values[30]	auto[0]	auto[0]	auto[1]	4560118	1			T36	50		T40	17164		T41	7
all_values[30]	auto[0]	auto[1]	auto[0]	504435	1			T36	3		T40	1894		T41	18
all_values[30]	auto[0]	auto[1]	auto[1]	4524347	1			T36	47		T40	16497		T41	15
all_values[30]	auto[1]	auto[0]	auto[1]	68863	1			T40	277		T41	2		T51	23
all_values[30]	auto[1]	auto[1]	auto[1]	68029	1			T40	276		T41	2		T51	33
all_values[31]	auto[0]	auto[0]	auto[0]	2610917	1			T31	529		T32	408		T33	79
all_values[31]	auto[0]	auto[0]	auto[1]	4540405	1			T36	47		T40	16160		T41	18
all_values[31]	auto[0]	auto[1]	auto[0]	499671	1			T36	10		T40	2231		T41	20
all_values[31]	auto[0]	auto[1]	auto[1]	4549628	1			T36	29		T40	17232		T41	6
all_values[31]	auto[1]	auto[0]	auto[1]	68237	1			T40	284		T41	3		T51	20
all_values[31]	auto[1]	auto[1]	auto[1]	68428	1			T40	261		T41	3		T51	41

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal