Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[1]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[2]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[3]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[4]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[5]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[6]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[7]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[8]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[9]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[10]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[11]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[12]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[13]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[14]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[15]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[16]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[17]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[18]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[19]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[20]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[21]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[22]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[23]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[24]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[25]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[26]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[27]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[28]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[29]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[30]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[31]	12134561	1			T31	889		T32	408		T33	154

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230230107

1

T31

19904

T32

6402

T33

3683

auto[1]

158075845

1

T31

8544

T32

6654

T33

1245

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

311802227

1

T31

17060

T32

13056

T33

3770

auto[1]

76503725

1

T31

11388

T33

1158

T34

5285

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289947539

1

T31

16715

T32

13056

T33

2536

auto[1]

98358413

1

T31

11733

T33

2392

T34

10806

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4495873	1			T31	258		T32	225		T33	37
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3356381	1			T31	86		T32	183		T33	10
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1203064	1			T31	185		T33	14		T34	81
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1493319	1			T31	180		T33	72		T34	236
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	389935	1			T33	13		T34	36		T38	23
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1195989	1			T31	180		T33	8		T34	88
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4501016	1			T31	235		T32	193		T33	46
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3356350	1			T31	89		T32	215		T33	14
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1204704	1			T31	194		T33	16		T34	103
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1491471	1			T31	173		T33	48		T34	210
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	390778	1			T33	3		T34	21		T38	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1190242	1			T31	198		T33	27		T34	87
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4495419	1			T31	275		T32	185		T33	47
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3357081	1			T31	87		T32	223		T33	4
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1204449	1			T31	168		T33	7		T34	64
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1493648	1			T31	187		T33	82		T34	305
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	389184	1			T33	6		T34	27		T38	21
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1194780	1			T31	172		T33	8		T34	72
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4495999	1			T31	256		T32	187		T33	66
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3366214	1			T31	84		T32	221		T33	23
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1199328	1			T31	182		T33	24		T34	89
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1491215	1			T31	220		T33	13		T34	237
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	390247	1			T33	2		T34	32		T38	25
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1191558	1			T31	147		T33	26		T34	79
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4495757	1			T31	249		T32	212		T33	46
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3366772	1			T31	90		T32	196		T33	9
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1202347	1			T31	166		T33	27		T34	109
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1489120	1			T31	194		T33	42		T34	206
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	387953	1			T33	8		T34	17		T38	19
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1192612	1			T31	190		T33	22		T34	58
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4500366	1			T31	237		T32	225		T33	26
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3358724	1			T31	89		T32	183		T33	6
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1205622	1			T31	175		T33	7		T34	69
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1491517	1			T31	206		T33	77		T34	252
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	389198	1			T33	14		T34	21		T38	19
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1189134	1			T31	182		T33	24		T34	82
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4494761	1			T31	257		T32	153		T33	84
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3366394	1			T31	84		T32	255		T33	10
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1199770	1			T31	168		T33	18		T34	79
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1491137	1			T31	180		T33	19		T34	221
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	390408	1			T33	4		T34	29		T38	7
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1192091	1			T31	200		T33	19		T34	143
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4499705	1			T31	261		T32	190		T33	56
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3361287	1			T31	89		T32	218		T33	15
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1205351	1			T31	196		T33	28		T34	92
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1488827	1			T31	183		T33	26		T34	190
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	391072	1			T33	3		T34	37		T38	14
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1188319	1			T31	160		T33	26		T34	103
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4504302	1			T31	261		T32	217		T33	64
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3355321	1			T31	81		T32	191		T33	12
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1208734	1			T31	160		T33	21		T34	89
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1489740	1			T31	218		T33	30		T34	264
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	391013	1			T33	4		T34	23		T38	21
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1185451	1			T31	169		T33	23		T34	69
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4496437	1			T31	271		T32	214		T33	79
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3358555	1			T31	89		T32	194		T33	11
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1197323	1			T31	150		T33	12		T34	71
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1498008	1			T31	213		T33	43		T34	223
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	390743	1			T33	5		T34	40		T38	5
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1193495	1			T31	166		T33	4		T34	108
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4491687	1			T31	289		T32	281		T33	62
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3361254	1			T31	72		T32	127		T33	19
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1205232	1			T31	172		T33	28		T34	87
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1493967	1			T31	176		T33	28		T34	180
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	390044	1			T33	4		T34	27		T38	13
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1192377	1			T31	180		T33	13		T34	100
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4490751	1			T31	241		T32	208		T33	74
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3366933	1			T31	89		T32	200		T33	16
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1204623	1			T31	172		T33	21		T34	81
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1489633	1			T31	163		T33	16		T34	232
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	389745	1			T33	2		T34	31		T38	30
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1192876	1			T31	224		T33	25		T34	125
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4491523	1			T31	275		T32	183		T33	58
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3360600	1			T31	91		T32	225		T33	14
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1200153	1			T31	163		T33	23		T34	130
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1496107	1			T31	178		T33	28		T34	203
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	393253	1			T33	6		T34	20		T38	10
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1192925	1			T31	182		T33	25		T34	81
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4495172	1			T31	288		T32	191		T33	38
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3367049	1			T31	78		T32	217		T33	9
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1201415	1			T31	183		T33	12		T34	71
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1490686	1			T31	170		T33	55		T34	297
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	388036	1			T33	10		T34	32		T38	23
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1192203	1			T31	170		T33	30		T34	104
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4490613	1			T31	258		T32	150		T33	86
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3365743	1			T31	78		T32	258		T33	16
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1204246	1			T31	177		T33	13		T34	83
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1491101	1			T31	184		T33	27		T34	209
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	389858	1			T33	4		T34	30		T38	10
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1193000	1			T31	192		T33	8		T34	81
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4502918	1			T31	292		T32	230		T33	33
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3358524	1			T31	87		T32	178		T33	10
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1202019	1			T31	182		T33	15		T34	88
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1492384	1			T31	150		T33	72		T34	227
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	392200	1			T33	10		T34	30		T38	33
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1186516	1			T31	178		T33	14		T34	88
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4518315	1			T31	234		T32	198		T33	42
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3349282	1			T31	88		T32	210		T33	15
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1202051	1			T31	168		T33	23		T34	107
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1493323	1			T31	202		T33	37		T34	181
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	388391	1			T33	7		T34	20		T38	17
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1183199	1			T31	197		T33	30		T34	66
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4500194	1			T31	295		T32	250		T33	29
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3360865	1			T31	93		T32	158		T33	11
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1201371	1			T31	161		T33	11		T34	78
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1492683	1			T31	184		T33	54		T34	260
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	390106	1			T33	6		T34	32		T38	26
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1189342	1			T31	156		T33	43		T34	83
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4506216	1			T31	251		T32	190		T33	58
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3357805	1			T31	84		T32	218		T33	9
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1196532	1			T31	190		T33	11		T34	81
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1497297	1			T31	194		T33	48		T34	170
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	388139	1			T33	7		T34	13		T38	29
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1188572	1			T31	170		T33	21		T34	87
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4503477	1			T31	223		T32	190		T33	34
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3359014	1			T31	87		T32	218		T33	8
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1200405	1			T31	208		T33	4		T34	79
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1496115	1			T31	170		T33	72		T34	223
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	390472	1			T33	10		T34	17		T38	29
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1185078	1			T31	201		T33	26		T34	62
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4510244	1			T31	248		T32	186		T33	49
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3354930	1			T31	94		T32	222		T33	15
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1201568	1			T31	143		T33	34		T34	119
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1496922	1			T31	170		T33	47		T34	185
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	388754	1			T33	5		T34	23		T38	18
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1182143	1			T31	234		T33	4		T34	35
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4501046	1			T31	248		T32	223		T33	74
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3361300	1			T31	82		T32	185		T33	15
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1199096	1			T31	208		T33	17		T34	61
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1495962	1			T31	183		T33	38		T34	279
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	389362	1			T34	26		T38	18		T40	482
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1187795	1			T31	168		T33	10		T34	54
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4511240	1			T31	297		T32	179		T33	70
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3354552	1			T31	72		T32	229		T33	13
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1201302	1			T31	172		T34	67		T38	48
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1495140	1			T31	168		T33	44		T34	256
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	388734	1			T33	3		T34	25		T38	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1183593	1			T31	180		T33	24		T34	62
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4503844	1			T31	255		T32	225		T33	48
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3355286	1			T31	75		T32	183		T33	10
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1190246	1			T31	183		T33	10		T34	79
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1503145	1			T31	178		T33	55		T34	202
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	391865	1			T33	10		T34	26		T38	21
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1190175	1			T31	198		T33	21		T34	88
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4505234	1			T31	272		T32	226		T33	29
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3356939	1			T31	80		T32	182		T33	5
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1201145	1			T31	178		T33	19		T34	86
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1496676	1			T31	188		T33	61		T34	284
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	387863	1			T33	17		T34	40		T38	8
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1186704	1			T31	171		T33	23		T34	101
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4490268	1			T31	293		T32	164		T33	53
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3370517	1			T31	76		T32	244		T33	8
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1198649	1			T31	176		T33	5		T34	93
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1495556	1			T31	176		T33	65		T34	204
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	390568	1			T33	5		T34	21		T38	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1189003	1			T31	168		T33	18		T34	74
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4505112	1			T31	277		T32	144		T33	31
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3345342	1			T31	93		T32	264		T33	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1194961	1			T31	168		T33	10		T34	66
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1504207	1			T31	175		T33	61		T34	240
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	391031	1			T33	10		T34	21		T38	11
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1193908	1			T31	176		T33	41		T34	99
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4501007	1			T31	298		T32	214		T33	58
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3359293	1			T31	88		T32	194		T33	9
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1203459	1			T31	163		T33	16		T34	53
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1491665	1			T31	166		T33	56		T34	197
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	392156	1			T33	9		T34	18		T38	9
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1186981	1			T31	174		T33	6		T34	48
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4483806	1			T31	254		T32	198		T33	45
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3372274	1			T31	88		T32	210		T33	13
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1200719	1			T31	132		T33	29		T34	76
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1496044	1			T31	215		T33	40		T34	241
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	389227	1			T33	8		T34	25		T38	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1192491	1			T31	200		T33	19		T34	37
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4504077	1			T31	259		T32	207		T33	42
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3359468	1			T31	79		T32	201		T33	11
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1200959	1			T31	160		T34	80		T38	90
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1490645	1			T31	182		T33	56		T34	178
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	392116	1			T33	11		T34	27		T38	16
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1187296	1			T31	209		T33	34		T34	83
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4497315	1			T31	267		T32	183		T33	58
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3359711	1			T31	81		T32	225		T33	8
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1199986	1			T31	185		T33	14		T34	45
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1496191	1			T31	188		T33	46		T34	296
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	391044	1			T33	10		T34	34		T38	18
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1190314	1			T31	168		T33	18		T34	118
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4500042	1			T31	277		T32	181		T33	57
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3366324	1			T31	87		T32	227		T33	8
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1196890	1			T31	166		T33	11		T34	62
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1495201	1			T31	185		T33	46		T34	212
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	390260	1			T33	14		T34	18		T38	9
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1185844	1			T31	174		T33	18		T34	102

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal