Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[1]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[2]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[3]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[4]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[5]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[6]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[7]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[8]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[9]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[10]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[11]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[12]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[13]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[14]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[15]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[16]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[17]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[18]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[19]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[20]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[21]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[22]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[23]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[24]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[25]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[26]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[27]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[28]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[29]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[30]	12134561	1			T31	889		T32	408		T33	154
bins_for_gpio_bits[31]	12134561	1			T31	889		T32	408		T33	154

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230230107

1

T31

19904

T32

6402

T33

3683

auto[1]

158075845

1

T31

8544

T32

6654

T33

1245

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230221429

1

T31

19898

T32

6402

T33

3683

auto[1]

158084523

1

T31

8550

T32

6654

T33

1245

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6978930	1			T31	578		T32	225		T33	120
bins_for_gpio_bits[0]	auto[0]	auto[1]	213098	1			T31	45		T33	3		T34	20
bins_for_gpio_bits[0]	auto[1]	auto[0]	213326	1			T31	45		T33	3		T34	20
bins_for_gpio_bits[0]	auto[1]	auto[1]	4729207	1			T31	221		T32	183		T33	28
bins_for_gpio_bits[1]	auto[0]	auto[0]	6984398	1			T31	550		T32	193		T33	106
bins_for_gpio_bits[1]	auto[0]	auto[1]	212537	1			T31	52		T33	4		T34	16
bins_for_gpio_bits[1]	auto[1]	auto[0]	212793	1			T31	52		T33	4		T34	16
bins_for_gpio_bits[1]	auto[1]	auto[1]	4724833	1			T31	235		T32	215		T33	40
bins_for_gpio_bits[2]	auto[0]	auto[0]	6980268	1			T31	581		T32	185		T33	134
bins_for_gpio_bits[2]	auto[0]	auto[1]	212986	1			T31	49		T33	2		T34	20
bins_for_gpio_bits[2]	auto[1]	auto[0]	213248	1			T31	49		T33	2		T34	20
bins_for_gpio_bits[2]	auto[1]	auto[1]	4728059	1			T31	210		T32	223		T33	16
bins_for_gpio_bits[3]	auto[0]	auto[0]	6974124	1			T31	617		T32	187		T33	100
bins_for_gpio_bits[3]	auto[0]	auto[1]	212150	1			T31	40		T33	3		T34	14
bins_for_gpio_bits[3]	auto[1]	auto[0]	212418	1			T31	41		T33	3		T34	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	4735869	1			T31	191		T32	221		T33	48
bins_for_gpio_bits[4]	auto[0]	auto[0]	6974183	1			T31	563		T32	212		T33	110
bins_for_gpio_bits[4]	auto[0]	auto[1]	212785	1			T31	46		T33	5		T34	13
bins_for_gpio_bits[4]	auto[1]	auto[0]	213041	1			T31	46		T33	5		T34	13
bins_for_gpio_bits[4]	auto[1]	auto[1]	4734552	1			T31	234		T32	196		T33	34
bins_for_gpio_bits[5]	auto[0]	auto[0]	6984715	1			T31	573		T32	225		T33	104
bins_for_gpio_bits[5]	auto[0]	auto[1]	212554	1			T31	45		T33	6		T34	18
bins_for_gpio_bits[5]	auto[1]	auto[0]	212790	1			T31	45		T33	6		T34	18
bins_for_gpio_bits[5]	auto[1]	auto[1]	4724502	1			T31	226		T32	183		T33	38
bins_for_gpio_bits[6]	auto[0]	auto[0]	6972511	1			T31	558		T32	153		T33	120
bins_for_gpio_bits[6]	auto[0]	auto[1]	212906	1			T31	47		T33	1		T34	21
bins_for_gpio_bits[6]	auto[1]	auto[0]	213157	1			T31	47		T33	1		T34	21
bins_for_gpio_bits[6]	auto[1]	auto[1]	4735987	1			T31	237		T32	255		T33	32
bins_for_gpio_bits[7]	auto[0]	auto[0]	6981792	1			T31	592		T32	190		T33	105
bins_for_gpio_bits[7]	auto[0]	auto[1]	211766	1			T31	48		T33	5		T34	21
bins_for_gpio_bits[7]	auto[1]	auto[0]	212091	1			T31	48		T33	5		T34	21
bins_for_gpio_bits[7]	auto[1]	auto[1]	4728912	1			T31	201		T32	218		T33	39
bins_for_gpio_bits[8]	auto[0]	auto[0]	6990842	1			T31	587		T32	217		T33	110
bins_for_gpio_bits[8]	auto[0]	auto[1]	211642	1			T31	51		T33	5		T34	14
bins_for_gpio_bits[8]	auto[1]	auto[0]	211934	1			T31	52		T33	5		T34	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	4720143	1			T31	199		T32	191		T33	34
bins_for_gpio_bits[9]	auto[0]	auto[0]	6978885	1			T31	590		T32	214		T33	133
bins_for_gpio_bits[9]	auto[0]	auto[1]	212577	1			T31	44		T33	1		T34	16
bins_for_gpio_bits[9]	auto[1]	auto[0]	212883	1			T31	44		T33	1		T34	16
bins_for_gpio_bits[9]	auto[1]	auto[1]	4730216	1			T31	211		T32	194		T33	19
bins_for_gpio_bits[10]	auto[0]	auto[0]	6978046	1			T31	590		T32	281		T33	115
bins_for_gpio_bits[10]	auto[0]	auto[1]	212606	1			T31	47		T33	3		T34	16
bins_for_gpio_bits[10]	auto[1]	auto[0]	212840	1			T31	47		T33	3		T34	16
bins_for_gpio_bits[10]	auto[1]	auto[1]	4731069	1			T31	205		T32	127		T33	33
bins_for_gpio_bits[11]	auto[0]	auto[0]	6972132	1			T31	521		T32	208		T33	106
bins_for_gpio_bits[11]	auto[0]	auto[1]	212627	1			T31	55		T33	5		T34	20
bins_for_gpio_bits[11]	auto[1]	auto[0]	212875	1			T31	55		T33	5		T34	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	4736927	1			T31	258		T32	200		T33	38
bins_for_gpio_bits[12]	auto[0]	auto[0]	6975142	1			T31	575		T32	183		T33	104
bins_for_gpio_bits[12]	auto[0]	auto[1]	212349	1			T31	41		T33	5		T34	16
bins_for_gpio_bits[12]	auto[1]	auto[0]	212641	1			T31	41		T33	5		T34	16
bins_for_gpio_bits[12]	auto[1]	auto[1]	4734429	1			T31	232		T32	225		T33	40
bins_for_gpio_bits[13]	auto[0]	auto[0]	6974811	1			T31	598		T32	191		T33	101
bins_for_gpio_bits[13]	auto[0]	auto[1]	212159	1			T31	43		T33	4		T34	19
bins_for_gpio_bits[13]	auto[1]	auto[0]	212462	1			T31	43		T33	4		T34	19
bins_for_gpio_bits[13]	auto[1]	auto[1]	4735129	1			T31	205		T32	217		T33	45
bins_for_gpio_bits[14]	auto[0]	auto[0]	6973325	1			T31	569		T32	150		T33	124
bins_for_gpio_bits[14]	auto[0]	auto[1]	212350	1			T31	50		T33	2		T34	16
bins_for_gpio_bits[14]	auto[1]	auto[0]	212635	1			T31	50		T33	2		T34	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	4736251	1			T31	220		T32	258		T33	26
bins_for_gpio_bits[15]	auto[0]	auto[0]	6984601	1			T31	579		T32	230		T33	118
bins_for_gpio_bits[15]	auto[0]	auto[1]	212434	1			T31	45		T33	2		T34	12
bins_for_gpio_bits[15]	auto[1]	auto[0]	212720	1			T31	45		T33	2		T34	12
bins_for_gpio_bits[15]	auto[1]	auto[1]	4724806	1			T31	220		T32	178		T33	32
bins_for_gpio_bits[16]	auto[0]	auto[0]	7001507	1			T31	553		T32	198		T33	97
bins_for_gpio_bits[16]	auto[0]	auto[1]	211936	1			T31	50		T33	5		T34	13
bins_for_gpio_bits[16]	auto[1]	auto[0]	212182	1			T31	51		T33	5		T34	13
bins_for_gpio_bits[16]	auto[1]	auto[1]	4708936	1			T31	235		T32	210		T33	47
bins_for_gpio_bits[17]	auto[0]	auto[0]	6981564	1			T31	601		T32	250		T33	88
bins_for_gpio_bits[17]	auto[0]	auto[1]	212396	1			T31	39		T33	6		T34	15
bins_for_gpio_bits[17]	auto[1]	auto[0]	212684	1			T31	39		T33	6		T34	16
bins_for_gpio_bits[17]	auto[1]	auto[1]	4727917	1			T31	210		T32	158		T33	54
bins_for_gpio_bits[18]	auto[0]	auto[0]	6987284	1			T31	592		T32	190		T33	113
bins_for_gpio_bits[18]	auto[0]	auto[1]	212519	1			T31	43		T33	4		T34	14
bins_for_gpio_bits[18]	auto[1]	auto[0]	212761	1			T31	43		T33	4		T34	14
bins_for_gpio_bits[18]	auto[1]	auto[1]	4721997	1			T31	211		T32	218		T33	33
bins_for_gpio_bits[19]	auto[0]	auto[0]	6987675	1			T31	545		T32	190		T33	106
bins_for_gpio_bits[19]	auto[0]	auto[1]	212038	1			T31	55		T33	4		T34	9
bins_for_gpio_bits[19]	auto[1]	auto[0]	212322	1			T31	56		T33	4		T34	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	4722526	1			T31	233		T32	218		T33	40
bins_for_gpio_bits[20]	auto[0]	auto[0]	6995626	1			T31	515		T32	186		T33	129
bins_for_gpio_bits[20]	auto[0]	auto[1]	212819	1			T31	46		T33	1		T34	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	213108	1			T31	46		T33	1		T34	9
bins_for_gpio_bits[20]	auto[1]	auto[1]	4713008	1			T31	282		T32	222		T33	23
bins_for_gpio_bits[21]	auto[0]	auto[0]	6983341	1			T31	590		T32	223		T33	127
bins_for_gpio_bits[21]	auto[0]	auto[1]	212461	1			T31	49		T33	2		T34	11
bins_for_gpio_bits[21]	auto[1]	auto[0]	212763	1			T31	49		T33	2		T34	12
bins_for_gpio_bits[21]	auto[1]	auto[1]	4725996	1			T31	201		T32	185		T33	23
bins_for_gpio_bits[22]	auto[0]	auto[0]	6994559	1			T31	589		T32	179		T33	110
bins_for_gpio_bits[22]	auto[0]	auto[1]	212806	1			T31	48		T33	4		T34	15
bins_for_gpio_bits[22]	auto[1]	auto[0]	213123	1			T31	48		T33	4		T34	15
bins_for_gpio_bits[22]	auto[1]	auto[1]	4714073	1			T31	204		T32	229		T33	36
bins_for_gpio_bits[23]	auto[0]	auto[0]	6984518	1			T31	574		T32	225		T33	108
bins_for_gpio_bits[23]	auto[0]	auto[1]	212478	1			T31	42		T33	5		T34	15
bins_for_gpio_bits[23]	auto[1]	auto[0]	212717	1			T31	42		T33	5		T34	15
bins_for_gpio_bits[23]	auto[1]	auto[1]	4724848	1			T31	231		T32	183		T33	36
bins_for_gpio_bits[24]	auto[0]	auto[0]	6990039	1			T31	593		T32	226		T33	103
bins_for_gpio_bits[24]	auto[0]	auto[1]	212753	1			T31	44		T33	6		T34	19
bins_for_gpio_bits[24]	auto[1]	auto[0]	213016	1			T31	45		T33	6		T34	19
bins_for_gpio_bits[24]	auto[1]	auto[1]	4718753	1			T31	207		T32	182		T33	39
bins_for_gpio_bits[25]	auto[0]	auto[0]	6971249	1			T31	598		T32	164		T33	119
bins_for_gpio_bits[25]	auto[0]	auto[1]	212943	1			T31	47		T33	4		T34	16
bins_for_gpio_bits[25]	auto[1]	auto[0]	213224	1			T31	47		T33	4		T34	16
bins_for_gpio_bits[25]	auto[1]	auto[1]	4737145	1			T31	197		T32	244		T33	27
bins_for_gpio_bits[26]	auto[0]	auto[0]	6990532	1			T31	576		T32	144		T33	96
bins_for_gpio_bits[26]	auto[0]	auto[1]	213490	1			T31	44		T33	6		T34	19
bins_for_gpio_bits[26]	auto[1]	auto[0]	213748	1			T31	44		T33	6		T34	19
bins_for_gpio_bits[26]	auto[1]	auto[1]	4716791	1			T31	225		T32	264		T33	46
bins_for_gpio_bits[27]	auto[0]	auto[0]	6983669	1			T31	581		T32	214		T33	128
bins_for_gpio_bits[27]	auto[0]	auto[1]	212196	1			T31	46		T33	2		T34	11
bins_for_gpio_bits[27]	auto[1]	auto[0]	212462	1			T31	46		T33	2		T34	11
bins_for_gpio_bits[27]	auto[1]	auto[1]	4726234	1			T31	216		T32	194		T33	22
bins_for_gpio_bits[28]	auto[0]	auto[0]	6967400	1			T31	552		T32	198		T33	112
bins_for_gpio_bits[28]	auto[0]	auto[1]	212897	1			T31	49		T33	2		T34	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	213169	1			T31	49		T33	2		T34	8
bins_for_gpio_bits[28]	auto[1]	auto[1]	4741095	1			T31	239		T32	210		T33	38
bins_for_gpio_bits[29]	auto[0]	auto[0]	6983101	1			T31	559		T32	207		T33	94
bins_for_gpio_bits[29]	auto[0]	auto[1]	212331	1			T31	41		T33	4		T34	10
bins_for_gpio_bits[29]	auto[1]	auto[0]	212580	1			T31	42		T33	4		T34	10
bins_for_gpio_bits[29]	auto[1]	auto[1]	4726549	1			T31	247		T32	201		T33	52
bins_for_gpio_bits[30]	auto[0]	auto[0]	6980556	1			T31	596		T32	183		T33	115
bins_for_gpio_bits[30]	auto[0]	auto[1]	212679	1			T31	44		T33	3		T34	17
bins_for_gpio_bits[30]	auto[1]	auto[0]	212936	1			T31	44		T33	3		T34	17
bins_for_gpio_bits[30]	auto[1]	auto[1]	4728390	1			T31	205		T32	225		T33	33
bins_for_gpio_bits[31]	auto[0]	auto[0]	6979464	1			T31	583		T32	181		T33	110
bins_for_gpio_bits[31]	auto[0]	auto[1]	212372	1			T31	45		T33	4		T34	17
bins_for_gpio_bits[31]	auto[1]	auto[0]	212669	1			T31	45		T33	4		T34	17
bins_for_gpio_bits[31]	auto[1]	auto[1]	4730056	1			T31	216		T32	227		T33	36